ECE 2300
Digital Logic & Computer Organization
Spring 2018
Two’s Complement Representation
Binary Arithmetic
Lecture 12: 1
Announcements
• HW4 due tomorrow
• HW5 will be released tonight
• Lab 3 report due next Monday/Tuesday
– Form group before the submission
• A batch of raw quiz scores released on CMS
Lecture 12: 2
Example: Setup Time Analysis
X
S F
Y
CLOCK
• Assumptions:
(1) Uniform gate delay = 1ns
(2) FF propagation delay = 1ns
(3) Setup time = 3ns, hold time = 2ns
• What’s the best achievable cycle time?
tclk >= tffpd(max) + tcomb(max) + tsetup = 1 + 3 + 3 = 7ns
Lecture 12: 3
Example: Hold Time Analysis with Clock Skew
combinational
FF1 logic FF2
CLOCK
Clock may arrive at FF2 up to 3ns later than FF1
Prop Delay (ns) Setup Hold Time
min max Time (ns) (ns)
FF 1 7 3 1
Comb 3 9 - -
• Hold time at FF2 met?
tffpd(min) + tcomb(min) >= thold + tskew(max)
1 + 3 >= 1 + 3
The hold time constraint is met
Lecture 12: 4
Timing Analysis Discussions
• To achieve a higher clock frequency, would you
prefer
– a smaller hold time or a larger one?
– a smaller setup time or a larger one?
– a negative clock skew or a positive one?
• a smaller skew or a larger one?
Lecture 12: 5
Course Content
• Binary numbers and logic gates
• Boolean algebra and combinational logic
• Sequential logic and state machines
• Binary arithmetic
• Memories
• Instruction set architecture
• Processor organization
• Caches and virtual memory
• Input/output
Lecture 12: 6
Unsigned Binary Integers
• An n-bit unsigned number represents 2n integer values
– From 0 to 2n-1
22 21 20 value
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
Lecture 12: 7
Unsigned Binary Fractions
• For the binary number bn-1bn-2…b1b0.b-1b-2…b-m
the decimal number is
n-1
D = S bi•2i
i=-m
• Examples
101.0012 = ?
Lecture 12: 8
Unsigned Binary Addition
• Just like base-10
– Add from right to left, propagating carry
carry
10010 (18) 10010 (18) 01111 (15)
+ 01001 (9) + 01011 (11) + 00011 (3)
(27) (29) 1001 0 (18)
10111 (23)
+ 111 (7)
11 11 0 (30)
Lecture 12: 9
Signed Magnitude Representation
• Most significant bit is used as a sign bit
– Sign bit of 0 for positive (0101 = 5)
– Sign bit of 1 for negative (1101 = -5)
• Range is from -(2n-1-1) to (2n-1-1) for an n-bit
number
• Two representations for zero (+0 and -0)
• Does ordinary binary addition still work?
0010 (2)
+ 1010 (-2)
1100 (not 0)
Lecture 12: 10
Another Encoding of Binary Numbers
000
0
111 001
-1 1
110 -2 2 010
101 -3 3 011
-4
100 Wrap-around point
Lecture 12: 11
Two’s Complement Representation
• MSB has weight -2n-1
• Range of an n-bit number: -2n-1 through 2n-1-1
– Most negative number (-2n-1) has no positive
counterpart -22 21 20
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 -4
1 0 1 -3
1 1 0 -2
1 1 1 -1
Lecture 12: 12
Two’s Complement Addition
• Procedure for addition is the same as
unsigned addition regardless of the signs of
the numbers
011 (3)
+ 101 (-3)
000 (0)
Lecture 12: 13
Sign Extension
• Replicate the MSB (sign bit)
4-bit 8-bit
0100 (4) 00000100 (still 4)
1100 (-4) 11111100 (still -4)
• Necessary for adding a two’s complement
numbers of different lengths
Lecture 12: 14
Fixed Size Representation
• Microprocessors usually represent numbers as fixed size
n-bit values
• Result of adding two n-bit integers is stored as n bits
• Integers are typically 32 or 64 bits (words)
– 4 or 8 bytes
– byte = 8 bits
Lecture 12: 15
Fixed Size Addition
• Examples with n = 4
2 0010 2 0010 -2 1110
+ 3 0011 + -3 1101 + 6 0110
5 0101 -1 1111 4 0100
-2 1110 7 0111 -7 1001
+ -6 1010 + 6 0110 + -4 1100
-8 1000 -3 1101 5 0101
Something went wrong!
Lecture 12: 16
Overflow
• If operands are too big, sum cannot be
represented as n-bit 2’s complement number
01000 (8) 11000 (-8)
+ 01001 (9) + 10111 (-9)
10001 (-15) 01111 (+15)
• Overflow occurs if
– Signs of both operands are the same, and
– Sign of sum is different
• Another test (easy to do in hardware)
– Carry into MSB does not equal carry out
Lecture 12: 17
Did Overflow Occur?
1 11 1 111 1 1
01110010 11110010
+ 01010011 + 01010011
11000101 01000101
YES NO
Lecture 12: 18
Two’s Complement Representation
• Positive numbers and zero are same as
unsigned binary representation
• To get two’s complement negative notation of
an integer
– Flip every bit first
– Then add one
011 (3) 01001 (9)
100 (1’s comp) 10110 (1’s comp)
+ 1 + 1
101 (-3) 10111 (-9)
Lecture 12: 19
(-X) = (X’+1)
• To get two’s complement negative notation of
an integer
– Flip every bit first 000
– Then add one 0
111 001
011 (3) -1 1
100 (1’s comp)
110 -2 2 010
+ 1
101 (-3)
101 -3 3 011
X’+1 X’
-4
100
Lecture 12: 20
Two’s Complement (2’s C) Shortcut
• To get -X
– Copy bits from right to left up to and including the
first “1”
– Flip remaining bits to the left
011010000 011010000
100101111 (1’s comp) (flip) (copy)
+ 1
100110000 100110000
Lecture 12: 21
Converting Binary (2’s C) to Decimal
1. If MSB = 1, take two’s complement to get a
positive number
2. Add powers of 2 for bit positions that have a “1”
3. If original number was negative,
n 2n
add a minus sign 0 1
1 2
X = 11100110two 2 4
-X = 00011010 3 8
4 16
= 24+23+21 = 16+8+2 5 32
= 26ten 6 64
7 128
X = -26ten 8 256
9 512
Assuming 8-bit 2’s complement numbers 10 1024
Lecture 12: 22
Converting Decimal to Binary (2’s C)
First Method: Division
1. Change to nonnegative decimal number
2. Divide by two – remainder is least significant bit
3. Keep dividing by two until answer is zero,
recording remainders from right (LSB) to left
4. Append a zero as the MSB;
if original number X was negative, return X’+1
X = 104ten 104/2 = 52 r0 bit 0 = 0
52/2 = 26 r0 bit 1 = 0
26/2 = 13 r0 bit 2 = 0
13/2 = 6 r1 bit 3 = 1
6/2 = 3 r0 bit 4 = 0
3/2 = 1 r1 bit 5 = 1
1/2 = 0 r1 bit 6 = 1
X = 01101000two
Lecture 12: 23
Converting Decimal to Binary (2’s C)
Second Method: Subtract Powers of Two
n 2n
1. Change to nonnegative decimal number
0 1
2. Subtract largest power of two 1 2
less than or equal to number 2 4
3. Put a one in the corresponding bit position 3 8
4. Keep subtracting until result is zero 4 16
5 32
5. Append a zero as MSB;
6 64
if original was X negative, return X’+1
7 128
8 256
X = 104ten 104 - 64 = 40 bit 6 = 1 9 512
40 - 32 = 8 bit 5 = 1 10 1024
8-8 = 0 bit 3 = 1
X = 01101000two
Lecture 12: 24
Full Adder (1 bit Adder with Carry)
• Inputs: A, B and Cin (carry-in)
• Outputs: S (sum) and Cout (carry-out)
A B Cin S Cout
A
0 0 0 0 0 B S
0 0 1 1 0 Cin
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
Cout
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Lecture 12: 25
Full-Adder Circuit Symbol
A
B S
Cin A B
Cout Cin
S
Cout
OR
FA
Lecture 12: 26
Before Next Class
• H&H 5.5
Next Time
More Binary Arithmetic
ALU
Lecture 12: 27
