MODULE 2:

MODULE –II

I. FLOATING POINT ARITHMETIC

In IEEE single precision format a floating point number is represented using 32
bits. The MSB represents the sign, 1 if negative and 0 if positive. The next eight bits
represents the exponent of the scale factor. The exponent is stored in the excess 127
format. The value stored is an unsigned integer E’ = E + 127. The last 23 bits represent
the mantissa. The number is stored in this format in the normalized form. So the MSB of
the mantissa will always be 1 and this bit is not explicitly represented. The 23 bits stored
in the mantissa
field represent the fractional part of the mantissa

For e.g. 1.001010…0 * 2-87 is represented as

0 00101000 001010………………….0

For excess-127 format, 0 ≤ E’ ≤ 255. However, 0 and 255 are used to represent special
value. So actually 1 ≤ E’ ≤ 254. That means -126 ≤ E ≤ 127.
Single precision uses 32-bit. The value range is from 2-126 to 2+127.
Double precision used 64-bit. The value range is from 2-1022 to 2+1023. Note the
following aspects
If a number is not normalized, it can always be put in normalized form by shifting the
fraction and adjusting the exponent.
As computations proceed, a number that does not fall in the represent able
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range of normal numbers might be generated

It requires an exponent less than -126 (underflow) or greater than +127

(overflow). Both are exceptions that need to be considered

Add/Subtract Rule

1. Choose the number with the smallest exponent and shift its mantissa right n times
where n is the difference between the exponents.
2. Set the exponent of the result as that of the larger exponent.
3. Perform addition or subtraction on the mantissa and determine the sign of the result.
4. Normalize the resulting value is necessary.

Example: Consider 2.9400 * 10 2 +

4.3100 * 10 4
↓
4.3100 * 10 4 +
.0294 * 10 4
--------------------------------------------------
4.3394 * 10 4

1.Multiply Rule

1. Add the exponents and subtract 127.

2. Multiply the mantissas and determine the sign of the result.

3. Normalize the resulting value is necessary.

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2.Divide Rule

1. Subtract the exponents and add 127.

2. Divide the mantissas and determine the sign of the result.

3. Normalize the resulting value is necessary

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Flow Chart

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Flow Chart (Multiplication)

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Flow Chart(DIVIDE )

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The hardware circuit for Floating point addition-subtraction unit is given

below.

In step 1, compare the exponent to determine how far to shift the smaller
exponent. Shift count value n= EA’-EB’ is determined by the subtractor unit. The value n
is sent to the shifter unit. The sign of the difference determine which mantissa to be
shifted. The sign sent to the Swap circuit. If the sign is 0 then EA’> EB” and mantissa
MA and MB are sent straight through the swap network. MB sent to the shifter unit and
shift n times right. MA sent directly to the adder/sub unit. If the sign is 1 then EA’< EB’
and mantissa swapped and sent to the shifter.

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In step 2, the exponent of the result E’ is determined as EA’ if EA’>=EB’ or EB’

if EA’<EB’ based on the difference resulting from comparing exponent in step 1.
In step 3, the control logic determines whether the mantissas are to be added or
subtracted. This is decided by the sign of the operands and the operation that is to
be performed on the operands. The control logic also determines the sign of the result SR.
In step 4, normalize the result. The number of leading zeros in M determines the number
of bit shift X to be applied to M. The normalized value is rounded to generate the 23 bit
mantissa MR. The value X is subtracted from E’ to generate the correct exponent ER’.

II.ALU DESIGN

ALU is a multi operation combinational circuit. It can perform a set of arithmetic

and logic operations using K select lines. Using K select lines it can perform 2k
operations. Consider the block diagram of 4 bit ALU.

A ns B are the inputs. S2= mode select ( select the arithmetic or logic operation)
S1 S0 specifies the operation to be performed. S0 S1 and Cin combine to generate 8
operations.
Design of ALU has 3 stages.

1)Design the arithmetic section independent of the logic section

2) Determine the logic operations obtained from the arithmetic circuit in step 1,assuming
that the input carries to all stages are 0.

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3) Modify the arithmetic circuit to obtain the required logic operations

1) Design of Arithmetic circuit

The basic component in the ALU is a Parallel adder.Consider the above figure we obtain
the following 8 functions

1.1) Design of arithmetic logic circuit

S1 S0 Output Operation
0 0 Fi= Ai + Bi OR
0 1 Fi = Ai XOR Bi XOR
1 0 Fi= AiBi AND

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1 1 F= Ai NOT

2 Arithmetic logic Unit

• A 4bit arithmetic circuit that perform 8 arithmetic operation is show

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• The 4 full-adder (FA) circuit constitute the parallel adder

• The carry into the first stage is the input carry

• The carry out of the fourth stage is the output carry.

• All other carries are connected internally from one stage to the next
• The selection variables are s1, s0 and Cin
• Variables s1 and S0 control all of the B inputs to the full-adder circuits
• The A inputs go directly to the other inputs of the full adders

V. DECIMALARITHMETIC
ADDITION,SUBTRACTION,MULTIPLICATION AND DIVISION

1.Addition and Subtracion Operation

Addition and subtraction of decimals is like adding and subtracting whole numbers. The
only thing we must remember is to line up the place values correctly. The easiest way to
do that is to line up the decimal points

Example
 Here is an example of adding 12.35 and 5.287. 12.35+
Notice how the decimal points are lined up. 5.287
_________
17.637
 Here is an example of subtracting 2.28 from
12.993. Notice how the decimal points are lined up.
12.993 +
2.28
---------------------
15.273

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Detailed Example of Addition

Add the following numbers 1.19 and .16

The answer to this is: 1.19 + .16 = 1.35.

 First line the numbers up in a column, lining up the

decimal points.

 Add down the columns, starting at the right. Notice that 9

+ 6 = 15, so we need to carry a 1 to the tenths column.

 Continue to add down the columns, moving from right to

left.

Detailed Example of Subtraction

Subtract 1.387 from 12.17.

The answer to this is: 12.17 - 1.387 = 10.783

 First line the numbers up in a column, lining up

the decimal points. Since the number 1.387 has
three digits after the decimal point, we add a zero
on the end of 12.17 so it also has three digits
showing past the decimal point.

 Subtract down the columns, starting at the right.

Notice that in the thousandths column 7 > 0. We
must "borrow" from the hundredths column.

 When we move to the hundredths column, we

notice that 8 > 6. We must "borrow" from the

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tenths column.

 Continue to subtract down the columns, moving

from right to left. Again, we need to borrow from
the ones place to be able to subtract the tenths.

Multiplication of Decimals

When multiplying numbers with decimals, we first multiply them as if they were whole
numbers. Then, the placement of the number of decimal places in the result is equal to the
sum of the number of decimal places of the numbers being multiplied.

For example, if we multiply 2.3 times 4.5, each

number has one digit to the right of the decimal, so
each has one decimal place. When they are
multiplied, the result will have two digits to the right
of the decimal, or two decimal places. Now let's
look at a detailed example of multiplying two
number with decimals.

Detailed Example of Multiplication

Multiply 12.3 by 3.54.
The answer is 43.542

 When multiplying multi-digit numbers, we start

with the digit at the furthest right of the bottom
number and multiply that by each of the digits of
the top number.

 Multiply the second digit from the right of the

bottom number by the top. Notice how this
second number is offset below the first. Do this
for each digit of the bottom number, moving
from right to left.

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 Continue doing this for each digit of the bottom

number, moving from right to left. Remember to
offset each number as you multiply.

 Now add the numbers up going down the

columns.

Division of Decimals

Division with decimals is easier to understand if the divisor (the dividend is divided by
the divisor) is a whole number.

 If the divisor has a decimal in it, we can make it

a whole number by moving the decimal point the
appropriate number of places to the right.

 However, if you shift the decimal point to the

right in the divisor, you must also do this for the
dividend.

 Once you have moved the decimal point so the

divisor is a whole number, you can do the
division.

Now let's look at a detailed example of dividing with decimals.

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Detailed Example of Division

Divide 0.2334 by .004
The answer is 58.35

 Place the numbers in the division equation

format.

 Move the decimal point in both the divisor and

dividend three places to the right so that the
divisor is a whole number.

 Begin the division with 4 into 23 (since 4 cannot

go into 2). This gives us 5 with a remainder of 3.

 Now bring down the next 3, so we must divide

33 by 4.

 Continue on with the division. Notice that you

must add a zero on the end of the dividend to
finish the division.

The decimal point in the result is directly above the

decimal point in the dividend.

1.2 Performing an arithmetic operation

 The ALU is a combinational circuit that has no internal storage.
 ALU gets the two operands from MUX and bus. The result is temporarily stored
in register Z.
 What is the sequence of operations to add the contents of register R1 to those of
R2 and store the result in R3?
o R1out, Yin
o R2out, SelectY, Add, Zin
o Zout, R3in

1.3 Fetching a word from memory

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 Address into MAR; issue Read operation; data into MDR.

 The response time of each memory access varies (cache miss, memory-mapped
I/O).
 To accommodate this, the processor waits until it receives an indication that the
requested operation has been completed (Memory-Function-Completed, MFC).

Memory-bus Internal processor

data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure 7.4. Connecti on and control signals forgister

re MD R.

 Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]

 Move (R1), R2
1. R1out, MARin, Read
2. MDRinE, WMFC
3. MDRout, R2in

Example : ADD (R3), R1

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 Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.

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2. EXECUTION OF BRANCH INSTRUCTION

 A branch instruction replaces the contents of PC with the branch target address,
which is usually obtained by adding an offset X given in the branch instruction.

 The offset X is usually the difference between the branch target address and the
address immediately following the branch instruction.

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Step Action

1 PCout , MAR in , Read, Select4,Add, Z in

2 Zout , PCin , Yin , WMF C
3 MDR out , IR in
4 Offset-field-of-IRout, Add, Z in
5 Z out , PCin , End

3. HARDWIRED CONTROL

To execute instructions, the processor must have some means of generating the
control signals needed in the proper sequence. The two categories are hardwired
control and microprogrammed control. Hardwired system can operate at high speed;
but with little flexibility.

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 CLK
Clock Control step Reset

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counter

Step decoder

T 1 T2 Tn

INS1
External
INS2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

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In a hardwired organization, the control logic is implemented with gates, flip-flops,

decoders and other digital circuits. Hardwired control received its name because the
control was implemented in hardware and could not be easily changed. A hardwired
control as the name implies, requires changes in the wiring if the design has to be
modified or changed. The control unit is implemented as a state machine, with
combinatorial circuits generating each of the control functions on the basis of the current
state and certain variables such as the op-code of the user instruction undergoing
execution. Its input logic signals are transformed into output logic signals which are the
control signals. A hardwired control unit must contain complex logic for sequencing
through the many micro-operations of the instruction cycle.
The hardwired implementations were faster, but too costly for most machines. It has the
advantage that it can be optimized to produce a fast mode of operation. The situation
that arises when the control unit is require to check the status of the condition or status
flags in order to choose between alternative courses of action; the hardwired control will
handle this situation by including an appropriate logic function like; End=T7.ADD +
T6.BR+(T6.N+T4.N). BRN +… in the encoder circuitry. For a given level of technology,
hardwired control will be faster, since there is no delay for microinstruction fetch from
ROM before the control unit can produce a control word.

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4. MICROPROGRAMMED CONTROL

In microprogrammed control, a program generates the control signals. A control word

(CW) is a word whose individual bits represent the various control signals. A sequence of
CWs corresponding to the control sequence of a machine instruction constitutes the micro
routine for that instruction, and the individual control words in this micro routine are
referred to as microinstructions. The micro routines for all instructions in the instruction
set of a computer are stored in a special memory called the control store. The control unit
can generate the control signals for any instruction by sequentially reading the CWs of
the corresponding micro routine from the control store. To read the control, words
sequentially from the control store, a micro programmed counter is used.

Fig: Basic organization of a micro programmed control unit

Every time a new instruction is loaded into the IR, the output of the block labeled
“starting address generator” is loaded into the PC. The PC is then automatically
incremented by the clock, causing successive microinstructions to be read from the
control store. Hence, the control signals are delivered to various parts of the processor in
the correct sequence.

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Fig: Organization of the control unit to allow conditional branching in the microprogram.
To support micro program branching, the organization of the control unit should be
modified. The starting and branch address generator loads a new address into the PC.
To allow implementation of a conditional branch, input to this block consists of the
external inputs and condition codes as well as the contents of the instruction register. In
this control unit, the PC is incremented every time a new microinstruction is fetched
from the micro program memory, except in the following situations:
 When a new instruction is loaded into the IR, the PC is loaded with the starting
address of the micro routine for that instruction.
 When a branch microinstruction is encountered and the branch condition is
satisfied, the PC is loaded with the branch address.
 When an End microinstruction is encountered, the PC is loaded with the address
of the first CW in the micro routine for the instruction fetch cycle.
ADD (Rs) +, Rd
1. PCout, MARin, Read, Select 4, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Rsout, MARin, Read, Select 4, Add, Zin
5. Zout, Rsin
6. Rdout, Yin, WMFC
7. MDRout, Select Y, Add, Zin
8. Zout, Rdin, End

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4.1 Horizontal and Vertical Microinstructions

The easiest way of structuring a microinstruction is to assign one bit for each control
signal. But this results in very long microinstructions and also only a very few of these
will be set to one in a particular clock cycle. So it is better to encode the
microinstructions such that a group of bits represent many control sequence, a particular
pattern of these bits represents a particular microinstruction. A horizontal
microinstruction is a minimally encoded scheme and a vertical microinstruction is a
tightly encoded scheme. In general, a horizontal approach involves a wider control store,
but is capable of greater speed. The vertical approach requires a narrow control store, but
must be decoded in order to drive the actual control lines, thus introducing a delay in
driving the control lines.

4.2 Micro program Sequencing

If all microprograms require only straightforward sequential execution of

microinstructions except for branches, letting a μPC governs the sequencing would be
efficient. However, there are two disadvantages:
 Having a separate microroutine for each machine instruction results in a large
total number of microinstructions and a large control store.
 Longer execution time because it takes more time to carry out the required
branches.
Example: Add src, Rdst

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It has four addressing modes: register, autoincrement, autodecrement, and indexed (with
indirect forms).

Pg No.436 – Computer Organisation by Carl V Hamacher

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Contents of IR OP code 0 1 0 Rsrc Rdst

1110 87 43 0

Address Microinstruction Textbook page 439

(octal)

000 PCout, MARin, Read, Select

4, Add, Zin
001 Zout, PCin, Yin, WMFC
002 MDRout, IRin
003 Branch { PC 101 (from Instruction decoder);
PC5,4  [IR10,9]; PC3  [IR10]  [IR9]  [IR8]}
121 Rsrcout, MARin , Read, Select4, Add,in Z
122 Zout, Rsrcin
123 Branch  { PC 170;PC0  [IR8]}, WMFC
170 MDRout, MARin, Read, WMFC
171 MDRout, Yin
172 Rdstout, SelectY, Add, Zin
173 Zout, Rdstin, End

Note:Microinstruction at location 170 is not executed for this addressing mode.

4.3 Microinstructions with next address field

The microprogram we discussed requires several branch microinstructions, which

perform no useful operation in the data path. A powerful alternative approach is to
include an address field as a part of every microinstruction to indicate the location of
the next microinstruction to be fetched.
 Pros: separate branch microinstructions are virtually eliminated; few limitations in
assigning addresses to microinstructions.
 Cons: additional bits for the address field (around 1/6)

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 External Condition
Inputs codes

Decoding circuits

A R

Control store

Next address I R

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization. R402-CO-Module III

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