Partitioning

ECE6133
Physical Design Automation of VLSI Systems

Prof. Sung Kyu Lim

School of Electrical and Computer Engineering
Georgia Institute of Technology
 Partitioning
Partitioning
System design

Decomposition of a complex system into smaller subsystems.

Each subsystem can be designed independently speeding up

the design process.

Decomposition scheme has to minimize the interconnections

between the subsystems.

Decomposition is carried out hierarchically until each

subsystem is of managable size.

Module 1 Module 2 Module 3 Module n Interface

Information

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 Partitioning

Partitioning of A Circuit
Input size = 48

(a)
~

(b)

Cut 1 = 4 Cut 2 = 4
Size 1 = 15 Size 2 = 16 Size 3 = 17

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 Partitioning

Partitioning at di
erent levels

Partitioning

System Board Chip

Level Level Level

System

Board
System
Level

Chip Board Board Board

Level Level Level

Chip Chip Chip

Level Level Level

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 Partitioning

Problem Formulation
1. Interconnections between partitions:
k X
X k
Obj1 :
i=1 j =1
cij
(i 6= j ) is minimized
2. Delay due to partitioning:
Obj2 : max
p 2P
i
(H (pi)) is minimized
~ 3. Number of terminals:
Cons1 : Count(Vi)  Ti
1  i  k
where,
cij is the cutsize between partitions Vi and Vj .
H (pi) is the number of times a hyperpath pi is cut.
Count(Vi) is the terminal count for partition Vi.

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 Partitioning

Problem Formulation

1. Area of each partition:

i  Area(Vi )  Ai
i = 1
2
: : :
k
Cons2 : Amin
max

~
2. Number of partitions:
Cons3 : Kmin  k  Kmax

The partitioning problem at any level or design style deals with

one or more of the above parameters.

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 Partitioning Methods
• Top-down Partitioning (cutsize only)
– Iterative improvement [KL70, FM82, Kr84, San89]
– Spectral based [HK92, AZ95]
– Clustering method [SU72, NOP87, WC92, SS93, CS93, HK95]
– Network flow based [YW94, YW97]
– Analytical based [RDJ94, LLC95]
– Multi-level [CS93, HB95, AHK97, KA+97, KK99]
• Bottom-up Clustering (delay only)
– Unit delay model [LLT69, CD93]
– General delay model [MBV91, RW93, YW95]
– Sequential circuits with retiming [PKL98, CLW99, CL00]
 Partitioning

Kernighan-Lin Algorithm

 It is a bisectioning algorithm
 The input graph is partitioned into two subsets of equal sizes.
 Till the cutsize keeps improving,
{ Vertex pairs which give the largest decrease in cutsize
~
are exchanged
{ These vertices are then locked
{ If no improvement is possible and some vertices are still
unlocked, the vertices which give the smallest
increase are exchanged
~ W. Kernighan and S. Lin, Bell System Technical Journal, 1970.

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 Partitioning

Kernighan-Lin Algorithm
Algorithm KL
begin
INITIALIZE()
while( IMPROVE(table) = TRUE ) do
(* if an improvement has been made during last iteration,
the process is carried out again. *)
while ( UNLOCK(A) = TRUE ) do
(* if there exists any unlocked vertex in A,
more tentative exchanges are carried out. *)
for ( each a 2 A ) do
if (a = unlocked) then
~
for( each b 2 B ) do
if (b = unlocked) then
if (Dmax < D(a) + D(b)) then
Dmax = D(a) + D(b)
amax = a
bmax = b
TENT-EXCHGE(amax bmax)
LOCK(amax bmax)
LOG(table)
Dmax = ;1
ACTUAL-EXCHGE(table)
end.

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Kernighan-Lin Algorithm
„ Perform single KL pass on the following circuit:
ƒ KL needs undirected graph (clique-based weighting)

Practical Problems in VLSI Physical Design KL Partitioning (1/6)

First Swap

Practical Problems in VLSI Physical Design KL Partitioning (2/6)

Second Swap

Practical Problems in VLSI Physical Design KL Partitioning (3/6)

Third Swap

Practical Problems in VLSI Physical Design KL Partitioning (4/6)

Fourth Swap
„ Last swap does not require gain computation

Practical Problems in VLSI Physical Design KL Partitioning (5/6)

Summary
„ Cutsize reduced from 5 to 3
ƒ Two best solutions found (solutions are always area-balanced)

Practical Problems in VLSI Physical Design KL Partitioning (6/6)

 Partitioning

Drawbacks of K-L Algorithm

 K-L algorithm considers balanced partitions only.

 As vertices have unit weights, it is not possible to
~ allocate a vertex to a partition.
 The K-L algorithm considers edges instead of hyperedges.
 High, O(n3) complexity.

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 Partitioning

Fiduccia-Mattheyses Algorithm

This algorithm is a modied version of Kernighan-Lin Algorithm.

 A single vertex is moved across the cut in a single move which
permits handling of unbalanced partitions.
 The concept of cutsize is extended to hypergraphs.
~  Vertices to be moved are selected in a way to improve
time complexity.
 A special data structure is used to do this.
 Overall time complexity of the algorithm is O(n2).
C. M. Fiduccia and R. M. Mattheyses, 19th DAC, 1982.

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 Partitioning

Data Structure Used in Fiduccia-Mattheyses Algorithm

+pmax Ist Partition

Vertex # Vertex #

-pmax
Vertex
1 2 ......... n List of free
vertices
+pmax IInd Partition

Vertex # Vertex #

-pmax
Vertex
1 2 ......... n

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Fiduccia-Mattheyses Algorithm
„ Perform FM algorithm on the following circuit:
ƒ Area constraint = [3,5]
ƒ Break ties in alphabetical order.

Practical Problems in VLSI Physical Design FM Partitioning (1/12)

Initial Partitioning
„ Random initial partitioning is given.

Practical Problems in VLSI Physical Design FM Partitioning (2/12)

Gain Computation and Bucket Set Up

Practical Problems in VLSI Physical Design FM Partitioning (3/12)

First Move

Practical Problems in VLSI Physical Design FM Partitioning (4/12)

Second Move

Practical Problems in VLSI Physical Design FM Partitioning (5/12)

Third Move

Practical Problems in VLSI Physical Design FM Partitioning (6/12)

Forth Move

Practical Problems in VLSI Physical Design FM Partitioning (7/12)

Fifth Move

Practical Problems in VLSI Physical Design FM Partitioning (8/12)

Sixth Move

Practical Problems in VLSI Physical Design FM Partitioning (9/12)

Seventh Move

Practical Problems in VLSI Physical Design FM Partitioning (10/12)

Last Move

Practical Problems in VLSI Physical Design FM Partitioning (11/12)

Summary
„ Found three best solutions.
ƒ Cutsize reduced from 6 to 3.
ƒ Solutions after move 2 and 4 are better balanced.

Practical Problems in VLSI Physical Design FM Partitioning (12/12)

Probing Further
„ FM Algorithm
ƒ [Krishnamurthy, 1984]: developed “look-ahead” gain concept,
where gain is now a vector.
ƒ [Sanchis, 1989]: perform “flat” multi-way partitioning, where
gain considers all possible destinations
ƒ [Cong and Lim, 1998]: showed that recursive is way better than
flat multi-way partitioning, improved flat method
ƒ [Dutt and Deng, 1996]: encourages neighboring cell move,
effective in avoiding cutting clusters
ƒ [Hagen et al, 1997]: showed that LIFO bucket works better than
FIFO
ƒ [Hauck and Borriello, 1997]: evaluated all existing FM
extensions and proposed the “best” combination

Practical Problems in VLSI Physical Design

Spectral Based Partitioning Algorithms

a c a b c d a b c d
a 0 1 0 3 a 4 0 0 0
3 3
b 0 5 0 0
1
A=
b 1 0 0 4 D=
c 0 0 0 3 c 0 0 3 0
b 4 d d 0 0 0 10
d 3 4 3 0

D: degree matrix; A: adjacency matrix; D-A: Laplacian matrix

Eigenvectors of D-A form the Laplacian spectrum of G
Some Applications of Laplacian Spectrum
H Placement and floorplan
[Hall 1970]
[Otten 1982]
[Frankle-Karp 1986]
[Tsay-Kuh 1986]

H Bisection lower bound and computation

[Donath-Hoffman 1973]
[Barnes 1982]
[Boppana 1987]

H Ratio-cut lower bound and computation

[Hagen-Kahng 1991]
[Cong-Hagen-Kahng 1992]
Eigenvalues and Eigenvectors
A x Ax
⎛ x1 ⎞ ⎛ a11 x1 + a12 x2 + L + a1n xn ⎞
⎛ a11 a12 L a1n ⎞⎜ ⎟ ⎜ ⎟
⎜⎜ ⎟⎟⎜ M ⎟=⎜ M ⎟
...
⎝ an1 an 2 L ann ⎠⎜⎝ xn ⎟ ⎜a x + a x + + a x
⎠ ⎝ n1 1 n2 2 L nn n
⎟
⎠

If Ax=λx
then λ is an eigenvalue of A
x is an eignevector of A w.r.t. λ
(note that Kx is also a eigenvector, for any constant K).
 Spectral Partitioning
• Hall’s Results [1970]
– Given an undirected edge weighted graph G
– Important property about the Laplacian Matrix Q of G
– Eigenvector of the 2nd smallest eigenvalue of Q gives 1-dimensional
placement of nodes in V
– Sum of the squared length of the edges are minimized
– Under Σ x2==1
• Hagen and Kahng’s Results [1992]
– 2nd smallest eigenvalue of Q is a tight lower bound of ratio-cut
– Derive partitioning from 1-dimensional placement for ratio-cut
minimization
Hagen-Kahng EIG Partitioning
„ Perform EIG partitioning and minimize ratio cut cost.
ƒ Clique-based graph model: dotted edge has weight of 0.5, and
solid edge with no label has weight of 0.25.

Practical Problems in VLSI Physical Design EIG Algorithm (1/11)

Adjacency Matrix

Practical Problems in VLSI Physical Design EIG Algorithm (2/11)

Degree Matrix

Practical Problems in VLSI Physical Design EIG Algorithm (3/11)

Laplacian Matrix
„ We obtain Q = D − A

Practical Problems in VLSI Physical Design EIG Algorithm (4/11)

Eigenvalue/vector Computation

Practical Problems in VLSI Physical Design EIG Algorithm (5/11)

EIG Partitioning

Practical Problems in VLSI Physical Design EIG Algorithm (6/11)

EIG Partitioning (cont)

Practical Problems in VLSI Physical Design EIG Algorithm (7/11)

EIG Partitioning (cont)

Practical Problems in VLSI Physical Design EIG Algorithm (8/11)

EIG Partitioning (cont)

Practical Problems in VLSI Physical Design EIG Algorithm (9/11)

Summary
„ Good solution found:
ƒ {(a,f,d,g,i), (j,b,h,e,c)} is well-balanced and has low RC cost.

Practical Problems in VLSI Physical Design EIG Algorithm (10/11)

Theorem

Practical Problems in VLSI Physical Design EIG Algorithm (11/11)

Probing Further
„ EIG Algorithm
ƒ [Chan et al, 1994]: extended EIG to multi-way partitioning, uses
k-smallest eigenvalues/eigenvectors
ƒ [Riess et al, 1994]: use GORDIAN-L placement to derive
partitioning solution that minimizes ratio-cut
ƒ [Alpert and Yao, 1995]: presented a new vertex ordering scheme
based on eigenvectors
ƒ [Alpert and Khang, 1995]: used dynamic programming to split
vertex ordering and obtain multi-way partitioning
ƒ [Li at al, 1996]: studied linear vs quadratic objectives, and
proposed α-order objective Fα, (1 ≤ α ≤ 2)

Practical Problems in VLSI Physical Design