STM32F101x4

STM32F101x6
Low-density access line, ARM®-based 32 bit MCU with
16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces
Datasheet - production data

Features
• Core: ARM® 32-bit Cortex®-M3 CPU
– 36 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1) LQFP64 LQFP48 VFQFPN36
10 x 10 mm 7 x 7 mm
performance at 0 wait state memory 6 × 6 mm

access
– Single-cycle multiplication and hardware • Up to 5 timers
division – Up to two16-bit timers, each with up to 4
• Memories IC/OC/PWM or pulse counter
– 16 to 32 Kbytes of Flash memory – 2 watchdog timers (Independent and
– 4 to 6 Kbytes of SRAM Window)
• Clock, reset and supply management – SysTick timer: 24-bit downcounter
– 2.0 to 3.6 V application supply and I/Os • Up to 4 communication interfaces
– POR, PDR and programmable voltage – 1 x I2C interface (SMBus/PMBus)
detector (PVD) – Up to 2 USARTs (ISO 7816 interface, LIN,
– 4-to-16 MHz crystal oscillator IrDA capability, modem control)
– Internal 8 MHz factory-trimmed RC – 1 × SPI (18 Mbit/s)
– Internal 40 kHz RC • CRC calculation unit, 96-bit unique ID
– PLL for CPU clock • ECOPACK® packages
– 32 kHz oscillator for RTC with calibration
• Low power Table 1. Device summary
– Sleep, Stop and Standby modes Reference Part number
– VBAT supply for RTC and backup registers STM32F101C4,
• Debug mode STM32F101x4 STM32F101R4,
– Serial wire debug (SWD) and JTAG STM32F101T4
interfaces STM32F101C6,
• DMA STM32F101x6 STM32F101R6,
STM32F101T6
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
• 1 × 12-bit, 1 µs A/D converter (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
• Up to 51 fast I/O ports
– 26/37/51 I/Os, all mappable on 16 external
interrupt vectors and almost all 5 V-tolerant

September 2015 DocID15058 Rev 6 1/87

This is information on a product in full production. www.st.com
Contents STM32F101x4, STM32F101x6

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 ARM® Cortex® -M3 core with embedded Flash and SRAM . . . . . . . . . 15
2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15
2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.18 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.19 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.23 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 32
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 32
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 51
5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.2 VFQFPN36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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Contents STM32F101x4, STM32F101x6

6.4 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.5.2 Evaluating the maximum junction temperature for an application . . . . . 83

7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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STM32F101x4, STM32F101x6 List of Tables

List of Tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Low-density STM32F101xx device features and peripheral counts . . . . . . . . . . . . . . . . . . 11
Table 3. STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Low-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. Maximum current consumption in Sleep mode, code running from Flash
or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 15. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 37
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 41
Table 18. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 21. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 26. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 27. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 28. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 29. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 30. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 31. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 32. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 33. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 34. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 35. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 36. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 37. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. SCL frequency (fPCLK1= MHz, VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 40. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 41. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 42. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 43. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 44. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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List of Tables STM32F101x4, STM32F101x6

Table 45. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 46. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 49. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 50. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 51. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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STM32F101x4, STM32F101x6 List of Figures

List of Figures

Figure 1. STM32F101xx Low-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32F101xx Low-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. STM32F101xx Low-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. STM32F101xx Low-density access line UFQPFN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. STM32F101xx Low-density access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 36
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 36
Figure 14. Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 15. Typical current consumption in Stop mode with regulator in Run mode
versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 22. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 23. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 24. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 28. I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 31. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 32. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 33. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 34. Power supply and reference decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 35. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 36. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 37. VFQFPN36 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 75
Figure 39. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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8
List of Figures STM32F101x4, STM32F101x6

Figure 40. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 41. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 78
Figure 42. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 43. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 44. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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STM32F101x4, STM32F101x6 Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of
the STM32F101x4 and STM32F101x6 low-density access line microcontrollers. For more
details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2:
Full compatibility throughout the family.
The Low-density STM32F101xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex®-M3 core please refer to the Cortex®-M3 Technical Reference
Manual, available from the www.arm.com website.

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2 Description

The STM32F101x4 and STM32F101x6 Low-density access line family incorporates the
high-performance ARM Cortex®-M3 32-bit RISC core operating at a 36 MHz frequency,
high-speed embedded memories (Flash memory of 16 to 32 Kbytes and SRAM of 4 to 6
Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB
buses. All devices offer standard communication interfaces (one I2C, one SPI, and two
USARTs), one 12-bit ADC and up to two general-purpose 16-bit timers.
The STM32F101xx Low-density access line family operates in the –40 to +85 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F101xx Low-density access line family includes devices in three different
packages ranging from 36 pins to 64 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F101xx Low-density access line microcontroller family
suitable for a wide range of applications such as application control and user interface,
medical and handheld equipment, PC peripherals, gaming and GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, Video intercoms, and
HVACs.

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STM32F101x4, STM32F101x6 Description

2.1 Device overview

Figure 1 shows the general block diagram of the device family.

Table 2. Low-density STM32F101xx device features and peripheral counts

Peripheral STM32F101Tx STM32F101Cx STM32F101Rx

Flash - Kbytes 16 32 16 32 16 32

SRAM - Kbytes 4 6 4 6 4 6
Timers

General-purpose 2 2 2 2 2 2

SPI 1 1 1 1 1 1

I2C 1 1 1 1 1 1
Communication

USART 2 2 2 2 2 2

12-bit synchronized ADC 1 1 1

number of channels 10 channels 10 channels 16 channels

GPIOs 26 37 51

CPU frequency 36 MHz

Operating voltage 2.0 to 3.6 V

Ambient temperature: –40 to +85 °C (see Table 8)

Operating temperatures
Junction temperature: –40 to +105 °C (see Table 8)

Packages VFQFPN36 LQFP48 LQFP64

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Description STM32F101x4, STM32F101x6

Figure 1. STM32F101xx Low-density access line block diagram

TRACECLK
TRACED[0:3] TPIU
as AS Trace/trig Trace
SWD pbus POWER
NJTRST SW/JTAG controller
JTDI
VDD = 2 to 3.6 V
VOLT. REG.
JTCK/SWCLK VSS

Flash obl
Cortex M3 CPU Ibus 3.3V TO 1.8V

Inte rfac e
JTMS/SWDIO Flash 32 KB
JTDO 64 bit @VDD
as AF Fmax : 3 6M Hz Dbus
NVIC

BusM atrix
SRAM
NVIC Syst em
6 KB @VDD

PCLK1 OSC_IN
GP DMA PCLK 2 PLL & XTAL OSC OSC_OUT
CLOCK 4-16 MHz
7 channels HCLK MANAGT
FCLK

AHB: Fmax =36 MHz

RC 8 MHz
IWDG
RC 42 kHz
@VDDA
Stand by
@VDDA in terface
SUPPLY VBAT
NRST SUPERVISION
@VBAT
VDDA POR / PDR Rst OSC32_IN
VSSA XTAL 32 kHz
OSC32_OUT
PVD Int
RTC Back up
AHB2 AHB2 reg TAMPER-RTC
APB2 APB 1 AWU
Backu p i nterf ace
EXTI
80AF
WAKEUP
4 Chann els

APB 1 : Fmax =24 / 36 MHz

TIM2
PA[ 15:0] GPIOA
TIM3 4 Chann els
PB[ 15:0] GPIOB
APB2 : Fmax = 36 MHz

RX,TX, CTS, RTS,

USART2 CK, SmartCard as AF
PC[15:0] GPIOC
I2C SCL,SDA,SMBA
PD[3:0] GPIOD as AF

MOSI,MISO, WWDG
SCK,NSS as AF SPI

RX,TX, CTS, RTS,

Smartcard as AF USART1
@VDDA

16AF 12bit ADC IF

Temp sen so r

ai15173c

1. AF = alternate function on I/O port pin.

2. TA = –40 °C to +85 °C (junction temperature up to 105 °C).

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STM32F101x4, STM32F101x6 Description

Figure 2. Clock tree

8 MHz
HSI RC HSI

/2
HCLK
36 MHz max to AHB bus, core,
Clock memory and DMA
Enable (3 bits)
/8 to Cortex System timer
PLLSRC SW
PLLMUL FCLK Cortex
HSI free running clock
..., x16 SYSCLK AHB APB1
36 MHz max PCLK1
x2, x3, x4 PLLCLK
Prescaler Prescaler
36 MHz to APB1
PLL max
/1, 2..512 /1, 2, 4, 8, 16 peripherals
Peripheral Clock
HSE
Enable (13 bits)

TIM2, TIM3 to TIM2, TIM3

If (APB1 prescaler =1) x1 TIMXCLK
CSS
else x2 Peripheral Clock
Enable (3 bits)
PLLXTPRE APB2
36 MHz max PCLK2
Prescaler
OSC_OUT to APB2
4-16 MHz /1, 2, 4, 8, 16 peripherals
Peripheral Clock
HSE OSC Enable (11 bits)
OSC_IN /2

ADC to ADC
Prescaler
/128 ADCCLK
/2, 4, 6, 8
OSC32_IN to RTC
LSE OSC LSE
32.768 kHz RTCCLK
OSC32_OUT
RTCSEL[1:0]

to Independent Watchdog (IWDG)

LSI RC LSI
40 kHz IWDGCLK Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
Main /2 PLLCLK LSI = low-speed internal clock signal
Clock Output LSE = low-speed external clock signal
MCO HSI
HSE
SYSCLK
MCO ai15174

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

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2.2 Full compatibility throughout the family

The STM32F101xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are
referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as
medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are
referred to as high-density devices.
Low- and high-density devices are an extension of the STM32F101x8/B devices, they are
specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Low-
density devices feature lower Flash memory and RAM capacities and a timer less. High-
density devices have higher Flash memory and RAM capacities, and additional peripherals
like FSMC and DAC, while remaining fully compatible with the other members of the
STM32F101xx family.
The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE
are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the
user to try different memory densities and providing a greater degree of freedom during the
development cycle.
Moreover, the STM32F101xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.

Table 3. STM32F101xx family

Memory size

Low-density devices Medium-density devices High-density devices

Pinout 16 KB 32 KB 64 KB 128 KB 256 KB 384 KB 512 KB

Flash Flash(1) Flash Flash Flash Flash Flash

32 KB 48 KB 48 KB
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM
RAM RAM RAM

144 - - - - 5 × USARTs
4 × 16-bit timers, 2 × basic timers
100 - -
3 × USARTs 3 × SPIs, 2 × I2Cs, 1 × ADC,
64 2 × USARTs 3 × 16-bit timers 2 × DACs, FSMC (100 and 144 pins)
2 × 16-bit timers 2 × SPIs, 2 × I2Cs,
48 - - -
1 × SPI, 1 × I2C 1 × ADC
36 1 × ADC - - -
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.

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STM32F101x4, STM32F101x6 Description

2.3 Overview

2.3.1 ARM® Cortex® -M3 core with embedded Flash and SRAM
The ARM® Cortex®-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xx Low-density access line family having an embedded ARM core, is
therefore compatible with all ARM tools and software.

2.3.2 Embedded Flash memory

16 or 32 Kbytes of embedded Flash is available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

2.3.4 Embedded SRAM

Up to 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.

2.3.5 Nested vectored interrupt controller (NVIC)

The STM32F101xx Low-density access line embeds a nested vectored interrupt controller
able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of
Cortex®-M3) and 16 priority levels.
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail-chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.

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2.3.6 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See Figure 2 for details on the clock tree.

2.3.8 Boot modes

At startup, boot pins are used to select one of three boot options:
• Boot from User Flash
• Boot from System Memory
• Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.

2.3.9 Power supply schemes

• VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
• VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
• VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.

2.3.10 Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is

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STM32F101x4, STM32F101x6 Description

higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 10: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.
• MR is used in the nominal regulation mode (Run)
• LPR is used in the Stop mode
• Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.

2.3.12 Low-power modes

The STM32F101xx Low-density access line supports three low-power modes to achieve the
best compromise between low power consumption, short startup time and available wakeup
sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.

2.3.13 DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.

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Description STM32F101x4, STM32F101x6

Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers
TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.15 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.

2.3.16 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

2.3.17 SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source

2.3.18 General-purpose timers (TIMx)

There areup to two synchronizable general-purpose timers embedded in the STM32F101xx
Low-density access line devices. These timers are based on a 16-bit auto-reload up/down
counter, a 16-bit prescaler and feature 4 independent channels each for input capture,

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STM32F101x4, STM32F101x6 Description

output compare, PWM or one pulse mode output. This gives up to 12 input captures / output
compares / PWMs on the largest packages.
The general-purpose timers can work together via the Timer Link feature for synchronization
or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs. They all have independent DMA request
generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.

2.3.19 I²C bus

The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.

2.3.20 Universal synchronous/asynchronous receiver transmitter (USART)

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.

2.3.21 Serial peripheral interface (SPI)

The SPI interface is able to communicate up to 18 Mbit/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPI interface can be served by the DMA controller.

2.3.22 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

2.3.23 ADC (analog to digital converter)

The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.

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Description STM32F101x4, STM32F101x6

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

2.3.24 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.

2.3.25 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

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STM32F101x4, STM32F101x6 Pinouts and pin description

3 Pinouts and pin description

Figure 3. STM32F101xx Low-density access line LQFP64 pinout

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3%
3%
3%
               
9%$7   9''B
3&$17,B7$03   966B
3&26&B,1   3$
3&26&B287   3$
3'26&B,1   3$
3'26&B287   3$
1567   3$
3&   3$
3& 
/4)3  3&
3&   3&
3&   3&
966$   3&
9''$   3%
3$:.83   3%
3$   3%
3$   3%
               
9''B

9''B
3$
966B

3$
3$
3$
3$
3&
3&
3%
3%
3%
3%
3%
966B
DLE

Figure 4. STM32F101xx Low-density access line LQFP48 pinout

BOOT0
VDD_3
VSS_3

PA15
PA14
PB9
PB8

PB7
PB6
PB5
PB4
PB3

48 47 46 45 44 43 42 41 40 39 38 37
VBAT 1 36 VDD_2
PC13-TAMPER-RTC 2 35 VSS_2
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PD0-OSC_IN 5 32 PA11
PD1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0-WKUP 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1

ai14378d

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Pinouts and pin description STM32F101x4, STM32F101x6

Figure 5. STM32F101xx Low-density access line UFQPFN48 pinout

"//4
6$$?
633?

0!
0!
0"
0"

0"
0"
0"
0"
0"
           
6"!4   6$$?
0# 4!-0%2 24#   633?
0# /3#?).   0!
0# /3#?/54   0!
0$ /3#?).   0!
0$ /3#?/54   0!
1&0.
.234   0!
  0!
633!
  0"
6$$!
  0"
0! 7+50
  0"
0!
 
0!            
0"

0"
0"
0"
0"
0"
633?
6$$?
0!
0!
0!
0!
0!
-36

Figure 6. STM32F101xx Low-density access line VFQPFN36 pinout

BOOT0
VSS_3

PA15

PA14
PB7

PB6

PB5

PB4

PB3

36 35 34 33 32 31 30 29 28
VDD_3 1 27 VDD_2

OSC_IN/PD0 2 26 VSS_2

OSC_OUT/PD1 3 25 PA13

NRST 4 24 PA12
QFN36
VSSA 5 23 PA11

VDDA 6 22 PA10

PA0-WKUP 7 21 PA9

PA1 8 20 PA8

PA2 9 19 VDD_1
10 11 12 13 14 15 16 17 18
PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

VSS_1

ai14654

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STM32F101x4, STM32F101x6 Pinouts and pin description

Table 4. Low-density STM32F101xx pin definitions

Pins Alternate functions(3)(4)

I / O level(2)
Main

Type(1)
VFQFPN36

function(3)
LQFP48

LQFP64

Pin name
(after reset) Default Remap

1 1 - VBAT S - VBAT - -
PC13-TAMPER-
2 2 - I/O - PC13(6) TAMPER-RTC -
RTC(5)
3 3 - PC14-OSC32_IN(5) I/O - PC14(6) OSC32_IN -
(5) (6)
4 4 - PC15-OSC32_OUT I/O - PC15 OSC32_OUT -
5 5 2 OSC_IN I - OSC_IN - -
6 6 3 OSC_OUT O - OSC_OUT - -
7 7 4 NRST I/O - NRST - -
- 8 - PC0 I/O - PC0 ADC_IN10 -
- 9 - PC1 I/O - PC1 ADC_IN11 -
- 10 - PC2 I/O - PC2 ADC_IN12 -
- 11 - PC3 I/O - PC3 ADC_IN13 -
8 12 5 VSSA S - VSSA - -
9 13 6 VDDA S - VDDA - -
WKUP/USART2_CTS/
10 14 7 PA0-WKUP I/O - PA0 ADC_IN0/ -
TIM2_CH1_ETR(7)
USART2_RTS/
11 15 8 PA1 I/O - PA1 -
ADC_IN1/TIM2_CH2(7)
USART2_TX/
12 16 9 PA2 I/O - PA2 -
ADC_IN2/TIM2_CH3(7)
USART2_RX/
13 17 10 PA3 I/O - PA3 -
ADC_IN3/TIM2_CH4(7)
- 18 - VSS_4 S - VSS_4 - -
- 19 - VDD_4 S - VDD_4 - -
SPI_NSS(7)/ADC_IN4
14 20 11 PA4 I/O - PA4 -
USART2_CK
15 21 12 PA5 I/O - PA5 SPI_SCK(7)/ADC_IN5 -
SPI_MISO(7)/ADC_IN6/
16 22 13 PA6 I/O - PA6 -
TIM3_CH1(7)

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Table 4. Low-density STM32F101xx pin definitions (continued)

Pins Alternate functions(3)(4)

I / O level(2)
Main

Type(1)
VFQFPN36

function(3)
LQFP48

LQFP64

Pin name
(after reset) Default Remap

SPI_MOSI(7)/ADC_IN7/
17 23 14 PA7 I/O - PA7 -
TIM3_CH2(7)
- 24 - PC4 I/O - PC4 ADC_IN14 -
- 25 - PC5 I/O - PC5 ADC_IN15 -
(7)
18 26 15 PB0 I/O - PB0 ADC_IN8/TIM3_CH3 -
19 27 16 PB1 I/O - PB1 ADC_IN9/TIM3_CH4(7) -
20 28 17 PB2 I/O FT PB2/BOOT1 - -
21 29 - PB10 I/O FT PB10 - TIM2_CH3
22 30 - PB11 I/O FT PB11 - TIM2_CH4
23 31 18 VSS_1 S - VSS_1 - -
24 32 19 VDD_1 S - VDD_1 - -
25 33 - PB12 I/O FT PB12 - -
26 34 - PB13 I/O FT PB13 - -
27 35 - PB14 I/O FT PB14 - -
28 36 - PB15 I/O FT PB15 - -
- 37 - PC6 I/O FT PC6 - TIM3_CH1
- 38 - PC7 I/O FT PC7 - TIM3_CH2
- 39 - PC8 I/O FT PC8 - TIM3_CH3
- 40 - PC9 I/O FT PC9 - TIM3_CH4
29 41 20 PA8 I/O FT PA8 USART1_CK/MCO -
(7)
30 42 21 PA9 I/O FT PA9 USART1_TX -
31 43 22 PA10 I/O FT PA10 USART1_RX(7) -
32 44 23 PA11 I/O FT PA11 USART1_CTS -
33 45 24 PA12 I/O FT PA12 USART1_RTS -
JTMS-
34 46 25 PA13 I/O FT - PA13
SWDIO
35 47 26 VSS_2 S - VSS_2 - -
36 48 27 VDD_2 S - VDD_2 - -

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STM32F101x4, STM32F101x6 Pinouts and pin description

Table 4. Low-density STM32F101xx pin definitions (continued)

Pins Alternate functions(3)(4)

I / O level(2)
Main

Type(1)
VFQFPN36

function(3)
LQFP48

LQFP64

Pin name
(after reset) Default Remap

JTCK/SWCL
37 49 28 PA14 I/O FT - PA14
K
TIM2_CH1_ETR/
38 50 29 PA15 I/O FT JTDI -
PA15 / SPI_NSS
- 51 - PC10 I/O FT PC10 - -
- 52 - PC11 I/O FT PC11 - -
- 53 - PC12 I/O FT PC12 - -
5 5 2 PD0 I/O FT OSC_IN(8) - -
6 6 3 PD1 I/O FT OSC_OUT(8) - -
- 54 - PD2 I/O FT PD2 TIM3_ETR -
TIM2_CH2 / PB3
39 55 30 PB3 I/O FT JTDO - TRACESWO
SPI_SCK
TIM3_CH1 / PB4
40 56 31 PB4 I/O FT NJTRST -
SPI_MISO
TIM3_CH2 /
41 57 32 PB5 I/O - PB5 I2C_SMBA
SPI_MOSI
42 58 33 PB6 I/O FT PB6 I2C_SCL(7) USART1_TX
(7)
43 59 34 PB7 I/O FT PB7 I2C_SDA USART1_RX
44 60 35 BOOT0 I - BOOT0 - -
45 61 - PB8 I/O FT PB8 - I2C_SCL
46 62 - PB9 I/O FT PB9 - I2C_SDA
47 63 36 VSS_3 S - VSS_3 - -
48 64 1 VDD_3 S - VDD_3 - -
1. I = input, O = output, S = supply.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

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6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
8. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

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STM32F101x4, STM32F101x6 Memory mapping

4 Memory mapping

The memory map is shown in Figure 7.

Figure 7. Memory map

APB memory space
0xFFFF FFFF
reserved
0xFFFF FFFF 0xE010 0000
reserved
0x6000 0000
reserved
0x4002 3400
CRC
7 0x4002 3000
reserved
0xE010 0000 0x4002 2400
Cortex-M3 internal
0xE000 0000 peripherals 0x4002 2000 Flash interface

0x4002 1400 reserved

0x4002 1000 RCC

6 0x4002 0400 reserved

0x4002 0000 DMA

0xC000 0000 reserved
0x4001 3C00
USART1
0x4001 3800
reserved
0x4001 3400
5 SPI
0x4001 3000
reserved
0xA000 0000 0x4001 2C00
reserved
0x4001 2800
ADC
0x4001 2400
reserved
4 0x1FFF FFFF 0x4001 1800
reserved Port D
0x1FFF F80F 0x4001 1400
0x4001 1000 Port C
0x8000 0000 Option Bytes
0x1FFF F800 0x4001 0C00 Port B

0x4001 0800 Port A

3 System memory 0x4001 0400 EXTI

0x4001 0000 AFIO

0x1FFF F000 reserved
0x6000 0000 0x4000 7400
PWR
0x4000 7000
BKP
0x4000 6C00
2 reserved
0x4000 6800
reserved
reserved 0x4000 6400
Peripherals reserved
0x4000 0000 0x4000 6000
reserved
0x4000 5800
0x4000 5400 I2C
1 0x4000 4800 reserved

0x4000 4400 USART2

SRAM reserved
0x2000 0000 0x4000 3400
0x0801 FFFF
0x4000 3000 IWDG

0x4000 2C00 WWDG

0 Flash memory
RTC
0x4000 2800
0x4000 0800 reserved
0x0800 0000
0x0000 0000 Aliased to Flash or 0x4000 0400 TIM3
system memory TIM2
0x4000 0000
depending on
0x0000 0000 BOOT pins
Reserved
ai15175b

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Electrical characteristics STM32F101x4, STM32F101x6

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

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STM32F101x4, STM32F101x6 Electrical characteristics

Figure 8. Pin loading conditions Figure 9. Pin input voltage

STM32F10xxx pin STM32F10xxx pin

C = 50 pF VIN

ai14124b
ai14123b

5.1.6 Power supply scheme

Figure 10. Power supply scheme

VBAT

Backup circuitry
Po wer swi tch (OSC32K,RTC,
1.8-3.6V
Wakeup logic
Backup registers)
Level shifter

OUT
IO
GP I/Os Logic
IN Kernel logic
(CPU,
Digital
VDD
VDD & Memories)
1/2/3/4/5 Regulator
5 × 100 nF VSS
+ 1 × 4.7 µF 1/2/3/4/5

VDD
VDDA

VREF VREF+

Analog:
10 nF 10 nF ADC
RCs, PLL,
+ 1 µF + 1 µF VREF- ...
VSSA

ai15496

Caution: In Figure 10, the 4.7 µF capacitor must be connected to VDD3.

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Electrical characteristics STM32F101x4, STM32F101x6

5.1.7 Current consumption measurement

Figure 11. Current consumption measurement scheme

IDD_VBAT
VBAT

IDD
VDD

VDDA

ai14126

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,
Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

Table 5. Voltage characteristics

Symbol Ratings Min Max Unit

External main supply voltage (including

VDD −VSS –0.3 4.0
VDDA and VDD)(1)
V
Input voltage on five volt tolerant pin VSS −0.3 VDD +4.0
VIN (2)
Input voltage on any other pin VSS − 0.3 4.0
|ΔVDDx| Variations between different VDD power pins - 50
Variations between all the different ground mV
|VSSX − VSS| - 50
pins
see Section 5.3.11: Absolute
Electrostatic discharge voltage (human body
VESD(HBM) maximum ratings (electrical -
model)
sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 6: Current characteristics for the maximum
allowed injected current values.

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STM32F101x4, STM32F101x6 Electrical characteristics

Table 6. Current characteristics

Symbol Ratings Max. Unit

IVDD Total current into VDD/VDDA power lines (source)(1) 150

(1)
IVSS Total current out of VSS ground lines (sink) 150
Output current sunk by any I/O and control pin 25
IIO
Output current source by any I/Os and control pin −25 mA
(3)
Injected current on five volt tolerant pins -5/+0
IINJ(PIN)(2)
(4)
Injected current on any other pin ±5
ΣIINJ(PIN) (5)
Total injected current (sum of all I/O and control pins) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
characteristics.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage
values.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

Table 7. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C

5.3 Operating conditions

5.3.1 General operating conditions

Table 8. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 36

fPCLK1 Internal APB1 clock frequency - 0 36 MHz
fPCLK2 Internal APB2 clock frequency - 0 36
VDD Standard operating voltage - 2 3.6
Analog operating voltage
2 3.6
(ADC not used) Must be the same potential
VDDA (1) V
Analog operating voltage as VDD(2)
2.4 3.6
(ADC used)
VBAT Backup operating voltage - 1.8 3.6

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Table 8. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

LQFP64 - 444
Power dissipation at TA =
PD LQFP48 - 363 mW
85 °C(3)
VFQFPN36 - 1000
Maximum power dissipation –40 85
TA Ambient temperature
Low power dissipation(4) –40 105 °C
TJ Junction temperature range - –40 105
1. When the ADC is used, refer to Table 41: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.5: Thermal
characteristics on page 82).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.5: Thermal characteristics on page 82).

5.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.

Table 9. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time

0 ∞
rate
tVDD - µs/V
VDD fall time
20 ∞
rate

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 10 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.

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STM32F101x4, STM32F101x6 Electrical characteristics

Table 10. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge) 2.1 2.18 2.26

PLS[2:0]=000 (falling edge) 2 2.08 2.16
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58

Programmable voltage PLS[2:0]=011 (falling edge) 2.28 2.38 2.48

VPVD V
detector level selection PLS[2:0]=100 (rising edge) 2.47 2.58 2.69
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8
PLS[2:0]=111 (rising edge) 2.76 2.88 3
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9
VPVDhyst(2) PVD hysteresis - - 100 - mV
(1)
Power on/power down Falling edge 1.8 1.88 1.96
VPOR/PDR V
reset threshold Rising edge 1.84 1.92 2.0
VPDRhyst(2) PDR hysteresis - - 40 - mV
tRSTTEMPO(2) Reset temporization - 1.5 2.5 4.5 ms
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.

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5.3.4 Embedded reference voltage

The parameters given in Table 11 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.

Table 11. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –40 °C < TA < +85 °C 1.16 1.20 1.24 V
ADC sampling time when reading
TS_vrefint(1) - - 5.1 17.1(2) µs
the internal reference voltage
Internal reference voltage spread
VRERINT(2) VDD = 3 V ±10 mV - - 10 mV
over the temperature range
ppm/
TCoeff(2) Temperature coefficient - - - 100
°C
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load)
• All peripherals are disabled except if it is explicitly mentioned
• The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 36 MHz)
• Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
• When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 12 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.

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Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol Parameter Conditions fHCLK Unit
TA = 85 °C

36 MHz 26

External clock (2), all 24 MHz 18

peripherals enabled 16 MHz 13

Supply current 8 MHz 7

IDD mA
in Run mode 36 MHz 19

External clock (2), all 24 MHz 13

peripherals Disabled 16 MHz 10
8 MHz 6
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol Parameter Conditions fHCLK Unit
TA = 85 °C

36 MHz 20

External clock (2), all 24 MHz 14

peripherals enabled 16 MHz 10

Supply current in 8 MHz 6

IDD mA
Run mode 36 MHz 15

External clock(2) all 24 MHz 10

peripherals disabled 16 MHz 7
8 MHz 5
1. Based on characterization, tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

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Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled

25

20
Consumption (mA)

15
36 MHz
16 MHz
8 MHz
10

0
– 45°C 25 °C 70 °C 85 °C
Temperature (°C)

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled

16

14

12
Consumption (mA)

10
36 MHz
8 16 MHz
8 MHz
6

0
– 45°C 25 °C 70 °C 85 °C
Temperature (°C)

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STM32F101x4, STM32F101x6 Electrical characteristics

Table 14. Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max(1)
Symbol Parameter Conditions fHCLK Unit
TA = 85 °C

36 MHz 14

External clock(2) all 24 MHz 10

peripherals enabled 16 MHz 7

Supply current in 8 MHz 4

IDD mA
Sleep mode 36 MHz 5

External clock(2), all 24 MHz 4.5

peripherals disabled 16 MHz 4
8 MHz 3
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

Table 15. Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Max
Symbol Parameter Conditions Unit
VDD/VBAT VDD/ VBAT VDD/VBAT TA =
= 2.0 V = 2.4 V = 3.3 V 85 °C(2)

Regulator in Run mode,

Low-speed and high-speed internal
RC oscillators and high-speed - 21.3 21.7 160
oscillator OFF (no independent
Supply watchdog)
current in
Stop mode Regulator in Low Power mode,
Low-speed and high-speed internal
RC oscillators and high-speed - 11.3 11.7 145
oscillator OFF (no independent
IDD
watchdog)
Low-speed internal RC oscillator µA
- 2.6 3.4 -
and independent watchdog ON
Supply
Low-speed internal RC oscillator
current in - 2.4 3.2 -
ON, independent watchdog OFF
Standby
mode Low-speed internal RC oscillator
and independent watchdog OFF, - 1.7 2 3.2
low-speed oscillator and RTC OFF
Backup
IDD_VBAT domain Low-speed oscillator and RTC ON 0.9 1.1 1.4 1.9
supply current
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not rested in production.

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Figure 14. Typical current consumption on VBAT with RTC on versus temperature at
different
VBAT values

2.5

Consumption ( µA )
2

1.5 2V
2.4 V
1
3V
0.5 3.6 V

0
–40 °C 25 °C 70 °C 85 °C 105 °C
Temperature (°C)
ai17351

Figure 15. Typical current consumption in Stop mode with regulator in Run mode
versus temperature at VDD = 3.3 V and 3.6 V

45

40

35

30
Consumption (µA)

25 3.3 V

20 3.6 V

15

10

0
–45 °C 25 °C 85 °C
Temperature (°C)

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Figure 16. Typical current consumption in Stop mode with regulator in Low-power
mode versus
temperature at VDD = 3.3 V and 3.6 V

30

25

20
Consumption (µA)

3.3 V
15
3.6 V

10

0
–45 °C 25 °C 85 °C
Temperature (°C)

Figure 17. Typical current consumption in Standby mode versus temperature at VDD =
3.3 V and
3.6 V

3.5

2.5
Consumption (µA)

2
3.3 V
3.6 V
1.5

0.5

0
–45 °C 25 °C 85 °C
Temperature (°C)

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Typical current consumption

The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load)
• All peripherals are disabled except if it is explicitly mentioned
• The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 36 MHz)
• Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
• When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK =
fPCLK2/4
The parameters given in Table 16 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.

Table 16. Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1) Typ(1)
Symbol Parameter Conditions fHCLK All peripherals All peripherals Unit
enabled(2) disabled
36 MHz 17.2 13.8
24 MHz 11.2 8.9
16 MHz 8.1 6.6
8 MHz 5 4.2
External
4 MHz 3 2.6
clock(3)
2 MHz 2 1.8
1 MHz 1.5 1.4
500 kHz 1.2 1.2
Supply 125 kHz 1.05 1
IDD current in mA
Run mode 36 MHz 16.5 13.1
24 MHz 10.5 8.2
Running on
16 MHz 7.4 5.9
high speed
internal RC 8 MHz 4.3 3.6
(HSI), AHB
4 MHz 2.4 2
prescaler
used to 2 MHz 1.5 1.3
reduce the
frequency 1 MHz 1 0.9
500 kHz 0.7 0.65
125 kHz 0.5 0.45
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

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Table 17. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1) Typ(1)
Symbol Parameter Conditions fHCLK All peripherals All peripherals Unit
enabled(2) disabled
36 MHz 6.7 3.1
24 MHz 4.8 2.3
16 MHz 3.4 1.8
8 MHz 2 1.2
(3)
External clock 4 MHz 1.5 1.1
2 MHz 1.25 1
1 MHz 1.1 0.98
500 kHz 1.05 0.96
Supply 125 kHz 1 0.95
IDD current in mA
Sleep mode 36 MHz 6.1 2.5
24 MHz 4.2 1.7
16 MHz 2.8 1.2
Running on High
Speed Internal RC 8 MHz 1.4 0.55
(HSI), AHB
4 MHz 0.9 0.5
prescaler used to
reduce the 2 MHz 0.7 0.45
frequency
1 MHz 0.55 0.42
500 kHz 0.48 0.4
125 kHz 0.4 0.38
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed
under the following conditions:
• all I/O pins are in input mode with a static value at VDD or VSS (no load)
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
• ambient operating temperature and VDD supply voltage conditions summarized in
Table 5.

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Table 18. Peripheral current consumption

Peripheral Typical consumption at 25 °C Unit

DMA1 15.97
AHB (up to 36 MHz) CRC 1.67
(1)
BusMatrix 8.33
APB1-Bridge 7.22
TIM2 33.33
TIM3 33.61
USART2 12.78
APB1 (up to 18 MHz) I2C1 10.83
WWDG 3.33
PWR 1.94
μA/MHz
BKP 2.78
IWDG 1.39
APB2-Bridge 3.33
GPIO A 7.50
GPIO B 6.81
GPIO C 7.22
APB2 (up to 36 MHz)
GPIO D 6.94
SPI1 4.86
USART1 12.78
ADC1(2) 15.54
1. The BusMatrix is automatically active when at least one master is ON. (CPU, DMA1).
2. Specific conditions for measuring ADC current consumption: fHCLK = 28 MHz, fAPB1 = fHCLK, fAPB2 = fHCLK,
fADCCLK = fAPB2 / 2. When ADON bit in the ADC_CR2 register is set to 1, a current consumption of analog
part equal to 0.7 mA must be added.

5.3.6 External clock source characteristics

High-speed external user clock generated from an external source
The characteristics given in Table 19 result from tests performed using an high-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 8.

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Table 19. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fHSE_ext 1 8 25 MHz
frequency(1)
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
-
tw(HSE)
OSC_IN high or low time(1) 5 - -
tw(HSE)
ns
tr(HSE) (1)
OSC_IN rise or fall time - - 20
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) - - 5 - pF
DuCy(HSE) Duty cycle - 45 - 55 %
IL OSC_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
1. Guaranteed by design, not tested in production.

Low-speed external user clock generated from an external source

The characteristics given in Table 20 result from tests performed using an low-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 8.

Table 20. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext - 32.768 1000 kHz
frequency(1)
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage
V
OSC32_IN input pin low level
VLSEL - VSS - 0.3VDD
voltage
tw(LSE)
OSC32_IN high or low time(1) 450 - -
tw(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) - - 50
tf(LSE)
Cin(LSE) OSC32_IN input capacitance(1) - - 5 - pF
DuCy(LSE) Duty cycle - 30 - 70 %
IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
1. Guaranteed by design, not tested in production.

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Figure 18. High-speed external clock source AC timing diagram

VHSEH
90%
10%
VHSEL

tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
THSE

External fHSE_ext
IL
clock source OSC _IN
STM32F10xxx

ai14127b

Figure 19. Low-speed external clock source AC timing diagram

VLSEH
90%
10%
VLSEL

tr(LSE) tW(LSE) t
tf(LSE) tW(LSE)
TLSE

External fLSE_ext
OSC32_IN IL
clock source
STM32F10xxx

ai14140c

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 21. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

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Table 21. HSE 4-16 MHz oscillator characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 8 16 MHz

RF Feedback resistor - - 200 - kΩ
Recommended load capacitance
C versus equivalent serial RS = 30 Ω - 30 - pF
resistance of the crystal (RS)(3)
VDD = 3.3 V, VIN = VSS
i2 HSE driving current - - 1 mA
with 30 pF load
gm Oscillator transconductance Startup 25 - - mA/V
(4)
tSU(HSE) Startup time VDD is stabilized - 2 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 20). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.

Figure 20. Typical application with an 8 MHz crystal

Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MH z controlled
RF
resonator gain
OSC_OU T STM32F10xxx
CL2 REXT(1)

ai14128b

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 22. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization

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time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2)

Symbol Parameter Conditions - Min Typ Max Unit

RF Feedback resistor - - - 5 - MΩ
Recommended load capacitance
C versus equivalent serial RS = 30 KΩ - - - 15 pF
resistance of the crystal (RS)
VDD = 3.3 V
I2 LSE driving current - - - 1.4 µA
VIN = VSS
gm Oscillator transconductance - - 5 - - µA/V
TA = 50 °C - 1.5 -
TA = 25 °C - 2.5 -
TA = 10 °C - 4 -

VDD is TA = 0 °C - 6 -
tSU(LSE)(3) Startup time s
stabilized TA = -10 °C - 10 -
TA = -20 °C - 17 -
TA = -30 °C - 32 -
TA = -40 °C - 60 -
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2,
are usually the same size. The crystal manufacturer typically specifies a load capacitance
which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray
where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it
is between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF is chosen,
then CL1 = CL2 = 8 pF.

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Figure 21. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Bias
32.768 KH z controlled
RF
resonator gain
OSC32_OU T STM32F10xxx
CL2

ai14129b

5.3.7 Internal clock source characteristics

The parameters given in Table 23 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.

High-speed internal (HSI) RC oscillator

Table 23. HSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency - - 8 - MHz

DuCy(HSI) Duty cycle - 45 - 55 %
User-trimmed with the RCC_CR
- - 1(3) %
register(2)
TA = –40 to 105 °C –2 - 2.5 %
Accuracy of the HSI
ACCHSI Factory-
oscillator TA = –10 to 85 °C –1.5 - 2.2 %
calibrated
(4) (5) TA = 0 to 70 °C –1.3 - 2 %
TA = 25 °C –1.1 - 1.8 %
HSI oscillator
tsu(HSI)(4) - 1 - 2 µs
startup time
HSI oscillator power
IDD(HSI)(4) - - 80 100 µA
consumption
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified
range.

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Low-speed internal (LSI) RC oscillator

Table 24. LSI oscillator characteristics (1)

Symbol Parameter Min Typ Max Unit

fLSI(2) Frequency 30 40 60 kHz

(3)
tsu(LSI) LSI oscillator startup time - - 85 µs
IDD(LSI) (3) LSI oscillator power consumption - 0.65 1.2 µA
1. VDD = 3 V, TA = –40 to 85 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.

Wakeup time from low-power mode

The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
• Stop or Standby mode: the clock source is the RC oscillator
• Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and VDD supply
voltage conditions summarized in Table 8.

Table 25. Low-power mode wakeup timings

Symbol Parameter Typ Unit

tWUSLEEP(1) Wakeup from Sleep mode 1.8 µs

Wakeup from Stop mode (regulator in run mode) 3.6
tWUSTOP(1) µs
Wakeup from Stop mode (regulator in low-power mode) 5.4
tWUSTDBY(1) Wakeup from Standby mode 50 µs
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.

5.3.8 PLL characteristics

The parameters given in Table 26 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.

Table 26. PLL characteristics

Value
Symbol Parameter Unit
Min(1) Typ Max(1)

PLL input clock(2) 1 8.0 25 MHz

fPLL_IN
PLL input clock duty cycle 40 - 60 %
fPLL_OUT PLL multiplier output clock 16 - 36 MHz

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Table 26. PLL characteristics (continued)

Value
Symbol Parameter Unit
Min(1) Typ Max(1)

tLOCK PLL lock time - - 200 µs

Jitter Cycle-to-cycle jitter - - 300 ps
1. Based on device characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.

5.3.9 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 85 °C unless otherwise specified.

Table 27. Flash memory characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

tprog 16-bit programming time TA = –40 to +85 °C 40 52.5 70 µs

tERASE Page (1 KB) erase time TA = –40 to +85 °C 20 - 40 ms
tME Mass erase time TA = –40 to +85 °C 20 - 40 ms
Read mode
fHCLK = 36 MHz with 1 wait - - 20 mA
state, VDD = 3.3 V
IDD Supply current Write / Erase modes
- - 5 mA
fHCLK = 36 MHz, VDD = 3.3 V
Power-down mode / Halt,
- - 50 µA
VDD = 3.0 to 3.6 V
Vprog Programming voltage - 2 - 3.6 V
1. Guaranteed by design, not tested in production.

5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.

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The test results are given in Table 28. They are based on the EMS levels and classes
defined in application note AN1709.

Table 28. EMS characteristics

Symbol Parameter Conditions Level/Class

VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK= 36 MHz 2B
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS pins fHCLK = 36 MHz 4A
to induce a functional disturbance conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC61967-2 standard which specifies the test board and the pin loading.

Table 29. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
Symbol Parameter Conditions Unit
frequency band
8/36 MHz

0.1 MHz to 30 MHz 7

VDD = 3.3 V, TA = 25 °C, 30 MHz to 130 MHz 8 dBµV
SEMI Peak level compliant with
IEC 61967-2 130 MHz to 1GHz 13
EMI Level 3.5 -

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5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Table 30. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge TA = +25 °C

VESD(HBM) 2 2000
voltage (human body model) conforming to JESD22-A114
TA = +25 °C V
Electrostatic discharge
VESD(CDM) conforming to II 500
voltage (charge device model)
ANSI/ESD STM5.3.1
1. Based on characterization results, not tested in production.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.

Table 31. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +85 °C conforming to JESD78A II level A

5.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.

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The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 32

Table 32. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on OSC_IN32,

-0 +0
OSC_OUT32, PA4, PA5, PC13
IINJ mA
Injected current on all FT pins -5 +0
Injected current on any other pin -5 +5

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5.3.13 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.

Table 33. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

Standard IO input low

-0.3 - 0.28*(VDD-2 V)+0.8 V(1)
level voltage
VIL -
IO FT(2) input low
-0.3 - 0.32*(VDD-2 V)+0.75 V(1)
level voltage
V
Standard IO input high
- 0.41*(VDD-2 V)+1.3 V(1) - VDD+0.3
level voltage
VIH
IO FT(2) input high VDD > 2 V 5.5
0.42*(VDD-2 V)+1 V(1) -
level voltage VDD ≤ 2 V 5.2
Standard IO Schmitt
trigger voltage - 200 - -
Vhys hysteresis(3) mV
IO FT Schmitt trigger
- 5% VDD(4) - -
voltage hysteresis(3)
VSS ≤ VIN ≤ VDD
- - ±1
Input leakage current Standard I/Os
Ilkg (5) µA
VIN = 5 V
- - 3
I/O FT
Weak pull-up
RPU VIN = VSS 30 40 50
equivalent resistor(6)
kΩ
Weak pull-down
RPD VIN = VDD 30 40 50
equivalent resistor(6)
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation.
2. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
4. With a minimum of 100 mV.
5. Leakage could be higher than max. if negative current is injected on adjacent pins.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).

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Electrical characteristics STM32F101x4, STM32F101x6

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 and Figure 23 for standard I/Os, and
in Figure 24 and Figure 25 for 5 V tolerant I/Os.

Figure 22. Standard I/O input characteristics - CMOS port

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54/87 DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Figure 24. 5 V tolerant I/O input characteristics - CMOS port

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Electrical characteristics STM32F101x4, STM32F101x6

Output driving current

The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can
sink or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 6).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 6).

Output voltage levels

Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 8. All I/Os are CMOS and TTL compliant.

Table 34. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

Output Low level voltage for an I/O pin

VOL(1) CMOS port(2),, - 0.4
when 8 pins are sunk at the same time
IIO = +8 mA, V
Output High level voltage for an I/O pin 2.7 V < VDD < 3.6 V
VOH(3) VDD–0.4 -
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
VOL(1) TTL port(2) - 0.4
when 8 pins are sunk at the same time
IIO = +8 mA V
Output high level voltage for an I/O pin
VOH(3) 2.7 V < VDD < 3.6 V 2.4 -
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
VOL(1) - 1.3
when 8 pins are sunk at the same time IIO = +20 mA(4)
V
Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V
VOH (3) VDD–1.3 -
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
VOL(1) - 0.4
when 8 pins are sunk at the same time IIO = +6 mA(4)
V
Output high level voltage for an I/O pin 2 V < VDD < 2.7 V
VOH(3) VDD–0.4 -
when 8 pins are sourced at the same time
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data, not tested in production.

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STM32F101x4, STM32F101x6 Electrical characteristics

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and
Table 35, respectively.
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 8.

Table 35. I/O AC characteristics(1)

MODEx
[1:0] bit Symbol Parameter Conditions Max Unit
value(1)

fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 2 MHz

Output high to low level fall
tf(IO)out 125(3)
10 time
CL = 50 pF, VDD = 2 V to 3.6 V ns
Output low to high level rise (3)
tr(IO)out 125
time
fmax(IO)out Maximum frequency(2) CL= 50 pF, VDD = 2 V to 3.6 V 10 MHz
Output high to low level fall
tf(IO)out 25(3)
01 time
CL= 50 pF, VDD = 2 V to 3.6 V ns
Output low to high level rise
tr(IO)out 25(3)
time
CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz
Fmax(IO)out Maximum Frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz
CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
Output high to low level fall
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
11 time
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 ns
5(3)
V
Output low to high level rise
tr(IO)out
time CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
Pulse width of external
- tEXTIpw signals detected by the - 10 ns
EXTI controller
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 26.
3. Guaranteed by design, not tested in production.

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 26. I/O AC characteristics definition

 
 
 

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5.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 33).
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 8.

Table 36. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST)(1) NRST Input low level voltage - –0.5 - 0.8

V
(1)
VIH(NRST) NRST Input high level voltage - 2 - VDD+0.5
NRST Schmitt trigger voltage
Vhys(NRST) - - 200 - mV
hysteresis
RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ
VF(NRST)(1) NRST Input filtered pulse - - - 100 ns
VNF(NRST) (1) NRST Input not filtered pulse - 300 - - ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).

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STM32F101x4, STM32F101x6 Electrical characteristics

Figure 27. Recommended NRST pin protection

VDD
External
reset circuit(1)
RPU Internal Reset
NRST(2)
Filter
0.1 µF

STM32F10xxx

ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 36. Otherwise the reset will not be taken into account by the device.

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5.3.15 TIM timer characteristics

The parameters given in Table 37 are guaranteed by design.
Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).

Table 37. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 36 MHz 27.8 - ns

Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 fTIMxCLK = 36 MHz 0 18 MHz
ResTIM Timer resolution - - 16 bit
16-bit counter clock period - 1 65536 tTIMxCLK
tCOUNTER when internal clock is
selected fTIMxCLK = 36 MHz 0.0278 1820 µs

- - 65536 × 65536 tTIMxCLK

tMAX_COUNT Maximum possible count
fTIMxCLK = 36 MHz - 119.2 s
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

5.3.16 Communications interfaces

I2C interface characteristics
The STM32F101xx Low-density access line I2C interface meets the requirements of the
standard I2C communication protocol with the following restrictions: the I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).

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STM32F101x4, STM32F101x6 Electrical characteristics

Table 38. I2C characteristics

Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol Parameter Unit
Min Max Min Max

tw(SCLL) SCL clock low time 4.7 - 1.3 -

µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
(3)
th(SDA) SDA data hold time 0 - 0 900(4)
tr(SDA) ns
SDA and SCL rise time - 1000 20+0.1Cb 300
tr(SCL)
tf(SDA)
SDA and SCL fall time - 300 - 300
tf(SCL)
th(STA) Start condition hold time 4.0 - 0.6 -
Repeated Start condition setup µs
tsu(STA) 4.7 - 0.6 -
time
tsu(STO) Stop condition setup time 4.0 - 0.6 - µs
Stop to Start condition time (bus
tw(STO:STA) 4.7 - 1.3 - µs
free)
Cb Capacitive load for each bus line - 400 - 400 pF
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C
fast mode clock.
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
4. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 28. I2C bus AC waveforms and measurement circuit(1)

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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

2. Rs = Series protection resistors, Rp = Pull-up resistors, VDD_I2C = I2C bus supply.

Table 39. SCL frequency (fPCLK1= MHz, VDD_I2C = 3.3 V)(1)(2)

I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ

400 0x801E
300 0x8028
200 0x803C
100 0x00B4
50 0x0168
20 0x0384
2
1. RP = External pull-up resistance, fSCL = I C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.

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STM32F101x4, STM32F101x6 Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 8.
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 40. SPI characteristics

Symbol Parameter Conditions Min Max Unit

fSCK Master mode 0 18

SPI clock frequency MHz
1/tc(SCK) Slave mode 0 18
tr(SCK) SPI clock rise and fall
Capacitive load: C = 30 pF 8
tf(SCK) time
tsu(NSS)(1) NSS setup time Slave mode 4 tPCLK -
th(NSS)(1) NSS hold time Slave mode 73 -
(1)
tw(SCKH) Master mode, fPCLK = 36 MHz,
SCK high and low time 50 60
tw(SCKL)(1) presc = 4
Data input setup time
tsu(MI) (1) SPI 1 -
Master mode
Data input setup time
tsu(SI)(1) - 1 -
Slave mode
Data input hold time
th(MI) (1) SPI 1 -
Master mode
Data input hold time
th(SI)(1) - 3 -
Slave mode
Slave mode, fPCLK = 36 MHz, ns
0 55
ta(SO)(1)(2) Data output access time presc = 4
Slave mode, fPCLK = 24 MHz 0 4 tPCLK
tdis(SO)(1)(3) Data output disable time Slave mode 10
tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25
Master mode (after enable
tv(MO)(1) Data output valid time - 3
edge)
th(SO)(1) Slave mode (after enable edge) 25 -
Data output hold time Master mode (after enable
th(MO)(1) 4 -
edge)
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 29. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK)

tSU(NSS) th(NSS)

CPHA= 0
SCK Input

CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1

ta(SO) tv(SO) th(SO) tr(SCK) tdis(SO)

tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
th(SI)
ai14134c

Figure 30. SPI timing diagram - slave mode and CPHA = 1(1)

NSS input
tSU(NSS) tc(SCK) th(NSS)

CPHA=1
SCK Input

CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1

tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI) th(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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STM32F101x4, STM32F101x6 Electrical characteristics

Figure 31. SPI timing diagram - master mode(1)

High

NSS input

tc(SCK)

CPHA= 0
SCK Input

CPOL=0
CPHA= 0
CPOL=1

CPHA=1
SCK Input

CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN

th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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Electrical characteristics STM32F101x4, STM32F101x6

5.3.17 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 8.
Note: It is recommended to perform a calibration after each power-up.

Table 41. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDA Power supply - 2.4 - 3.6 V

fADC ADC clock frequency - 0.6 - 14 MHz
fS(1) Sampling rate - 0.043 - 1 MHz
fADC = 14 MHz - - 823 kHz
fTRIG(1) External trigger frequency
- - - 17 1/fADC
0 (VSSA or VREF-
VAIN Conversion voltage range(2) - - VREF+ V
tied to ground)
See Equation 1 and
RAIN(1) External input impedance - - 50 κΩ
Table 42 for details
RADC(1) Sampling switch resistance - - - 1 κΩ
Internal sample and hold
CADC(1) - - - 8 pF
capacitor
fADC = 14 MHz 5.9 µs
tCAL(1) Calibration time
- 83 1/fADC

Injection trigger conversion fADC = 14 MHz - - 0.214 µs

tlat(1)
latency - - - 3(3) 1/fADC

Regular trigger conversion fADC = 14 MHz - - 0.143 µs

tlatr(1)
latency - - - 2(3) 1/fADC
0.107 - 17.1 µs
tS(1) Sampling time fADC = 14 MHz
1.5 - 239.5 1/fADC
tSTAB(1) Stabilization time - 14 1/fADC
fADC = 14 MHz 1 - 18 µs
Total conversion time
tCONV(1) 14 to 252 (tS for sampling +12.5 for
(including sampling time) - 1/fADC
successive approximation)
1. Guaranteed by design, not tested in production.
2. VREF+ is internally connected to VDDA and VREF- is be internally connected to VSSA.
3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.

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STM32F101x4, STM32F101x6 Electrical characteristics

Equation 1: RAIN max formula:

TS
R AIN < ---------------------------------------------------------------
N+2
- – R ADC
f ADC × C ADC × ln ( 2 )

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 42. RAIN max for fADC = 14 MHz(1)

Ts (cycles) tS (µs) RAIN max (kΩ)

1.5 0.11 0.4

7.5 0.54 5.9
13.5 0.96 11.4
28.5 2.04 25.2
41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
1. Guaranteed by design, not tested in production.

Table 43. ADC accuracy - limited test conditions(1) (2)

Symbol Parameter Test conditions Typ Max(3) Unit

ET Total unadjusted error fPCLK2 = 28 MHz, ±1.3 ±2

EO Offset error fADC = 14 MHz, RAIN < 10 kΩ, ±1 ±1.5
VDDA = 3 V to 3.6 V
EG Gain error ±0.5 ±1.5 LSB
TA = 25 °C
ED Differential linearity error Measurements made after ±0.7 ±1
EL Integral linearity error ADC calibration ±0.8 ±1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should
be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially
inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
3. Based on characterization, not tested in production.

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Electrical characteristics STM32F101x4, STM32F101x6

Table 44. ADC accuracy(1) (2) (3)

Symbol Parameter Test conditions Typ Max(4) Unit

ET Total unadjusted error ±2 ±5

fPCLK2 = 28 MHz,
EO Offset error fADC = 14 MHz, RAIN < 10 kΩ, ±1.5 ±2.5
EG Gain error VDDA = 2.4 V to 3.6 V ±1.5 ±3 LSB
ED Differential linearity error Measurements made after ±1 ±2
ADC calibration
EL Integral linearity error ±1.5 ±3
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
4. Based on characterization, not tested in production.

Figure 32. ADC accuracy characteristics

VDDA
[1LSBIDEAL =
4096
EG
(1) Example of an actual transfer curve
4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET=Total u nadjusted er ror: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset e rror: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain er ror: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential linearity error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral linearity error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1

0 1 2 3 4 5 6 7 4093 4094 4095 4096

VSSA VDDA ai15497

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STM32F101x4, STM32F101x6 Electrical characteristics

Figure 33. Typical connection diagram using the ADC

VDD STM32F10xxx

Sample and hold ADC

VT converter
0.6 V
RAIN(1) AINx RADC(1)
12-bit
converter
VT
VAIN 0.6 V
Cparasitic CADC(1)
IL±1 µA

ai14139d

1. Refer to Table 41 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 34. The 10 nF capacitors
should be ceramic (good quality). They should be placed them as close as possible to the
chip.

Figure 34. Power supply and reference decoupling

STM32F10xx4/6

VDDA

1 µF // 10 nF

VSSA

ai15498

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Electrical characteristics STM32F101x4, STM32F101x6

5.3.18 Temperature sensor characteristics

Table 45. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope 4.0 4.3 4.6 mV/°C
V25(1) Voltage at 25°C 1.34 1.43 1.52 V
tSTART(2) Startup time 4 - 10 µs
ADC sampling time when reading the
TS_temp(3)(2) - - 17.1 µs
temperature
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.

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STM32F101x4, STM32F101x6 Package characteristics

6 Package characteristics

6.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

6.2 VFQFPN36 package information

Figure 35. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package outline
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1. Drawing is not to scale.

DocID15058 Rev 6 71/87

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Package characteristics STM32F101x4, STM32F101x6

Table 46. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.800 0.900 1.000 0.0315 0.0354 0.0394

A1 - 0.020 0.050 - 0.0008 0.0020
A2 - 0.650 1.000 - 0.0256 0.0394
A3 - 0.200 - - 0.0079 -
b 0.180 0.230 0.300 0.0071 0.0091 0.0118
D 5.875 6.000 6.125 0.2313 0.2362 0.2411
D2 1.750 3.700 4.250 0.0689 0.1457 0.1673
E 5.875 6.000 6.125 0.2313 0.2362 0.2411
E2 1.750 3.700 4.250 0.0689 0.1457 0.1673
e 0.450 0.500 0.550 0.0177 0.0197 0.0217
L 0.350 0.550 0.750 0.0138 0.0217 0.0295
K 0.250 - - 0.0098 - -
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 36. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package recommended footprint

 

 

 





 



 


 



:2?&0?6

1. Dimensions are expressed in millimeters.

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Package characteristics STM32F101x4, STM32F101x6

Device Marking for VFQFPN36

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.

Figure 37. VFQFPN36 marking example (package top view)

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1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.

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STM32F101x4, STM32F101x6 Package characteristics

6.3 LQFP64 package information

Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

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1. Drawing is not to scale.

Table 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -

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Package characteristics STM32F101x4, STM32F101x6

Table 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 39. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package

recommended footprint

 


  






 


 





AIC

1. Dimensions are expressed in millimeters.

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STM32F101x4, STM32F101x6 Package characteristics

Device Marking for LQFP64

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.

Figure 40. LQFP64 marking example (package top view)

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1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.

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Package characteristics STM32F101x4, STM32F101x6

6.4 LQFP48 package information

Figure 41. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

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STM32F101x4, STM32F101x6 Package characteristics

Table 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package characteristics STM32F101x4, STM32F101x6

Figure 42. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

recommended footprint




 
 



 



 
 







AID

1. Dimensions are expressed in millimeters.

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Device Marking for LQFP48

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.

Figure 43. LQFP48 marking example (package top view)

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1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.

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Package characteristics STM32F101x4, STM32F101x6

6.5 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 8: General operating conditions on page 31.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in ° C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 49. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

45
LQFP 64 - 10 x 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
55
LQFP 48 - 7 x 7 mm / 0.5 mm pitch
ΘJA °C/W
Thermal resistance junction-ambient
32
UFQFPN 48 - 6 x 6 mm / 0.5 mm pitch
Thermal resistance junction-ambient
18
VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch

6.5.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.

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6.5.2 Evaluating the maximum junction temperature for an application

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 50: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).
The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F101xx junction temperature range.

Example: high-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 49 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the junction temperature range of the STM32F101xx (–40 < TJ < 105 °C).

Figure 44. LQFP64 PD max vs. TA

700
600
500
PD (mW)

400
300 Suffix 6
200
100
0
65 75 85 95 105 115

TA (°C)

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Ordering information scheme STM32F101x4, STM32F101x6

7 Ordering information scheme

Table 50. Ordering information scheme

Example: STM32 F 101 C 4 T 6 A xxx

Device family
STM32 = ARM-based 32-bit microcontroller

Product type
F = general-purpose

Device subfamily
101 = access line

Pin count
T = 36 pins
C = 48 pins
R = 64 pins

Flash memory size

4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory

Package
T = LQFP
U = VFQFPN

Temperature range
6 = Industrial temperature range, –40 to 85 °C.

Internal code
“A” or blank(1)

Options
xxx = programmed parts
TR = tape and real
1. For STM32F101x6 devices with a blank internal code, please refer to the STM32F103x6/8/B datasheet
available from the ST website: www.st.com.

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact the nearest ST sales office.

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STM32F101x4, STM32F101x6 Revision history

8 Revision history

Table 51. Document revision history

Date Revision Changes

23-Sep-2008 1 Initial release.

I/O information clarified on page 1. Figure 7: Memory map modified.
In Table 4: Low-density STM32F101xx pin definitions: PB4, PB13, PB14,
PB15, PB3/TRACESWO moved from Default column to Remap column.
VREF- is not available in the offered packages: Figure 1: STM32F101xx
Low-density access line block diagram, Figure 10: Power supply scheme
and Figure 34: Power supply and reference decoupling updated,
Figure 30: Power supply and reference decoupling (VREF+ not
07-Apr-2009 2
connected to VDDA) removed.
Note modified in Table 12: Maximum current consumption in Run mode,
code with data processing running from Flash and Table 14: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
Figure 15, Figure 16 and Figure 17 show typical curves.
ACCHSI max values modified in Table 23: HSI oscillator characteristics.
Small text changes.
Note 5 updated and Note 4 added in Table 4: Low-density STM32F101xx
pin definitions.
VRERINT and TCoeff added to Table 11: Embedded internal reference
voltage. Typical IDD_VBATvalue added in Table 15: Typical and maximum
current consumptions in Stop and Standby modes. Figure 14: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
fHSE_ext min modified in Table 19: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator
characteristics and Table 22: LSE oscillator characteristics (fLSE =
24-Sep-2009 3 32.768 kHz), notes modified and moved below the tables.
Note 1 modified below Figure 20: Typical application with an 8 MHz
crystal.
Table 23: HSI oscillator characteristics modified. Conditions removed from
Table 25: Low-power mode wakeup timings.
Figure 27: Recommended NRST pin protection modified.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 49.
Jitter added to Table 26: PLL characteristics.
CADC and RAIN parameters modified in Table 41: ADC characteristics.
RAIN max values modified in Table 42: RAIN max for fADC = 14 MHz.
Small text changes.
Added VFQFPN48 package.
Updated note 2 below Table 38: I2C characteristics
20-May-2010 4 Updated Figure 28: I2C bus AC waveforms and measurement circuit(1)
Updated Figure 27: Recommended NRST pin protection
Updated Section 5.3.12: I/O current injection characteristics

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Revision history STM32F101x4, STM32F101x6

Table 51. Document revision history (continued)

Date Revision Changes

Updated footnotes below Table 5: Voltage characteristics on page 30 and

Table 6: Current characteristics on page 31
Updated tw min in Table 19: High-speed external user clock
characteristics on page 43
19-Apr-2011 5
Updated startup time in Table 22: LSE oscillator characteristics (fLSE =
32.768 kHz) on page 46
Added Section 5.3.12: I/O current injection characteristics
Updated Section 5.3.13: I/O port characteristics
Updated:
– All GPIOs are high current...’ in Section 2.3.22: GPIOs (general-
purpose inputs/outputs)
– first sentence in Output driving current
– Table 2: Low-density STM32F101xx device features and peripheral
counts, Table 4: Low-density STM32F101xx pin definitions,
– Table 6: Current characteristics
– Table 8: General operating conditions
– Table 18: Peripheral current consumption
– notes in Table 38: I2C characteristics
– note 2. in Table 44: ADC accuracy
– title of Table 39: SCL frequency (fPCLK1= MHz, VDD_I2C = 3.3 V)
– reference for ‘VESD(CDM)’ in Table 30: ESD absolute maximum ratings
25-Sep-2015 6 – Table 50: Ordering information scheme,
– Table 49: Package thermal characteristics,
– Figure 28: I2C bus AC waveforms and measurement circuit(1)
Added
– note 5. in Table 23: HSI oscillator characteristics
– Figure 37: VFQFPN36 marking example (package top view)
– Figure 40: LQFP64 marking example (package top view)
– Figure 43: LQFP48 marking example (package top view)
Corrected
– Corrected ‘tf(IO)out’ in Figure 26: I/O AC characteristics definition
– Sigma letter in Section 5.1.1: Minimum and maximum values
Removed
– UFDFPN48 package
– First sentence in Section 5.3.16: Communications interfaces

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STM32F101x4, STM32F101x6

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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