LogiCORE IP 3GPP Mixed Mode

Turbo Decoder v2.0

PB009 (v2.0) November 18, 2015 Product Brief

Introduction LogiCORE IP Facts Table

The LogiCORE™ IP 3GPP Mixed Mode Turbo Core Specifics
Decoder provides a flexible turbo convolutional UltraScale+™ Families
decode function for both LTE and WCDMA air Supported UltraScale™ Architecture
interfaces. The implementation is compliant Device Family (1) Zynq®-7000 All Programmable SoC
with the requirements set out in both [Ref 1] 7 Series

and [Ref 2]. The core provides an optimized Supported User

AXI4-Stream
Interfaces
turbo decode function for base stations at all
form factors, from femto to macrocells. The Provided with Core
decoder, when used with a TCC encoder, Design Files Encypted RTL
provides an effective way of transmitting data Example Design VHDL
reliably over noisy data channels.
Test Bench VHDL

Constraints File Not Provided

Additional Documentation
Simulation Encrypted VHDL
A full product guide is available for this core. Model C Model and MATLAB® Model
Access to this material can be requested by Supported
N/A
clicking on this registration link: S/W Driver
www.xilinx.com/member/mm_tcc_dec_eval/index.htm Tested Design Flows(2)
Design Entry Vivado® Design Suite
Features For supported simulators, see the
Simulation
• Three versions of this core can be Xilinx Design Tools: Release Notes Guide.

generated, each supporting different Synthesis Vivado Synthesis

standard options: Support
° LTE only Provided by Xilinx at the Xilinx Support web page

UMTS only Notes:

°
1. For a complete listing of supported devices, see the Vivado IP
° LTE and UMTS catalog.
2. For the supported versions of the tools, see the
• When UMTS and LTE are both supported Xilinx Design Tools: Release Notes Guide.

the core can switch between different

standards on a block by block basis.
• Each core is completely self contained,
requiring nothing else to decode data.
• All 3GPP LTE block sizes supported: 188
different block sizes in the range 40–6144
• All 3GPP UMTS block sizes supported, that
is block sizes in the range 40-5114.

See Feature Summary for additional features.

© Copyright 2012–2015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands
included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective
owners.

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PB009 (v2.0) November 18, 2015 Product Specification
 Product Brief

Feature Summary
• Configurable with either 1, 2, 4 or 8 decode units, allowing resource utilization to be optimized
while meeting system performance requirements at all base station form factors.
• Dynamically selectable number of iterations 1-15.
• Support for MAX, MAX_SCALE and MAX_STAR algorithms.
• AXI4-Stream interfaces used for control and data input/output.
• C model and MATLAB MEX function available for bit accurate modelling of error correcting
performance.
• Number representation: Twos complement fractional.
• Data Input: 7 or 8 bits (4 or 5 integer bits with 3 fractional bits)
• Hardware DSP units can be used instead of logic resources to tailor the core resource usage to
specific user applications.
• Demonstration test bench to show an example of core usage.
• Integrated scheduler ensures that decode latency remains virtually constant with variable
block sizes.

Overview
The TCC decoder is used in conjunction with a TCC encoder to provide an effective way of
transmitting data reliably over noisy data channels. The turbo decoder operates very well under
low signal-to-noise conditions and provides a performance close to the theoretical optimal
performance defined by the Shannon limit [Ref 3].

References
1. 3GPP TS 25.212 "Multiplexing and channel coding (FDD)", v10.1.0
2. 3GPP TS 36.212 "Multiplexing and channel coding", v10.3.0
3. C. Berrou, A. Glavieux, and P. Thitimajshima, Near Shannon Limit Error-correcting Coding and
Decoding Turbo Codes, IEEE Proc 1993 Int Conf. Comm., pp1064-1070

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PB009 (v2.0) November 18, 2015
 Product Brief

Technical Support
Xilinx provides technical support at the Xilinx Support web page for this LogiCORE™ IP product
when used as described in the product documentation. Xilinx cannot guarantee timing,
functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.

To contact Xilinx Technical Support, navigate to the Xilinx Support web page.

Licensing and Ordering Information

This Xilinx LogiCORE™ IP module is provided under the terms of the Xilinx Turbo Code LogiCORE IP
License Terms.The module is shipped as part of the Vivado Design Suite. For full access to all core
functionalities in simulation and in hardware, you must purchase a license for the core. Contact
your local Xilinx sales representative for information about pricing and availability.

For more information, visit the 3GPP Mixed Mode Turbo Decoder product page.

Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property
page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools,
contact your local Xilinx sales representative.

Disclaimer: France Telecom, for itself and certain other parties, claims certain intellectual property
rights covering Turbo Codes technology, and has decided to license these rights under a licensing
program called the Turbo Codes Licensing Program. Supply of this IP core does not convey a
license nor imply any right to use any Turbo Codes patents owned by France Telecom, TDF or GET.
Contact France Telecom for information about its Turbo Codes Licensing Program at the following
address:

France Telecom R&D,

VAT/TURBOCODES,
38, rue du Général Leclerc,
92794 Issy Moulineaux,
Cedex 9,
France.

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PB009 (v2.0) November 18, 2015
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Evaluation License
An evaluation license is available for this core. The evaluation version of the core operates in the
same way as the full version for several hours, depending on clock frequency. Operation is then
disabled and the data output does not change. If you notice this behavior in hardware, it means
that you are using an evaluation version of the core. The Xilinx tools warn that an evaluation license
is being used during netlist implementation. If a full license is installed in order for the core to run
on hardware, delete the old configuration file and re-create the core from new.

Revision History
The following table shows the revision history for this document:

Date Version Description of Revisions

11/18/2015 2.0 UltraScale+ device support added.
04/02/2014 2.0 Characterization data added to PG030.
12/18/2013 2.0 Added UltraScale architecture support.
03/20/2013 2.0 Updated for Vivado design tools.
01/18/2012 1.0 Xilinx initial release.

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