IC Compiler I-2013.
12 CAE Training
Hierarchical Flow
Design Planning CAE
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Enhanced Data Flow Analysis and
Improved RDL Route Shielding
• Improved RDL routing flow
Read Verilog
with support for RDL net
shielding
Initial Placement • New, highly integrated Data Flow
• Support for creating and Analysis tool
removing RDL net shields with
new create_rdl_shield I/O Planning
• DFA Control Center panel organizes
command RDL Routing
functions for easy operation
• Reporting pinpoints blockages Data Flow
Analysis • All legacy DFA critical functions are
and other issues that prevent supported
complete shielding
Plan Group
Shaping
Power Network
Synthesis
Timing Budgeting
Hierarchical Flow
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Two Major Projects for I-2013.12
• RDL Shielding
– New command (RDL routing flow)
• Data Flow Analysis
– LayoutWindow integration
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IC Compiler I-2013.12 CAE Training
RDL Shielding
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Overview
• To simplify shield wire creation and removal for routed
RDL nets, IC Compiler supports the new
create_rdl_shield command
• To improve the shielding ratio, routing resources for
shielding wires must be reserved during the routing
stage
– The route_rdl_flip_chip command routes RDL nets and
reserves additional space to create shielding wires
– The push_rdl_route or optimize_rdl_route commands
also reserve space for shielding wires on RDL nets
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Flow to Create Shielding Wires for Nets
• P/G P/G P/G
• P/G P/G P/G
define_routing_rule Define shielding rules
set_net_routing_rule Set rules to target nets
set_route_rdl_options Set the shielding net
route_rdl_flip_chip Route RDL nets
push_rdl_route Modify routes (Optional)
/optimize_rdl_route
create_rdl_shield Create shielding wires
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Define the Shielding Net
set_route_rdl_options
set_route_rdl_options
[-layer_bump_spacings {layer_spacing_list}]
[-connect_edge_center true | false]
[-detour_cost low | high]
[-secondary_routing_layer_cost low | medium | high]
[-layer_routing_angles {layer_angle_list}]
[-shielding_net net_name]
• Example
set_route_rdl_options -shielding_net VSS \
-layer_bump_spacings {M8 5}
• Report current RDL route options
report_route_rdl_options
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Create Shielding Wires
create_rdl_shield
create_rdl_shield
-layers layer_list
[-nets collection_of_nets | -nets_in_file
nets_file]
[-mode new | unshield | reshield]
[-shield_on_bump true | false]
[-shield_via_tie true | false]
[-shield_routing_tie true | false]
[-trim_floating true | false]
Example:
create_rdl_shield –layers {ZA M8} –mode new \
–nets {PAD_NET1 PAD_NET2}
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Creating and Replacing Shield Wires
create_rdl_shield –mode mode_type
-mode new
• Creates new shielding wires on target layers for unshielded nets
• If a target net is fully or partially shielded on a target layer, no new
shielding wire is created on that layer
• If a target net does not have shielding rules defined by
define_routing_rule or its shielding width of target layer defined by
define_routing_rule is 0, the tool skips this net and issues a
warning message
-mode unshield
• Removes existing shielding wires on target layer that are associated with
shielded nets
• Removes vias and routes used to tie (route type is “shield dynamic”)
-mode reshield
• Creates new shielding wires on target layer after unshielding the nets
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Example #1
create_rdl_shield –layers ZA –nets PAD_NET1 \
–shield_on_bump true
create_rdl_shield –layers ZA –nets PAD_NET1 \
–shield_on_bump false
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Example #2
• When creating shielding wires for PAD_NET1 and PAD_NET2 with ground net gndNet,
you can use the following command:
create_rdl_shield –layers {ZA M8}
–mode new
–nets {PAD_NET1 PAD_NET2}
• This command reports the shielding ratios per net:
Layer ZA :
Shielded 80% side-wall of (PAD_NET1)
Shielded 100% side-wall of (PAD_NET2)
Shielded 2 nets with average ratio as follows
1) 90.00% (total shield ratio/number of shielded nets)
2) 95.00% (total shield length/total shielded net length)
Layer M8:
Shielded 85% side-wall of (PAD_NET1)
Shielded 90% side-wall of (PAD_NET2)
Shielded 2 nets with average ratio as follows
1) 87.50% (total shield ratio/number of shielded nets)
2) 88.00% (total shield length/total shielded net length)
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DRC Concerns
• Shielding wires created by create_rdl_shield
should not have any DRC violations, including spacing
violations or 45 degree acute angles
• Fat rules are not honored in the RDL router
• Example violations
– Spacing violation formed by two shielding
wires of different shielded nets
– A 45 degree acute angle violation formed
by shielding wires is a violation
– (90 degree angle is OK)
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Recommended Flow to Update Nets With
Existing Shields
1) Remove shielding wires with one of these commands:
• create_rdl_shield –mode unshield
• remove_route_by_type –shield
• remove_net_shape [get_net_shapes -shield_of N]
2) Apply push_rdl_route or optimize_rdl_route to
the nets
3) Create shielding wires for targets
create_rdl_shield –mode new
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I-2013.12 Design Planning
Data Flow Analysis (DFA)
Layout Window Integration
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Data Flow Analysis
UI Integrated Into IC Compiler Layout Window
• Same capabilities, and more, Before 2013.12: Two window UI
all available in Layout Window
– Consumes less screen space
DFA Viewer IC Compiler
Window Layout Window
• Logical modules are presented
as module object blocks to the
left of the design
– Can easily create a placement
movebounds from a module
object block 2013.12: Single window UI
• Logical connectivity analysis
now performed directly in
Layout Window
– Module sizes represent actual
area @ utilization %
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Data Flow Analysis
Accessing The 3 Parts Of Data Flow Analysis
DFA includes 3 parts: Pull-downs
1. Logic Connectivity Analysis
– Performed in DFA Viewer DFA Viewer IC Compiler
Window Layout Window
– Now integrated in Layout
Window
2. Advanced Flyline Analysis
– Formerly accessed from
pull-down Tabbed palette
– Now accessed from palette
3. Macro Editing
– Formerly accessed from
pull-down
– Now accessed from palette
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Data Flow Analysis
Logic Connectivity Analysis In Layout Window
• Module data, such as hard DFA Modules / Hierarchy Browser
macro count and utilization
displayed on each DFA
module (lower left corner)
• Can color and cross-color
DFA children modules in
layout
– Can “mirror” colors set in
the Hierarchy Browser
– Same UI command is
set_hierarchy_color
• Can save module object
block layout to a file, then
reload file to resume work
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Data Flow Analysis
Logic Connectivity Analysis, Use Mouse To See More
Click or Cursor
1. Left click inside DFA module
– Displays total # of net
connections to other module
object blocks (red lines) 3
– Displays connections to 2
module I/Os (yellow lines) 1
2. Place cursor over module
object block edge
– Displays module information
in an InfoTip
3. Left click on a connection
flyline
– Displays net names, by
driver/load direction
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Data Flow Analysis
Summary
• We continue to invest in DFA Integrated In Layout Window
DFA and other floorplan
analysis capabilities
• Our objective is to
provide assistance in
addition to automation
• Your success is our
success
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Agenda
End-of-Life of ILMs
Attribute to Query Blocks With Abstraction Data
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Agenda
End-of-Life of ILMs
Attribute to Query Blocks With Abstraction Data
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End-of-Life of ILMs
• Starting with version I-2013.12, the following commands are
obsolete as part of the phased end-of-life of ILMs:
create_ilm, create_ilm_models,
write_interface_timing, compare_interface_timing
– IC Compiler issues an OBS-030 error message when you use any of
them
Error: Starting from the 2013.12 release, the command
%s is no longer supported. (OBS-030)
• IC Compiler issues an OBS-001 message when you use the
following commands:
get_ilms, report_ilm, check_ilm,
get_ilm_objects, propagate_ilm
Warning: Starting from the 2014.09 release, the command %s
will no longer be supported (OBS-001)
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End-of-Life of ILMs
• IC Compiler issues an OBS-031 warning message when you use
ILMs at the top level
Warning: Starting from the 2014.09 release, ILMs will no longer
be supported. Use blocks with block-abstraction information
instead. (OBS-031)
• To support the hierarchical clock mesh flow, the
propagate_ilm –clock_mesh_annotation command is
replaced by the
propagate_clock_constraints –clock_mesh_annotation
command
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Agenda
End-of-Life of ILMs
Attribute to Query Blocks With Abstraction Data
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Attribute to Query Blocks With
Abstraction Data
• Overview
– Starting with H-2013.03-SP2, IC Compiler supports querying
blocks that are annotated with abstraction information
• Benefit
– Improved ease-of-use; you can now check if a block is annotated
with abstraction data without loading the top-level design
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Usage Details
• To get a collection of blocks for which block abstractions
have been created, run the following commands after you
open the design library:
set BLOCK_LIST {block1 block2 ...}
get_mw_cels \
–filter "@has_block_abstraction == true" \
$BLOCK_LIST
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Summary
• The phased end-of-life of ILMs continues with the
create_ilm and associated commands being made
obsolete in version I-2013.12
• Without loading the top-level design, you can check if a
block has a corresponding block abstraction based on
the has_block_abstraction attribute setting
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Thank You
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