SULIT
(EMT 245)
15
Appendix 3
[Lampiran 3]
Instruction Code Bytes T States Machine Cycles
Instruction Code Bytes T States Machine Cycles
8085A 8080A
8085A 8080A
ACI DATA CE data 2 7 7 F R
LXI RP,DATA 16 00RP 0001 data16 3 10 10 F R R
ADC REG 1000 1SSS 1 4 4 F
MOV REG,REG 01DD DSSS 1 4 5 F*
ADC M 8E 1 7 7 F R
MOV M,REG 0111 0SSS 1 7 7 F W
ADD REG 1000 0SSS 1 4 4 F
MOV REG, M 01DD D110 1 7 7 F R
ADD M 86 1 7 7 F R
MVI REG, DATA 00DD D110 data 2 7 7 F R
ADI DATA C6 data 2 7 7 F R
MVI M, DATA 36 data 2 10 10 F R W
ANA REG 1010 0SSS 1 4 4 F NOP 00 1 4 4 F
ANA M A6 1 7 7 F R ORA REG 1011 0SSS 1 4 4 F
ANI DATA E6 data 2 7 7 F R
ORA M B6 1 7 7 F R
CALL LABEL CD addr 3 18 17 S R R W W*
CC LABEL DC addr 3 9/18 11/17 .
S R /S R R W W*
ORI DATA F6 data 2 7 7 F R
CM LABEL FC addr 3 9/18 11/17 .
S R /S R R W W*
OUT
PCHL
PORT D3 data
E9
2
1
10
6
10
5
F R O
S*
CMA 2F 1 4 4 F
POP RP 11 RP 0001 1 10 10 F R R
CMC 3F 1 4 4 F
PUSH RP 11 RP 0101 1 12 11 S W W*
CMP REG 1011 1SSS 1 4 4 F
RAL 17 1 4 4 F
1 7 7 F R
CMP M BE
3 9/18 11/17
.
S R /S R R W W*
RAR 1F 1 4 4 F
CNC LABEL D4 addr
3 9/18 11/17
.
S R /S R R W W*
RC D8 1 6/12 5/11 S/S R R*
CNZ LABEL C4 addr
3 9/18 11/17
.
S R /S R R W W*
RET C9 1 10 10 F R R
CP LABEL
CPE LABEL
F4 addr
EC addr 3 9/18 11/17
.
S R /S R R W W*
RIM (8085A only) 20
07
1
1
4
4
-
4
F
RLC F
F R
CPI DATA FE data 2 7 7
.
S R /S R R W W* RM F8 1 6/12 5/11 S/S R R*
CPO LABEL
CZ LABEL
E4 addr
CC addr
3
3
9/18
9/18
11/17
11/17
.
S R /S R R W W* RNC D0 1
1
6/12
6/12
5/11
5/11
S/S R R*
RNZ C0 S/S R R*
F
DAA 27 1 4 4
RP F0 1 6/12 5/11 S/S R R*
F BB
DAD RP 00RP 1001 1 10 10
RPE E8 1 6/12 5/11 S/S R R*
F*
DCR REG 00SS S101 1 4 5
RPD E0 1 6/12 5/11 S/S R R*
1 10 10 F R W
DCR M 35 1 4 4
RRC 0F F
1 6 5 S*
DCX RP 00RP 1011 1 12 11
RST N 11XX X111 S W W*
1 4 4 F
DI F3 1 6/12 5/11
RZ C8 S/S R R*
1 4 4 F
EI FB 1 4 4
SBB REG 1001 1SSS F
1 5 7 F B
HLT 76 1 7 7
SBB M 9E F R
2 10 10 F R I
IN PORT DB data 2 7 7
SBI DATA DE data F R
1 4 5 F*
INR REG 00SS S100 3 16 16
SHLD ADDR 22 addr F R R WW
1 10 10 F R W
INR M 34 1 4 -
SIM (8085A only) 30 F
1 6 5 S*
INX RP 00RP 0011 1 6 5
SPHL F9 S*
†
DA addr 3 7/10 10 F R/F R R
JC LABEL 32 addr 3 13 13
†
STA ADDR F R R W
JM LABEL FA addr 3 7/10 10 F R/F R R
STAX RP 000X 0010 1 7 7 F W
JMP LABEL C3 addr 3 10 10 F R R
STC 37 1 4 4
F
JNC LABEL D2 addr 3 7/10 10 F R/F R R †
SUB REG 1001 0SSS 1 4 4
C2 addr †
F
JNZ LABEL 3 7/10 10 F R/F R R
96 1 7 7
JP LABEL F2 addr †
SUB M F R
3 7/10 10 F R/F R R
SUI DATA D6 data 2 7 7
JPE LABEL EA addr F R
3 7/10 10 F R/F R R †
E2 addr XCHG EB 1 4 4 F
JPO LABEL
3 7/10 10 F R/F R R †
JZ LABEL CA addr XRA REG 1010 1SSS 1 4 4
F
3 7/10 10 F R/F R R †
LDA ADDR 3A addr XRA M AE 1 7 7
FR
3 13 13 FRRR
LDAX RP 000X 1010 XRI DATA EE data 2 7 7
FR
1 7 7 FR
LHLD ADDR 2A addr XTHL E3 1 16 18
F RRWW
3 16 16 FRRRR
Machine cycle types:
* Five clock period instruction fetch with 8080A
F Four clock period instr fetch † The longer machine cycle sequence applies regardless of conditio n evaluation with 8080A
S Six clock period instr fetch . An extra READ cycle (R) will occur for this condition with 8080A
R Memory read
I I/O read
W Memory write
O I/O write
B Bus idle
X Variable or optional binary digit
DDD Binary digits identifying a destination register B=000, C=001, D=010, Memory=110
SSS Binary digits identifying a source register E=011, H=100, L=101, A=111
RP Register Pair BC=00, HL=10, DE=01, SP=11
SULIT
(EMT 245)
15
