Transistor Amplifier

Insert your group members’ names… …here in this two-column header.

Batangas State University Main Campus II

College of Engineering, Architecture and Fine Arts
Electronics, Instrumentation and Control, and Mechatronics Engineering Department

Abstract 1. Introduction

Insert short summary of the whole design in Insert your research.

this column.
1.1. Insert sub topics

1.2. Insert sub topics

2. Objectives

The main goal of this design is to improve the

students’ ability in Electronic Circuit
Analysis and Design. It also specifically
seeks the following objectives:
 To design an amplifier with the
specifications given in Table 1
 To construct an amplifier by
applying different techniques and
knowledge in designing transistor
amplifiers
 To prototype the designed amplifier
in a breadboard.
 Table 1: Project Specifications 0.015µF
0.047µF
Specification Value 0.1µF
1µF
Gain 100-130 10µF

Power Minimum at VCC = Connecting - -

12V Wires

Load Resistance 1 kΩ Breadboard - -

Frequency Range 1kHz – 10 kHz

3.2. Methodology
Maximum Input 10µA
Current
This section covers the methodologies the
Output Swing 5Vp-p
researchers had undergone. Insert your
methodology

3. Materials and Methodology

The materials and methodologies used and

applied by the researchers in the designing
the circuit are covered in this section.

3.1. Materials

Table 2 shows the materials used by the

researchers in designing the amplifier.

Table 2: Materials
Figure 1: Final Schematic
Materials Qty Value

BJT NPN 2 2N5551 4. Results and Discussion

150kΩ
Resistors 11
120kΩ
22kΩ This section covers the findings and the
8.2kΩ discussion of the entire design of the
1.6kΩ
1kΩ amplifier.
620Ω
200Ω
120Ω 4.1. Setting the DC Level
20Ω
5600pF
Capacitors 7 Voltage divider bias is used in the first stage
0.015µF
of the amplifier. The researchers set the
quiescent points of the transistor by To make sure that the ICQ sit in the middle of
computing for the proper bias resistors. This the DC load line, the researchers set the VC to
is to prevent distortion in the input and output be exactly half of the supply voltage as
signal. By letting the input AC signal sit on a described by Scherz (see references).
large DC level, the negative half cycle of the
AC signal is eliminated. To accomplish this, 1
𝑉𝐶 = 𝑉𝐶𝐶 = 6𝑉
the researchers set a q-point value for the base 2
current. The collector resistance can be solved:
𝐼𝐵𝑄 = 5𝑢𝐴 𝑉𝐶𝐶 − 𝐼𝐶𝑄 𝑅𝐶 − 𝑉𝐶 = 0
𝑉𝐶𝐶 − 𝑉𝐶
𝑅𝐶 =
It satisfies the given specification on input 𝐼𝐶𝑄
current. The hFE gain of the 2N5551 BJT 12𝑉 − 6𝑉
= = 8571.428571Ω
NPN transistor is between 80-250. The 0.7𝑚𝐴
researchers used DC operating point analysis
in NI Multisim to compute for the Beta. The researchers used the closest standard
value of resistor, which is 8.2kΩ, as their
collector resistance.

Because there is a large difference in the

chosen resistance than the calculated, DC
currents were recalculated.

𝑉𝐶𝐶 − 𝑉𝐶 6𝑉
𝐼𝐶𝑄 = = = 0.731707𝑚𝐴
𝑅𝐶 8.2𝑘𝛺
𝐼𝐶𝑄 0.731707𝑚𝐴
𝐼𝐵𝑄 = = = 5.22648𝜇𝐴
𝛽 140

Figure 2: DC operating point analysis According to Scherz, by rule of thumb, VE

should be 10% of the supply voltage to
Figure 2 shows that the value of Beta is stabilize the emitter terminal from
around 140. Solving for the collector current, temperature changes.
IC:
𝑉𝐸 = 0.1𝑉𝐶𝐶 = 0.1 × 12𝑉 = 1.2𝑉
𝐼𝐶𝑄 = β𝐼𝐵 = (140)(5𝑢𝐴) = 0.7𝑚𝐴
Emitter resistance can be solved by assuming
that the emitter and collector currents are
equal. Using NI Multisim, the researchers tried the
amplification of the first stage on a 1kΩ load
𝑉𝐸 1.2𝑉 and supplied a 20mVp 1kHz signal on the
𝑅𝐸 = = = 1640Ω
𝐼𝐶𝑄 0.731707𝑚𝐴 input. Figure 3 shows the sample simulation.

The researchers used 1.6kΩ as their emitter

resistance.

To compute for the base resistances, VB must

first be known:

𝑉𝐵 = 𝑉𝐵𝐸 + 𝑉𝐸 = 0.7𝑉 + 1.2𝑉 = 1.9𝑉

To set the bias resistors in the base, the R1 to

R2 ratio must be established.
𝑉𝐶𝐶 𝑅2
𝑉𝐵 =
𝑅1 + 𝑅2
𝑅1 𝑉𝐶𝐶 − 𝑉𝐵 12𝑉 − 1.9𝑉 Figure 3: First Stage
= = ≅ 5.32
𝑅2 𝑉𝐵 1.9𝑉
𝑅1 = 5.32𝑅2 It can be observed that limiting the input
current to 10uA results to a low gain. To
According to Boylestad, the resistance R2 of obtain the gain theoretically, re should first be
the voltage divider configuration should be at established.
most 0.1 times the input resistance seen at the
emitter terminal of the transistor, BRE. 26mV 26mV
re = = = 35.5333Ω
Ie 0.731707𝑚𝐴
𝑅2 = 0.1𝛽𝑅𝐸 = 0.1 × 140 × 1.6𝑘Ω RC ||RL 8.2kΩ ||1kΩ
AV = − =−
= 22400Ω ≅ 𝟐𝟐𝐤𝛀 re 35.5333𝛺
𝑅1 = 5.3158𝑅2 = 119𝑘Ω ≅ 𝟏𝟐𝟎𝐤 = −25.0836

The researchers chose to use 120kΩ and This shows that a single stage amplifier with
22kΩ as their R1 and R2, respectively. input current limited to 10uA is not enough to
produce the specified output. The gain
4.2. Trying-out the First Stage of the computed experimentally is equal to:
Amplifier
 Vo 867mV 𝑉𝐸 1.2𝑉
AV = − =− = −21.675 𝑅𝐸2 = = = 122.45𝛀 ≅ 𝟏𝟐𝟎𝛀
Vi 40mV 𝐼𝐶𝑄 9.8𝑚𝐴

The researchers landed on the decision to use This time, the researchers tried to use fixed
a two-stage amplifier. bias configuration for the base. To compute
for the base bias resistor, Kirchhoff’s Voltage
4.3. DC Bias of the Second Stage of Law is used:
the Amplifier 𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 − 𝑉𝐸 = 0
𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝑉𝐸
𝑅𝐵 =
The DC bias of the second stage should 70𝑢𝐴
accommodate a bigger base current. This is 12𝑉 − 0.7𝑉 − 1.2𝑉
= = 144.29𝑘Ω
because the signal had already undergone 70𝑢𝐴
amplification in the first. Moreover, to allow 𝑹𝑩 ≅ 𝟏𝟓𝟎𝐤𝛀
an output swing of 5Vp-p on a 1kΩ load, the
output current must also be larger than 4mAp- 4.4. Cascading
p. To do this, the researchers tried multiple
values of input impedance that will act as the Figure 4 shows the cascaded amplifier. The
load of the first stage and measured the values of the capacitors are set to a high value
average output current from the first stage. to make sure that the input signal falls in the
This will be the average input signal of the mid-band. It shows an output voltage of
second stage. The average output current as 9.26Vp-p from a 20mVp input signal.
measured from the simulation is 70uAPK.

The researchers set the IBQ of the second stage

to be 70uA.
𝐼𝐵𝑄2 = 70𝜇𝐴
𝐼𝐶𝑄2 = 𝛽𝐼𝐵𝑄2 = 140 × 70𝜇𝐴 = 9.8𝑚𝐴

With VC set to half of VCC and VE set to 10%

of VCC, the bias resistances are calculated
similarly to the first stage:

𝑉𝐶𝐶 − 𝑉𝐶 Figure 4: Cascaded Circuit

𝑅𝐶2 =
𝐼𝐶𝑄2
6𝑉
= = 612.245Ω ≅ 𝟔𝟐𝟎𝛀
9.8𝑚𝐴
 𝑅𝐸2 = 20Ω

4.6. Capacitors

The input and output impedances of

every stage of the amplifier are calculated
to compute for the value of the
capacitances.
𝑅𝑖1 = 𝑅1 || 𝑅2 || 𝐵(𝑟𝑒 + 𝑅𝐸1 )
𝑅𝑖1
Figure 5: Bode Plot 𝑅𝑖1 = 120𝑘Ω || 22𝑘Ω || 140(35.5333Ω
Figure 5 shows that the gain in the mid-band + 330Ω)
is equal to 123.914194V @ frequency of 𝑹𝒊𝟏 = 𝟏𝟑𝟔𝟑𝟕. 𝟐𝟎𝟕𝟏𝟑𝛀
3.947kHz. By simply cascading two 𝑹𝒐𝟏 ≅ 𝑹𝑪 = 𝟖. 𝟐𝒌𝛀
amplifier stages, the gain can be achieved. 𝑅𝑖2 = 𝑅𝐵 || 𝐵(𝑟𝑒 + 𝑅𝐸2 )
26𝑚𝑉
𝑅𝑖2 = 150𝑘Ω ||140 × ( + 33Ω)
4.5. Swamping 9.8𝑚𝐴
𝑹𝒊𝟐 = 𝟒𝟖𝟑𝟎. 𝟔𝟖𝛀
The distortion that resulted from cascading 𝑹𝒐𝟏 ≅ 𝑹𝑪 = 𝟔𝟐𝟎𝛀
the two stages is an effect of too much gain.
To lessen the gain from an amplifier, To calculate the low cutoff capacitors, the
according to Scherz, to stabilize or minimize researchers use the low frequency from the
the effect of emitter transresistance, re, from specified range. They also used 330Ω as their
affecting the gain, swamping is used. source resistance.
𝒇𝑳 = 𝟏𝒌𝑯𝒛
By adding a resistor in series with a bypass 1
𝐶𝑖 =
capacitor will result in lower gain because of 2𝜋(𝑅𝑖 + 𝑅𝑠 )𝑓𝐿
its fair share in the input impedance of the 1
=
circuit. This added resistor also will not affect 2𝜋(13637.20713 + 680Ω) × 1000𝐻𝑧
the emitter resistance, RE, in the DC analysis. = 0.011116𝑢𝐹 ≅ 𝟎. 𝟎𝟏𝟓𝒖𝑭

The researchers use NI Multisim to find the 1

𝐶1−2 =
value of swamping resistor to decrease the 2𝜋(𝑅𝑜1 + 𝑅𝑖2 )𝑓𝐿
gain down to the specified gain. The 1
=
resistances are: 2𝜋(8.2𝑘Ω + 4830.68𝛺) × 1000𝐻𝑧
𝑅𝐸1 = 200Ω = 0.01221𝑢𝐹 ≅ 𝟎. 𝟎𝟏𝟓𝒖𝑭
 1 1
𝐶𝑜 = 𝐶𝑤1 = − (79)𝐶𝑏𝑐 − 𝐶𝑏𝑒
2𝜋(𝑅𝑜2 + 𝑅𝐿 )𝑓𝐿 2𝜋(𝑅𝑜1 ||𝑅𝑖2 )𝑓𝑢
1 1
= =
2𝜋(620Ω + 1kΩ) × 1000𝐻𝑧 2𝜋(8.2𝑘Ω || 4830.68𝛺) × 10𝑘𝐻𝑧
= 0.09824𝑢𝐹 ≅ 𝟎. 𝟏𝒖𝑭 − (79)(6𝑝𝐹) − 20𝑝𝐹
𝐶𝑤1 = 4741.58𝑝𝐹 ≅ 𝟓𝟔𝟎𝟎𝒑𝑭
1
𝐶𝑏1 =
2𝜋(0.1𝑅𝐸 )𝑓𝐿 1
𝐶𝑤2 = − 𝐶𝑏𝑐
1 2𝜋(𝑅𝑜2 ||𝑅𝐿 )𝑓𝑢
=
2𝜋(0.1 × 1.6kΩ) × 1000𝐻𝑧 1
= − 6𝑝𝐹
= 0.9947𝑢𝐹 ≅ 𝟏𝒖𝑭 2𝜋(620Ω || 1kΩ) × 10𝑘𝐻𝑧
𝐶𝑤2 = 0.0415856𝑢𝐹 ≅ 𝟎. 𝟎𝟒𝟕𝒖𝑭
1
𝐶𝑏2 =
2𝜋(0.1𝑅𝐸 )𝑓𝐿 CW1 is connected between the two stages
1 while CW2 is connected in the output.
=
2𝜋(0.1 × 120Ω) × 1000𝐻𝑧
= 13.2629𝑢𝐹 ≅ 𝟏𝟎𝒖𝑭 4.7. Output

From 2N5551 transistor’s datasheet, the The following are the findings of the
values of the input and output capacitance of design. It covers all the specifications that
the transistor are: are met.

𝐶𝑏𝑐 = 6𝑝𝐹 4.7.1. Gain and Frequency

𝐶𝑏𝑒 = 20𝑝𝐹

To filter the high frequency to the specified

high frequency limit of 10kHz, additional
capacitances are added to the circuit.

1
𝐶𝑖 = = 𝐶𝑚𝑖 + 𝐶𝑏𝑒 + 𝐶𝑤1
2𝜋(𝑅𝑖 ||𝑅𝑠 )𝑓𝑢
𝐶𝑚𝑖 = (1 − 𝐴𝑣)𝐶𝑏𝑐
1
𝐶𝑜 = = 𝐶𝑚𝑜 + 𝐶𝑤2
2𝜋(𝑅𝑜 ||𝑅𝐿 )𝑓𝑢 Figure 6: Bode Plot
𝐶𝑚𝑜 ≅ 𝐶𝑏𝑐
Figure 6 shows the bode plot of the final
circuit. It shows that the maximum gain is
approximately 123.9320 and is found on the
mid-band frequency of 3.9811kHz. It shows
that the plot of the frequency appeared bell-
shaped instead of its natural trapezoidal
graph. This is caused by a narrow bandwidth
of 9kHz. To locate the cutoff gain:
Figure 7: Input Signal
𝐴𝑣−3𝑑𝐵 = 0.707𝐴𝑣𝑚𝑖𝑑
= 0.707 × 77.5 = 54.7925 4.7.3. Power
To compute for the power generated to the
It shows that the upper frequency of 10kHz load, the RMS values of current and voltage
has slightly achieved its upper limit. The at the output were needed. Using the
lower frequency limit, 1kHz, on the other voltage/current probe and the power probe in
hand, falls largely below that -3dB gain. NI Multisim, the power can be solved.

4.7.2. Input Characteristics

To produce the best output, the researchers

computed for the input signal needed. To
produce an output of 5V with a gain of 57, the
input signal should be:
𝑉𝑜 4𝑉𝑝−𝑝
𝑉𝑖 = = = 32𝑚𝑉𝑝 − 𝑝
𝐴𝑉 124
𝑜𝑟 16.1290𝑚𝑉𝑝
The input frequency should fall between the
frequency range. It would be better to apply a Figure 8: Output Probe
frequency that will yield to the maximum
gain. The researchers chose to apply 4kHz. It can be seen from Figure 8 that the RMS
Figure 7 shows the applied signal using a voltage and current is equal to 1.80V and
function generator. We can adjust the 1.80mA, respectively. The output power is
frequency and input voltage because in actual equal to:
condition 32mVp-p and 16.1290mVp are not
the exact value to attain the desired output. 𝑷𝑶 = 𝑉𝑅𝑀𝑆 × 𝐼𝑅𝑀𝑆 = 1.80𝑉 × 1.80𝑚𝐴
= 𝟑. 𝟐𝟒𝒎𝑾
4.7.4. Output Swing

By supplying the exact input signal shown in

Figure 7, the output swing of 5Vp-p
achievable. Figure 9 shows an undistorted
sinusoidal output waveform from the
oscilloscope.

Figure 9: Oscilloscope

5. Conclusions

Insert your Conclusions. Answer each

objective briefly.

References
 Practical Electronics for Inventors by
Paul Scherz and Simon Monk 3rd edition
 Electronic Devices and Circuit Theory by
Robert Boylestad 11th edition

Cite your own references.