ECE 8223

ANALOG INTEGRATED CIRCUIT

PROJECT #1 REPORT

Submitted to
DR. RAYMOND S. WINTON

By
KRITSA CHINDANON
 PART I
DESCRIPTION OF PROJECT AND INTENT

1.1 Objective

The objective of this project is to simulate and observe specific test circuit.
Parameters in the test circuit are adjusted to observe their impact. Each transistor is
specified using MOSIS AMIS C5 (0.5 micron) T5AR technology. Test circuit is
constructed and simulated using software, CADENCE PSD v 15.0.

PART II
IDENTIFYING TEST CIRCUIT

2.1 Test Circuit

Cascode amplifier is shown on Figure 1.1 (Yan, n.d). In modern IC design, a

commonly used configuration for a single-stage amplifier is a cascode configuration.
This configuration consists of a common-source-connected transistor feeding in to a
common-gate-connected transistor (Johns, 1997). Two transistors in Figure 1 are NMOS.
Adding one NMOS transistor to this circuit should provide should enhance the output
voltage. This configuration is identified as the composite cascode amplifier (Figure 1.2.).
This composite cascode amplifier is incorporated as a test circuit for this project.

Figure 1.1 Basic cascode amplifier

The simulation purpose of this project is to investigate the output of both

amplifiers. An investigation will focus mostly on the composite cascode amplifier than
its predecessor. The results should provide the performance and limitation of this
particular circuit.
Figure 1.2. Composite Cascode Amplifier
 PART III
SIMULATION AND ASSESSMENT PLAN

3.1 Transistors technology

The technology incorporated for each transistor is MOSIS AMIS C5 (0.5 micron)
T5AR.

3.2 Schematics

Circuits in figure 1.1 and 1.2 are constructed using the software, CADENCE PSD
version 15.0. The schematics for cascode amplifier and Composite cascode amplifier are
provided respectively on Figure 3.1 and 3.2.

Figure 3.1. Schematics for basic cascode amplifier

 Figure 3.2. Schematics for composite cascode amplifier

3.3 Parameters

The parameters are in parameter boxes on both schematics. Parameters, VB and

Ix are retained at 0.5mV and 50uA respectively. Technology parameters are employed
from T5AR technology file.

3.4 Simulation procedures

The simulation parameters are applied to both configurations. They are initialized
as follow:

DC Sweep

Swept Var. Type: Voltage Source

Sweep Type: Linear
Name: Vin
Start Value: 0.0m
End Value: 2.0m
Increment: 0.2m

Parametric

Sweep Var. Type: Temperature

Sweep Type: Linear
Start Value: 24
End Value: 28
Increment: 1
 PART IV
FINDINGS

After performing a simulation on both circuits, the results are obtained and
analyzed.

4.1 Cascode configuration and Composite cascode configuration

In this part, only DC sweep is incorporated. The output voltage (Vout) traces are
provided on Figure 4.1 and 4.2. Their traces show similar linear behavior. The output
voltage linearly decreases as the input voltage increases. An opposite behavior can be
obtained by connecting the negative terminal of voltage source, Vin to transistor M3 gate.
This will provide positive slope output voltage.

Figure 4.1. Output voltage for basic cascode amplifier

 Figure 4.2. Output voltage for composite cascode amplifier

Table 4.1 provides values for Vin and Vout. They show that the output voltage
on the composite cascode amplifier is significantly larger than the cascode amplifier.
They prove that the composite cascode amplifier has higher voltage gain (Vout/Vin).

Table 4.1. Values for each configuration. Composite configuration (Left),

Basic configuration (Right)

The transconductance plot of each configuration is display on Figure 4.3 and 4.4.
The transconductance of the composite configuration has fluctuation. Figure 4.5
determines that the cause is at drain current of transistor M3 (The purple line).
 Figure 4.3. Transconductance for basic cascode amplifier

Figure 4.4: Transconductance for Composite cascode amplifier

 Figure 4.5: Drain Currents (ID) for composite cascode amplifier

4.2 Composite cascode amplifier characteristics

Parametric sweep on temperature exhibits the behavior of the composite cascode

amplifier at different temperature. According to Figure 4.6, the green line represents
lowest temperature, 24 Celsius. The pink line is 28 Celsuis, which is the highest
temperature. Output voltage decreases as temperature increases.

Figure 4.6. Output voltage of the composite configuration at different temperature.

(Green = 24, Red = 25, Violet = 26, Yellow = 27, Pink = 28)
4.3 Parameters variation

Parameters of the composite cascode amplifier are altered and simulated. They
exhibit different impact on the circuit behavior. Each of the following parameter is
altered through parametric sweep except VTH0. VTH0 is modified manually in the
model reference dialog box. The behavior of each alteration is summarized below:

Channel Length, Lx: It directly proportional to the output voltage. Convergence

error can occurred if this parameter reaches a specific point. The limit is dependent with
other parameters. Technology T5AR limits Lx to a certain point. The simulation was
aborted when Lx was initialized as 0.1 um.

Gate length, LDn: It has no significant impact on the output voltage. The gate
length was altered at 0.1 um, 0.4um, and 10 um. They revealed similar outcome.

Current source, Ix: The current source is directly proportional to the output
voltage. When adjusting parameter with this behavior, the convergence error should be
aware.

Threshold Voltage, VTH0: This technology parameter increases the output

voltage as it increases. The default T5AR technology value is 0.586875 V.

The plot and parametric sweep setup for each alteration is provided in appendix
A.
 PART V
CONCLUSIONS

The cascode amplifier configuration is popular in modern IC design. The basic

configurations consist of two transistors. Adding another transistor should enhance the
voltage gain. In this project, a NMOS transistor is added to the configuration. It results
as the composite cascode amplifier. Both configurations are constructed, investigated,
and simulated using software. The goals are showing their voltage gain and observing
several characteristics of the composite cascode amplifier.

The simulation results support points that the composite configuration has
significantly higher voltage gain than the basic configuration. This results in high output
voltage. Several parameters on the composite cascode amplifier have been modified.
Their variations have different effect on the outcome.

There was a convergence error during the simulation of the composite cascode
amplifier. It is recommended to adjust several parameters such as, Lx, Ix, and VB
properly to avoid convergence error. Technology T5AR has a specific limit for
parameter Lx. Those parameters mentioned in Part II has been adjusted for successful
simulation.
 REFERENCES

Yan, S., Lecture8, n.d.,

www.ece.utexas.edu/~slyan/archive/ee382m_spring04/notes/lecture8.pdf

Johns, D. A. and Martin K, Analog Integrated Circuit Design, Wiley Student Edition,
2005, John Wiley and Sons, Inc. Singapore
 APPENDIX A
PARAMETERS ALTERATIONS

Each parameter has identical setup on:

Sweep Var. Type: Global parameter

Sweep Type: Linear

Their Name, Start Value, End Value, and Increment are different.
VTH0 has to be adjusted manually in the transistor model reference dialog box.
Please refer to part IV for summary of each alteration.

A1. Channel Length, Lx

Parametric setup:
Name: Lx, Start Value: 0.5u, End Value: 0.8u, Increment: 0.1u

Figure A1: Lx alteration

(Green = 0.5um, Red = 0.6 um, Violet = 0.7 um, Yellow = 0.8um)
A2. Gate Length, LDn

Parametric setup:
Name: LDn, Start Value: 0.5u, End Value: 1.5u, Increment: 0.5u

Figure A2. LDn alteration (Green = 0.5 um, Red = 1.0 um, Violet = 1.5 um)

A3. Current source, Ix

Parametric setup:
Name: Ix, Start Value: 0.5u, End Value: 1.5u, Increment: 0.5u

Figure A3. Ix alteration (Green = 0.5 uA, Red = 1.0 uA, Violet = 1.5 uA)
A4. Threshold Voltage, VTH0

Perform only DC sweep for this alteration.

VTH0 = 1.0 V

Figure A3. VTH0 alteration

Table A1. VTH0 alteration results