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Unit 7-Vhdl: 1. VLSI Design Flow

This document provides an overview of VHDL (VHSIC Hardware Description Language). It discusses the VLSI design flow, including behavioral, structural, and physical design descriptions. It also covers finite state machines and using HDLs like VHDL and Verilog to implement digital circuit designs. The document outlines different VHDL modeling styles such as structural, data-flow, behavioral, and mixed modeling. Finally, it discusses VHDL data types and objects like signals, constants, and variables.

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Jake Roosenbloom
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312 views4 pages

Unit 7-Vhdl: 1. VLSI Design Flow

This document provides an overview of VHDL (VHSIC Hardware Description Language). It discusses the VLSI design flow, including behavioral, structural, and physical design descriptions. It also covers finite state machines and using HDLs like VHDL and Verilog to implement digital circuit designs. The document outlines different VHDL modeling styles such as structural, data-flow, behavioral, and mixed modeling. Finally, it discusses VHDL data types and objects like signals, constants, and variables.

Uploaded by

Jake Roosenbloom
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Unit 7-

VHDL
by Harsha

1. VLSI Design
Flow
• Very Large-Scale
Integration (VLSI) is
the current level of
computer microchip
miniaturisation and
refers to microchips
containing hundreds
of thousands of
transistors.

• It uses three domains


of design
description:

• Behavioural -
Description of
function of
design. Most
abstract.

• Structural -
Specifies
architecture.

• Physical -
Description of
physical
implementation
of design

—Design Entry
Entering the design into a design System using a Hardware Description Language
(HDL)

—Schematic
Look at both the pics yo

OMIT

2. FSM & HDL


• Sequential logic systems (not combinational ones) are finite state machines
(FSMs)

• As FSMs, they consist of a set of states, some inputs, some outputs, and a set
of rules for moving from state to state.

• In Digital Systems Design, we begin by defining how the system works with an
FSM Model.

• Once the FSM is fully designed, it is easy to write out the design in a hardware
description language (HDL) such as Verilog or VHDL for implementation on a
digital IC (integrated circuit).

READ FROM THESE LINKS FOR MORE—

https://www.allaboutcircuits.com/technical-articles/implementing-a-finite-state-
machine-in-vhdl/

https://www.xilinx.com/support/documentation/university/Vivado-Teaching/HDL-
Design/2015x/VHDL/docs-pdf/lab10.pdf

3. Different modelling styles in VHDL


Modelling style describes the way we design digital IC’s.

Types of modelling styles are—

1. Structural Modelling
• It shows how the data / signal flows though the components from input
to output.

• “As a structure”

2. Data-flow Modelling
• It shows how the data / signal flows though the components from input
to output. It works on Concurrent Execution.

3. Behavioural Modelling
• It shows how the system performs according to current input values.

• We define what value we get at the output corresponding to the input


values.

• Describes behaviour of an entity as a set of statements that are


executed sequentially in that specific order.

4. Mixed Modelling
• Take a guess.

4. Data Types and Objects


Objects — are things that hold values

• Have a class and type


• May have an initial declaration value

• class Identifier: Type := InitialValue;


• A VHDL object consists of one of the objects

1. Signal
• Used to connect entities together to form models.

• Signals must be scheduled to occur (kinda like during run-


time)

• SIGNAL sign_name : sign_type [:=


initial_value];

2. Constant
• Names assigned to specific values of a type.

• Gives ability to have a better documented model.

• Eg: CONSTANT PI: REAL := 3.1415;


3. Variables
• Used for local storage in process statements &
subprograms.

• Assignments occur immediately, as opposed to signals


where assignments occur in the future, so they are more
efficient, and take less memory.

• Eg: VARIABLE var_name: var_type[:= value];

Types — determine the legal


values for an object

(Note: Lookup the syntax of the


types just in case)

Scalar Type- Describe objects


that can hold, at most, one
value at a time.

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