There are two available modes of operation for 8086.
1. Minimum mode of Operation
2. Maximum Mode of Operation
Minimum mode is obtained by connecting the mode selection MN/MX’ to +5V. Maximum
mode is obtained by connecting MN/MX’ to ground.
1. Minimum Mode of Operation
In minimum mode of operation, 8086 provides all control signals needed to
implement the memory and I/O interfacing.
For minimum mode 8288 bus controller is not required
The minimum mode signals can be divided into the following basic groups:
a) Address/Data Bus
b) Status Signals
c) Control Signals
d) Interrupt and DMA Signals
a) Address/ Data Bus
Serves two functions
20 bit address bus (A0-A19)
16 bit data lines (D0-D15) multiplexed with address lines (A0-A15) carries address during
first clock cycle then carries data
b) Status Signals
4 most significant address lines (A16-A19) are multiplexed with status signals (S3-S6)
Bit S3 and S4 are used to specify 8086 internal segment registers.
S4 S3 Segment Register
0 0 Extra
0 1 Stack
1 0 Code
1 1 Data
Bit S5 is the logic level of the internal enable flag
Bit S6 is always at logic ‘0’ level.
c) Control Signals
The following are the control signals associated with 8086 minimum mode
ALE (Address Latch Enable): latch address and data
BHE’/S7: (Bus High Enable): must be made low for read or write operation and it acts as
status signal S7
M/IO’ (Memory/IO’): IO operation if M/IO’=0 and Memory operation if M/IO’=1
DT/R’ (Data Transmit/Receive): Data Transmitting if DT/R’=1
Data Receiving if DT/R’=0
RD’(Read): indicates read bus cycle when RD’=0
WR’(Write): indicates write bus cycle when WR’=0
DEN’(Data Enable): tells the external device when to put data
READY: used to insert wait states into the bus
d) Interrupt and DMA Signals
The key interrupt signals are INTR (Interrupt Request) and INTA’ (Interrupt
Acknowledge)
The DMA interface of the 8086 minimum mode consists of HOLD and
HLDA signals
Minimum Mode Timing Diagrams
a) Read Cycle Timing Diagram for Minimum Mode (Input)
b) Write Cycle Timing Diagram for Minimum Mode (Output)
2. Maximum Mode
In maximum mode, the 8086 is operated by connecting the MN/MX’ pin to ground
In this mode, the processor derives the status signals S2, S1, S0. Another chip called
Bus Controller derives the control signals using these status signals.
In maximum mode, there may be more than one microprocessors (co-
processors) in the system configuration.
The Bus Controller receives the three status signals S2, S1, S0 from 8086 and
generates the signals that are needed to control the memory, IO and Interrupt
Interfaces.
̅̅̅̅̅̅̅ is used to issue interrupt acknowledge pulses to the interrupt controller or to the
interrupting device
̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅ (IO write Command) enable an IO interface to read or
̅̅̅̅̅̅̅ (IO Read Command),
write data from or to the address port
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅
Memory Read Command), ̅̅̅̅̅̅̅ (Memory Write Command) are used to read from or
write into memory locations
For both IO and memory write command signals, the advance signals namely
(Advance IO Write Command) and (Advance Memory Write Command) are
available
Maximum Mode Timing Diagrams
a) Read Cycle Timing Diagram
b) Write Cycle Timing Diagram
