Dual Damascene

Related terms:

Dielectrics, Plasma, Damascene Process, Barrier Layer, Metallizations, Seed Layer

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Learn more about Dual Damascene

Aqueous Cleaning and Surface Condi-

tioning Processes
Glenn W. Gale, ... Karen A. Reinhardt, in Handbook of Silicon Wafer Cleaning
Technology (Second Edition), 2008

4.6.2.1 Copper dual damascene interconnects

Copper dual damascene wiring, with lower resistivity than Al, is now fully main-
stream and will remain the interconnect metal for foreseeable technology nodes.
One method for controlling the cleaning process with the Cu dual damascene
devices is to move from wet benches to spray tools or single-wafer cleaning systems.
Single-wafer cleaning has been gaining acceptance in the back end of the line
process especially for 300 mm wafers at nodes less than 130 nm. Batch processing
in wet benches with the traditional and semi-aqueous F chemistries can be difficult
because of the possible attack of the metal during post-metal cleaning. Rinsing
efficiency in batch immersion processing is limited by diffusion, such that the
residence time of F at the wafer surface is difficult to control in comparison with
faster rinsing single-wafer spin processes. Thus, corrosion can be more difficult to
avoid in batch immersion systems.

The challenge for any new chemical formulation for <130-nm technology is to be
able to affectively clean structures in a very short period and to be quickly quenched
when the cleaning process is complete. Many IC cleaning recipes for single-wafer
spin spray tools call for a maximum of 2 minutes cleaning cycles, including the H2O
rinse and drying steps. This is one of the reasons that aggressive formulations have
been developed for the single-wafer technology, to enable fast process times and
high throughputs with excellent cleaning results.

> Read full chapter

Process Technology for Copper Inter-

connects
Jeffrey Gambino, in Handbook of Thin Film Deposition (Third Edition), 2012

8.3.5 Chemical Mechanical Polishing

CMP is used to pattern the Cu and barrier layer after metallization of the dual
damascene structure. The wafers are placed face-down on a rotating pad on which
the slurry is dispensed. Copper CMP typically requires at least two steps [16,102].
The first step is Cu removal, stopping on the barrier layer, and the second step is the
barrier removal, stopping on the dielectric. Overpolishing is required to ensure that
all metals are removed from the field regions in all parts of the wafer. During the
overpolish, there will be thinning of the Cu in regions with high Cu pattern density.
This thinning results in variations in wire resistance. To minimize the variation
in wire resistance caused by differences in local pattern density, design rules are
required which restrict the local Cu pattern density [20]. In addition, low downforce
processes are required to minimize Cu erosion during the overpolish step [103].

There are a number of problems with Cu CMP in a porous low-k structure, including
Cu dishing and insulator erosion, cracking and adhesion loss in the dielectric
stack, and scratching or contamination of the low-k material by components or the
slurry or reaction by-products [104–108]. The problems with dishing/erosion and
cracking/adhesion loss can be minimized by reducing the downforce during CMP
and improving the adhesion between layers in the stack [104]. There are two basic
integration schemes for Cu CMP with porous low-k structures: the permanent polish
stop method (Figure 8.16A–C) [104,105,109] and the direct CMP method (Figure
8.16D–F) [109]. In the permanent polish stop approach, a relatively dense material,
such as SiO2 [104] or nonporous SiCOH [105,109], is used on top of the porous
low-k material. The advantage of this approach is that the porous low-k material is
protected from CMP-related scratches and contamination. The disadvantage is that
the effective dielectric constant of the stack increases. Hence, there is much research
on minimizing damage and contamination when the polish stops directly on the
porous low-k dielectric [106,109–111].
Figure 8.16. Schematic of CMP options. (A–C) Polish stop method: (A) Cu plating,
(B) Cu CMP, and (C) barrier CMP. (D–F) Direct CMP method: (D) Cu plating, (E) Cu
CMP, and (F) barrier CMP [109].

For direct CMP on the low-k dielectric, the first requirement is a low removal rate for
the porous low-k material during the polish. Organic compounds such as surfactants
are used to lower the polish rate of the low-k material with respect to the metal
layer [109–112]. The surfactants selectivity segregate to the surface of the SiCOH
and thereby reduce the polish rate with respect to the metals [112]. However, it is
often observed that the presence of surfactants in the slurry increases the dielectric
constant of the porous SiCOH [109,110]. Additional –CH2 and C–H bonds are
observed in the bulk of the porous SiCOH after exposure to surfactants in the slurry,
which are responsible for the increase in dielectric constant [110]. Significant
diffusion of both linear and branched surfactants into porous low-k materials has
been observed at room temperature, consistent with this model [111]. There are a
number of approaches to minimize the change in dielectric constant. One approach
is to optimize the slurry to prevent residues from forming in the pores [109,110].
Another approach is to do a post-CMP anneal at 350°C to restore the dielectric
constant [109,110]. A third approach is to use a bilayer porous SiCOH film, with the
near surface region (that is exposed to CMP) having a lower porosity than the bulk
of the film [28].

> Read full chapter

Mass Transport-Induced Failure

Milton Ohring, Lucian Kasprzak, in Reliability and Failure of Electronic Materials and
Devices (Second Edition), 2015

5.8.1 Introduction
A need to reduce signal delay in ICs has resulted in the selection of copper as a
replacement for Al/Cu. Dual damascene is the new technique used to form inter-
connect structures based on conductive copper metal lines inlaid into an oxide or
low dielectric constant (k) nonconductive layer. The dual damascene technique forms
trenches and vias (hence dual or twice used) into which copper is eventually electro-
plated. CMP is used to remove excess metal from the wafer surface. The process
has been adopted for forming copper interconnects because traditional plasma etch
techniques cannot be used for patterning copper films. Copper/low k interconnects
formed by the dual damascene technique are ubiquitous in state-of-the-art manu-
facture of IC devices.

> Read full chapter

Post-CMP Cleaning
Manish Keswani, Zhenxing Han, in Developments in Surface Contamination and
Cleaning, 2015

5.3 Copper Post-CMP Cleaning

Copper is the material of choice for interconnects in today’s IC manufacturing
due to its lower resistivity and higher resistance to electromigration compared to
aluminum. Copper interconnects are formed using a dual damascene process at the
end of which CMP is used to remove excess copper and Ta/TaN adhesion/barrier
layer. Colloidal silica, the most commonly used abrasive in copper CMP slurry,
chemisorbs onto the copper oxide (Cu2O or CuO) and copper hydroxide (Cu(OH)2)
formed through oxidation of copper by hydrogen peroxide in the slurry [62]. Chen
et al. developed a cleaning method for the removal of colloidal silica abrasive from
polished copper surface using a two-step process [62]. The first step involved a buf-
fing step employing dilute HNO3/benzotriazole (BTA) aqueous solution that causes
etching of the copper oxide and releases the attached silica particles by breaking the
chemical bond between silica and the copper oxide. Figure 4.23 illustrates bridging
of silica abrasive to copper hydroxide by means of oxygen and removal of the particle
using the buffing step. The copper surface is passivated with BTA at the end of this
step. The optimum concentrations and buffing time that yielded lowest dishing of
~ 5 nm were identified to be 3 vol.% HNO3 and 5 mM BTA and 10 s, respectively.
In order to prevent redeposition of silica abrasive on a hydrophobic Cu-BTA surface,
a second PVA brush scrubbing step using a nonionic surfactant, Triton X-100, was
shown to be critical. It was hypothesized that adsorption of surfactant molecules at
critical micelle concentration level renders the Cu-BTA surface hydrophilic, which in
conjunction with PVA brush scrubbing cleans any residual colloidal silica as well as
prevents its redeposition by steric barrier mechanism.

Figure 4.23. Schematic representation of bridging of colloidal silica abrasive to

copper hydroxide and the removal of particle using an aqueous solution of HNO3
and BTA.

Reprinted from Ref. [62].

Hong et al. determined the role of additives such as BTA and pH adjusters (am-
monium hydroxide and TMAH) on adhesion and removal of silica particles to/from
copper films in citric acid-based post-copper CMP cleaning solutions [63]. The zeta
potential of both silica particles (30 nm) and copper increased in magnitude with
addition of citric acid in 1 mM KCl solutions. The adsorption of citrates on these
surfaces was explained as the reason for higher surface charge and the resulting high
zeta potential. Adhesion studies were in line with zeta potential measurements and
showed a decrease in the adhesion force between silica particles and copper with
increasing citric acid concentration due to higher electrostatic repulsion between
the surfaces.

The authors also calculated the theoretical total interaction force using the DLVO
theory between silica particle and copper surface as a function of separation distance
in various cleaning formulations. Their results, shown in Fig. 4.24, indicated that the
strongest attractive force was obtained in the BTA and citric acid solution containing
TMAH, while the weakest attractive interaction was calculated for the same solution
but with TMAH replaced by NH4OH. The adhesion force was also measured exper-
imentally in these cleaning solutions and compared to that in DI water (Fig. 4.24).
The smallest adhesion of 0.0124 nN was measured in citric acid solutions with pH
adjusted to 6.0 using ammonium hydroxide, while largest adhesion force of 8.87 nN
was measured in TMAH containing citric acid solutions of pH 6.0. The much higher
adhesion in TMAH solutions was attributed to the adsorption of TMA ions on silica
and copper causing these surfaces to exhibit lower zeta potential values as measured
experimentally. The highest particle removal efficiency was measured for cleaning
solutions that yielded lowest adhesion force, thereby highlighting the importance of
pH adjuster in cleaning formulations.

Figure 4.24. (a) Calculated interaction force between silica particles and copper
surface using DLVO theory in various cleaning formulations, (b) adhesion forces
between silica particles and copper surface in post-CMP Cu cleaning chemistries.

Reprinted from Ref. [63].

Venkatesh et al. conducted polarization studies on copper treated with BTA for 1 min
and subsequently with solutions containing TMAH only, TMAH with arginine (1%)
and TMAH with arginine (1%) and uric acid (0.01 M) [64]. The role of TMAH was that
of cleaning agent; arginine, a chelating agent for copper and uric acid, was proposed
as replacement for BTA to inhibit copper corrosion. The importance of achieving a
balance in the cleaning chemistry was highlighted so that minimal or no etching
of copper occurs and any etched copper is complexed to prevent its redeposition.
Figure 4.25 shows the corrosion current density estimated from the polarization
curves for various cleaning formulations. The current density was lowest for DI water
as no BTA was removed in this case. TMAH alone was identified as the most favorable
formulation for not only effectively removing BTA but also providing lowest copper
corrosion. Uric acid was not found to offer any additional benefit in reducing copper
corrosion rate.

Figure 4.25. Corrosion current density of Cu in various solutions.

Reprinted from [64].

Particle contamination and cleaning studies were performed by dipping copper

samples in a slurry containing 12.5 wt.% silica abrasive of size 100 nm and treating
the samples in various solutions. The field emission scanning electron microscopy
(FE-SEM) images of fresh copper sample, copper sample treated with DI water,
and solution of TMAH, arginine, and uric acid are shown in Fig. 4.26a through c,
respectively. It is clear from these images that the treatment of DI water results in a
significant number of particles remaining on the surface. In the case of TMAH/argi-
nine/uric acid treated copper sample, it appears very clean and the particles appear to
be completely removed. The effectiveness of TMAH formulation in achieving good
cleaning was attributed to the high pH of the solution causing the surface charge of
the particle and substrate to be negative and the interactive forces to be repulsive. It
was proposed that TMAH removed BTA film, facilitated the wetting of the surface (to
make it hydrophobic), and enabled slight etching of the copper required for particle
removal. Arginine complexed the etched copper ions and aided in preventing their
redeposition.

Figure 4.26. FE-SEM micrographs of various Cu samples (a) fresh Cu, (b) dipped
in silica slurry and treated with water, (c) dipped in silica slurry and treated with
solutions containing 0.5 wt.% TMAH, 1 wt.% arginine, and 0.01 M uric acid.

Reprinted from Ref. [64].

> Read full chapter

Megasonic Cleaning
R. Nagarajan, ... K.R. Gopi, in Developments in Surface Contamination and Clean-
ing: Methods for Removal of Particle Contaminants, 2011

6 Industry Case Studies

Chang et al. [41] have discussed the use of 0.8–1 MHz frequency acoustic waves to
enhance cleaning efficiency for post-etch polymer removal in the Cu-low-k dual
damascene process. They demonstrated effective usage of megasonic cleaning with-
out structural damage (though the average Cu root mean square (RMS) roughness,
measured by an atomic force microscope (AFM), did increase from 8.5 nm to 9.5 nm
at maximum input power), and yields >90%. Processing time was greatly reduced
with the megasonic enhancement.

Keswani et al. [42] have investigated the feasibility of removal of particles from
silicon wafers in electrolyte solutions of different ionic strengths irradiated with
megasonic waves, using KCl as model electrolyte and silica as model particles. They
have measured the effect of ionic strength on acoustic pressure in solutions using
a hydrophone, and found that sound wave pressure amplitude can be increased
in electrolyte solutions of ionic strength greater than 0.01 M. The key result from
this work was that the removal of particles can be achieved at lower acoustic power
densities through the use of simple electrolyte solutions.

Kim et al. [43] have developed a megasonic system for nano-pattern cleaning that
does not cause damage. An L-type (named for the shape) waveguide made from
quartz was found to give best cleaning results. The maximum values and standard
deviations of acoustic pressure were decreased by 17% and 14%, respectively. They
conclude, therefore, that the L-type would have higher particle removal efficiency
and would be less likely to cause pattern damage.

Huang et al. [44] have compared various cleaning processes used to remove
post-CMP (chemical mechanical polishing) residue in hard disk substrate manu-
facturing. The results are summarized in Figure 2.31. Megasonic cleaning is clearly
superior to ultrasonics and scrubbing in defect reduction. This is reinforced for
various particle types in Figure 2.32. The authors conclude that brush scrubbing can
remove 99% of the contamination, but megasonics is needed to remove sub-μm
particles.

FIGURE 2.31. Defect number after various cleaning processes [36]

FIGURE 2.32. Particle residue by type after various cleaning processes [36]

> Read full chapter

Back-end Process Simulation

F.H. Baumann, P.L. O’Sullivan, in Encyclopedia of Materials: Science and Technol-
ogy, 2001

5 Applications
Figure 9 shows a 3D simulation of sputter deposition into an L-shaped test feature
using a level set code. 3D simulations are necessary in many cases to realistically
determine the processing windows for sputter deposition of barrier and seed layers
in copper interconnect structures. In the dual-damascene approach used for copper
metalization, the contact hole and the trench for the line are first etched into the
dielectric. After sputter deposition of barrier and seed layer, the via and the line are
formed in a single step using electroplating. Both, the barrier layer, which prevents
out-diffusion of copper, as well as the copper seed layer need to be continuous
and void free to ensure a reliable and functioning interconnect. The integrity of the
sputtered film has to be maintained for every site on the wafer. Due to the loss of
symmetry, this necessitates 3D simulations.
Figure 9. Different views of L-shaped, 0.8 μm deep test feature after sputter depo-
sition of a 0.4 μm thick film. The simulation was performed using a full 3D level set
code.

Figure 10 shows how process simulation can be used to inspect for processing
nonuniformities on the reactor scale level. While the process shows symmetric
side-wall coverage for a via located in the center of a wafer, severe encroachment is
observed at the bottom of the side-wall for vias positioned at the edge of the wafer.

Figure 10. Use of process simulation to reveal weak spots in the process before an
actual experiment is performed. The cylindrical via is placed at the corner of the wafer
(a). Clearly, the top coverage is asymmetric (b), since parts of the via are exposed
to more target area than others. A cut through the lower part of the side wall (c)
reveal two weak spots in the deposited film. The lower side wall coverage at location
A stems from the fact that less target is seen from here. Unexpectedly, a second thin
spot occurs at the opposite side, location B. Thinning at this spot occurs from the
development of an overhang due to increased top coverage of the right hand side
at the via entrance, see (b).

Simulations like these enable the process engineer to spot potential trouble spots in
advance (before processing a single wafer) and thus expedite the development of a
new process.
> Read full chapter

Applications of chemical mechanical

planarization (CMP) to More than
Moore devices
G. Zwicker, in Advances in Chemical Mechanical Planarization (CMP), 2016

18.2 CMP for “More than Moore” devices

Chemical mechanical polishing/planarization (CMP) was developed in the late 1980s
in order to overcome problems with multi-layer metallization. The increasing topog-
raphy as a result of stacked metal lines led to depth-of-focus problems during pho-
tolithography and to reliability problems caused by metal line thinning. The effective
planarization by CMP of the inter-level dielectric layers allowed the fabrication of
more than three metal layers. Without CMP, modern logic devices with up to 12
metal layers could not be realized. Thus, CMP is one of the enabling technologies
of today's ubiquitous electronics.

Over the years, the development of various CMP processes for “More Moore”
simplified device processing and allowed, for example, the realization of copper
metallization by introducing damascene and dual-damascene technology. In to-
day's sub-14 nm logic device fabrication, the number of CMP steps required in
front-end-of-line and back-end-of-line integration reaches up to 18–20 (Moon
et al., 2014). For example, the introduction of finFET technology with replacement
metal gates (RMG) leads to the tasks of mastering the critical CMP steps shown in
Table 18.1 after Moon et al. (2014).

Table 18.1. Critical CMP steps of state-of-the-art logic devices

CMP steps Challenges

finFET STI CMP Oxide CMP, highly selective to SiN, minimum
dishing
finFET poly-Si CMP Poly-Si CMP, good planarization efficiency,
highly uniform, advanced endpoint control
finFET RMG poly open CMP (POC) Oxide CMP, two-step process: (1) bulk removal,
(2) stop on SiN, extremely highly selective to SiN
(minimum nitride loss)
finFET RMG W gate CMP W CMP, extremely highly selective to oxide (de-
termines the final gate height)
finFET self-aligned contact (SAC) SiN cap CMP SiN CMP, highly selective to oxide (minimum ox-
ide loss)
Contact W CMP W CMP, extremely highly selective to oxide for
minimum topography, prevents galvanic corro-
sion in W
In order to overcome the identified challenges, advanced slurries, pads and cleaning
chemistries have been developed by the consumables manufacturers.

Only a few years after the introduction of CMP for the fabrication of “More Moore”
devices, the first MEMS devices were demonstrated by Sandia labs, which employed
polishing for poly-Si layer planarization (Sniegowski, 1996). Later, CMP was adopted
for the fabrication of many “More than Moore” devices.

In most cases, the process engineers had to use the standard slurries and pads of
“More Moore” developments. That was true until recently, when the consumables
suppliers discovered the potential of the enormously growing MEMS market. Today,
slurries optimized for MEMS processes are available. Slurry companies had to react
on the demands of the integrated device manufacturers and foundries and learned
to formulate tunable polishing slurries. By using sophisticated additives, slurries
fulfilling the requirements for power device fabrication and MEMS manufacturing
have been developed.

With the exception of a few analogue IC and power device manufacturers using
300 mm wafer technology, all analogue and RF ICs, MEMS and MOEMS devices,
mainstream power MOS and biochips are produced on smaller wafer sizes between
100 and 200 mm. In many cases, legacy tools, that is, refurbished “More Moore”
CMP equipment, are used in the manufacturing lines.

> Read full chapter

Sputter Processing
Andrew H. Simon, in Handbook of Thin Film Deposition (Third Edition), 2012

4.6.4 Multistep Sputtering Sequences

Modern semiconductor-manufacturing sputter-process sequences are able to ex-
ploit several of the developments discussed in the previous sections in combination
in order to engineer specific layer thicknesses, feature coverage, and interface prop-
erties. We previously covered in Section 4.6.2 how clustered chambers on a common
vacuum enable the sequential deposition of different materials without breaking
the vacuum. Particularly with respect to copper-interconnect wiring applications,
multiple processing steps within the same chamber have become a standard means
of satisfying demanding specifications for reliability and performance. To illustrate
these developments, we will briefly examine some representative examples.

One basic example of a multistep sputter-deposition sequence involves a

three-chamber process in which a copper-interconnect feature is cleaned and de-
posited with barrier and seed layers. Whereas tooling and process details have
changed, the schematic sequence of the process steps have been the same over
several technology nodes going back more than a decade [40,41]. The incoming
structure is depicted in Figure 4.12A and typically consists of dual-damascene via
and trench features. When filled with metal, the trenches will enable intralevel signal
transmission, while the vias span the full height of the layer and provide electrical
contact to the wiring levels directly above and below.

Figure 4.12. Schematic representation of a clustered deposition sequence used in

copper interconnects: (A) incoming line/via structure, postetching; (B) Ar+ sputter
preclean; (C) TaN (black line) and Ta (patterned line) deposition; (D) final structure
after Cu seed layer deposition, Cu electroplating, and polishing [34].

Upon entering the high-vacuum environment, the wafer is first subjected to a

desorption step in the degas chamber. The degas step will usually be in an inert
ambient such as argon and will be done at a temperature significantly higher (by
~50–100°C) than the other steps in the sequence to ensure that no desorption occurs
during subsequent deposition or cleaning steps.

The deposition and etch steps for the sequence are illustrated schematically in Figure
4.12B–D. Following the degas step, the exposed metal at the bottom of the via is
cleaned of native oxide. One traditional method for metals precleaning has been to
sputter etch with Ar+ plasma in a dedicated sputter-etch chamber. As was mentioned
previously, for copper interconnects, it is now common to use reactive hydrogen
plasma cleans prior to barrier deposition [19,20] with the object being to reduce
the native copper oxide at the via bottom and expose a clean copper surface for
contact to the following wiring level. The use of reactive hydrogen cleans in lieu of
argon sputtering also eliminates the dimensional feature enlargement and physical
bombardment damage to the dielectric layer, which are common side effects of
sputter etching done at high pedestal biases.

As with most conductive materials used in ICs, copper interconnects require a liner
layer between the dielectric and the conductive metal. The liner layer in copper
interconnects needs to serve multiple purposes: (1) it provides adhesion between
the metal wire and the surrounding dielectric; (2) it prevents diffusion of copper
into the dielectric and corrosion of the copper by ingress of oxidizing species; (3) it
can provide current redundancy during electromigration voiding, thereby providing
advance warning of circuit failure.

An optimal barrier/liner layer for copper interconnects, which satisfies all three of
these requirements, is a sputter-deposited bilayer of TaN followed by Ta [15,16,42].
The deposition of this bilayer is accomplished by two sequential process steps in the
Ta(N) deposition chamber, with the TaN being deposited by reactive sputtering in
a sputter-gas atmosphere of argon and nitrogen, and the Ta layer typically being
deposited at the same magnetron power as the TaN layer, but in an argon-only
ambient with the nitrogen flow shut off. The TaN/Ta bilayer is thus a combination of
reactive sputtering for the initial layer and conventional magnetron sputtering for
the second, pure Ta layer. The TaN initial layer facilitates the growth of the low-re-
sistivity alpha-phase tantalum in the overlayer, which provides for current-strapping
redundancy in case of electromigration failure.

The final step in the sputter-deposition sequence is the deposition of a conformal

layer of copper, which will serve as a seed layer for subsequent electroplating of
copper to fill the features. As was described previously, most modern Cu sputter
sources will use some form of self-sustained sputtering [37,38] in order to achieve
high ionization, directionality, and conformality in high aspect-ratio dual-dama-
scene structures.

An alternate sequence for cleaning and depositing a copper barrier/liner and seed
layer stack involves depositing the TaN barrier-first, then sputter etching through
the TaN at the via bottom [28–34]. The schematic process flow is shown in Figure
4.13A–D. The initial deposition of the TaN barrier (Figure 4.13A) is followed by an
argon sputter etch (Figure 4.13B). As was discussed previously, the argon sputter
plasma can be created in situ in the deposition chamber using the biasable wafer
pedestal and some means of ionizing the argon sputter gas, such as inductive coils
or shaped magnetrons, depending on the source design. The argon sputter etch is
long enough to fully etch through the TaN layer at the via bottom and partway into
the copper wire structure in the interconnect layer immediately below.
Figure 4.13. Schematic representation of a multistep barrier deposition-etch se-
quence used in a “barrier-first”/“punch-through” copper-interconnect scheme to
increase via contact area: (A) TaN (black line) deposition on the line/via structure; (B)
Ar+ sputter etch to create an anchoring gouge for the via in the wiring layer below;
(C) Ta (patterned line) deposition; (D) final structure after Cu seed layer deposition,
Cu electroplating, and polishing [34].

The result is a gouged-via bottom, as shown in Figure 4.13B. As with the flat-bo-
ttomed structure in Figure 4.11, the argon sputter etch is followed by a pure Ta de-
position (Figure 4.13C), followed by Cu seed layer deposition in a separate chamber.
In Ta(N) chambers with in situ argon etch capability, the TaN/Etch/Ta sequence can
be performed as one multistep recipe.

The gouged-via structure depicted in Figure 4.13A–D (also referred to as

“punch-through” or “barrier-first”) [31,33,34] has a number of advantages over
the flat-bottomed structure in Figure 4.11. The gouging of the via into the layer
below enlarges the effective contact area since the geometrical area of the gouged
interface is larger than in the case of the flat via bottom. The four-point bend test
for the structures in question indicates a 30% improvement in the physical yield
strength with the gouged-via structure [34]. The sputter etching through the TaN
layer means that the layer structure at the via-bottom interface is Cu/Ta/Cu instead
of Cu/Ta/TaN/Cu, resulting in a lower contact resistance due to the absence of the
most resistive layer in the structure, the TaN layer.
The effect of the two different fabrication sequences is illustrated by the via-re-
sistance data shown in Figure 4.14, which depicts the (normalized) via resistance
for gouged and nongouged splits fabricated in dual-damascene structures with
~130 nm linewidths [34]. Relative to the gouged-via splits, the nongouged-via splits
show >50% higher median via resistances at-level, with resistance distributions that
are 3–4× wider. As the second metal-level via structures are subjected to the thermal
stresses of a subsequent level build (M3), the resistances for the flat-bottom via
wafers are seen to shift upward until they are ~25% higher at wafer final test. In
contrast, the gouged-via wafers maintain their narrower distributions throughout
the multilevel wiring build and show negligible resistance shift between second
metal level and wafer final test.

Figure 4.14. Contact resistance for control (Figure 4.12) versus barrier-first
deposition (Figure 4.13) sequences: wafers 1–4—control via structure; wafers
5–8—gouged-via structure. The resistance shifts between the second metal level
(M2) and the subsequent levels are lower for the gouged structure [34].

The gouged-via structure exhibits advantages in reliability performance as well [34].

Electromigration data comparing the structures depicted in Figures 4.12 and 4.13
are shown in Figure 4.15 for line-depletion electromigration testing. The non-
gouged-via structures show a distribution of failure lifetimes that are both shorter
and more than an order of magnitude wider. The wider failure distribution on the
flat-bottom structures is indicative of a bimodal failure distribution, with an early
failure component of approximately 25%. Similar results have been reported by
other authors [31,33].
Figure 4.15. Electromigration performance for control (Figure 4.12) versus barri-
er-first deposition (Figure 4.13) sequences: wafer 1—control via structure; wafers 2
and 3—gouged-via structure. The failure distributions for the gouged-via structure
are seen to be longer-lived and narrower [34].

It should be noted that temperature control during the via etch is essential for
good interface quality. Immediate re-oxidation of primary conductors such as copper
and aluminum has been observed when argon sputter-etch temperature is not
controlled, resulting in elevated contact resistance and oxidized interfaces [72].

> Read full chapter

Nanoimprint lithography (NIL) and re-

lated techniques for electronics applica-
tions
I. Tiginyanu, ... V. Popa, in Nanocoatings and Ultra-Thin Films, 2011

10.8 NIL for three-dimensional (3D) patterning

3D structuring requires control of both lateral and vertical dimensions of the com-
ponents. Photolithography can only generate one-dimensional (1D) or two-dimen-
sional (2D) patterns. The fabrication of 3D structures usually requires more than one
processing step and relies on a layer-by-layer fabrication with accurate alignment
between the layers. However, the production cost exponentially increases with the
number of layers, and defects accumulate as the number of layers increases. The
fabrication of 3D structures by photolithography remains still a great challenge.
NIL provides an alternative approach to attaining this goal. We will shortly describe
some other approaches for 3D structuring before the overview of the NIL. While
conventional photolithography requires the use of binary masks for multiple expo-
sures with alignment between steps, photolithography with grayscale masks yields
3D structures in a single exposure. In this version of photolithography, the mask
encodes the final shape of a structure in the form of an optical density contour map
that determines the illumination intensity during the exposure of a resist or another
sensitive material (Geissler and Xia, 2004).

Holographic patterning which relies on the interference between intersecting laser

beams is another approach for 3D structuring. Complex patterns can be produced by
intersecting more than two laser beams or by using multiple sequential exposures.
3D periodic lattices are generated when four coherent laser beams are focused onto
the same spot, and the exposed regions are removed by selective dissolution. This
technique is suitable for the fabrication of 3D photonic crystals. Writing with focused
laser or electron beams can also be used for obtaining 3D structures through the
transformation of a 2D pattern into a 3D structure by varying the exposure dose
during scanning. The add-on and layer-by-layer fabrication of 3D structures is based
on the creation of a 2D pattern first, which serves as a template for subsequent
deposition steps. The repetition of patterning and deposition layer-by-layer results
in the production of 3D structures with desired shape. This approach has been
demonstrated for contact printing with elastomeric stamps, and for IJP and robotic
deposition in conjunction with different types of ink formulations that include col-
loidal fluids and suspensions, ceramic powders, or polymer-based binder solutions
imprinted into compact payers of ceramic powder (Geissler and Xia, 2004 and
references therein).

There is a strong need for 3D nanoscale patterning technology for various optical
devices and dual damascene processes in the next generation. A breakthrough in
this field has been made by NIL because of its low cost and process simplicity.
Layer-by-layer techniques have also been developed based on NIL and polymer
bonding. For successful multilayer fabrication, it is very important to control the
adhesion between the two polymer layers and between mold and polymer. Two
techniques, bonding with a thin adhesive layer and direct thermal bonding near
glass transition temperature, have been proposed to achieve good bonding between
two polymer layers while maintaining the structural integrity of the bottom polymer
layers (Park et al., 2007).

Microtransfer molding was demonstrated to be suitable for forming complex, 3D

microstructures of organic polymers and ceramics (Zhao et al., 1996). A heat-curable
liquid epoxy (F109CLR) in the surface relief structure of a PDMS mold was partially
cured at 65°C for 25 min. The pre-cure of the pre-polymer increased its viscosity,
and thus greatly reduced the possibility that the pre-polymer in the grooves of the
mold would be drawn into gaps in the microstructure of the first layer by capillarity.
A substrate, the surface of which had already been patterned with one layer of a
microstructure, was placed upside down onto the mold with a pre-cured, filled relief
structure. The whole system was then fully cured at 25°C for 24 h. The PDMS mold
was peeled away and a two-layer microstructure was obtained. The process was
repeated to make the third layer. A 3D nanostructure was also imprinted using a
3D mold (Sun et al., 1998), and more complex 3D nanostructures such as sealed
cavities were obtained by combining simple 2D geometries from two molds (Kong et
al., 2004; Low et al., 2006). The careful selection of mold geometries in this method
constitutes a simplified and efficient approach toward building up desirable 3D
structures without resorting to the use of a sacrificial process or components. 3D
structures fabricated for a variety of specific applications were presented using both
thermoplastic and crosslinked polymer materials.

3D nanostructures, in particular with sub-40 nm metal T-gates and an air-bridge

structure, have been patterned with NIL in a single-step imprint in polymer and
metal by lift-off (Li et al., 2001). For this purpose, a method based on EBL and
RIE was developed to fabricate NIL molds with 3D protrusions. Nanometer-order
3D imprint molds have also been fabricated using acceleration voltage modulation
electron beam (EB) direct writing, in which spin-on-glass (SOG) is used as an EB
resist whose depth is controlled by changing the EB acceleration voltage (Taniguchi
et al., 2004). The exposed SOG area and depth were developed with 1 EB exposure
using buffered hydrofluoric acid (BHF), yielding a 3D SOG mold. Two acceleration
voltage changes were used, i.e., changing the EB gun bias and changing the sub-
strate voltage. A 3D sub-100 nm nanoimprint mold has been fabricated by using
control-of-acceleration-voltage EBL with inorganic resist, and by using UV-NIL, a
replicated pattern was obtained that approximately corresponded to the fabricated
mold (Unno et al., 2007). The process of fabrication of 3D gold pattern in one shot
on the PET substrate by using EBL is illustrated in Fig. 10.7.

10.7. Technological steps for fabrication of three-dimensional gold pattern on the

polyethylene terephthalate substrate by using EBL.

(Reprinted from Unno N, Taniguchi J, Ide S, Ishikawa S, Ootsuka Y, Yamabe K and

Kanbara T (2009), ‘Three dimensional metal nanoimprint technique for electrode and
electric probe’, Journal of Physics: Conference Series, 191, 012014. Copyright (2009)
with permission from IOP)
 The fabrication process of a 3D metal nanoimprint mold involves three major steps
(Unno et al., 2009). First, a positive tone EB resist is spin-coated on a cleaned Si
substrate and cured to form a 500 nm film. Second, the sample is delineated by
EB changing acceleration voltage. Then the EB-exposed area on the SOG film is
developed. Finally, a Cr layer having a thickness of around 10–20 nm is deposited
on a fabricated 3D mold. After coating the mold with Cr, the surface of Cr is oxidized
to Cr2O3. Next, gold is deposited on the Cr layer, after which the hot plate is heated,
and the PET substrate is placed on the hard mold for 30 min. After that, the PET
substrate is removed, and the gold pattern is transferred onto the PET substrate.

The fabrication of ordered 3D hierarchical nanostructures by NIL has been demon-

strated through exploiting the properties of imprinted polymers (Zhang and Low,
2006). The hierarchical structures were obtained by a series of sequential imprinting
steps, where smaller structures are imprinted on top of larger imprinted structures.
Higher order hierarchy was achieved by sequentially adding imprinting steps. An
important feature of this fabrication technique is that the subsequent imprinting is
carried out at a temperature below the glass transition temperature of the polymer
film and below the imprinting temperature of the preceding imprint without the
assistance of any solvents or plasticizers. This technique is suitable for the production
of various formats of hierarchical structures by varying the mold geometries and
mold orientations in the sequential imprinting.

Reverse contact UV-NIL is also an effective tool for the fabrication of 3D multilayered
nanostructures (Kehagias et al., 2006). This technique is a combination of reverse NIL
and contact ultraviolet lithography. In this process, a UV crosslinkable polymer and a
thermoplastic polymer are spin-coated onto a patterned hybrid metal-quartz stamp.
These thin polymer films are then transferred from the stamp to the substrate by
contact at a suitable temperature and pressure. The whole assembly is then exposed
to UV light. After separation of the stamp and the substrate, the unexposed polymer
areas are rinsed away with acetone, leaving behind the negative features of the
original stamp with no residual layer.

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