KAU CPCS 214 l 2008 .

I/O Systems Requirements, I/O device char-

acteristics, interconnect systems (shared bus,
Computer Organization point-to-point), addressing I/O devices (dedi-
and Architecture cated, memory-mapped), interfacing I/O (pro-
grammed, interrupt- driven, DMA).
Dr. Muhammad Al-Hashimi
. Parallel Processing An introduction to mul-
tiprocessing.
Credits 3
Homepage www.hashimi.ws/cs212
Textbook David A. Patterson and John L. Hen-
Email [email protected] nessy, Computer Organization & Design: The Hard-
Phone 695-1223 l 695-2000 & Ext. 51223 ware/Software Interface, 3rd edition, Morgan Kauf-
mann Publishers, 2004. ISBN: 1558606041
Office Fac. Computing & Info Tech l Room ?
Prerequisite CPCS 211 l C language basics Assessment Personal best 3 out of 4 tests, pro-
gramming and group discussion assignments. De-
ACM/IEEE CC2001 AR2–AR7, AR8.
tails in FAQ on the homepage.
40% Tests
This sophomore-level course explains how com- 10% Programming assignment
puters are designed and how they work. We study 10% Reading assignments
modern computer design principles using a typical 40% Final exam
processor. We then learn how efficient memory sys-
tems are designed to work closely with the pro- Learning Resources Check the homepage for the
cessor. Next, we study input/output (I/O) systems latest lecture schedule, summary and slides, discus-
which bring the processor and memory together with sion forums, audio clips, software tools, textbook re-
a wide range of devices. Finally, we briefly intro- sources, online guides and supporting web links.
duce systems with many processors. The course
emphasizes system- level issues, understanding pro- Learning Objectives Broadly (check lecture sum-
gram performance, and the use of abstraction as a maries for detailed learning outcomes):
tool to manage complexity.
. Examine how instructions and data are stored
and processed from high level to machine level.
Topics Material designed for 14 teaching weeks.
. Examine the assembly interface to hardware.
Check the homepage for current teaching schedule.
. Show how processors implement instruction set
. Instruction Sets Registers, ops and operands, architecture specifications.
assembly (symbolic) and machine instructions, . Explain how locality of reference is utilized to
addressing modes, instruction families, ma- build effective memory systems from different
chine instruction design, instruction set archi- storage technologies.
tecture. . Examine how memory systems interact with
. Computer Arithmetic Signed and unsigned the processor to execute instructions efficiently.
arithmetic, floating point format, arithmetic and . Describe how I/O devices interface to the pro-
accuracy, arithmetic instructions. cessor and memory.
. Identify key performance issues and how they
. Performance Evaluation Performance mea-
influence design and implementation
surement and reporting, execution times and
rates, Amdahl’s law. . Appreciate how abstraction is used to manage
design complexity.
. Processors Basic integer ALU, datapath de-
sign, hard-wired and microprogrammed con-
References Check homepage for complete list.
trol, processor performance, exceptions and in-
terrupts, instruction overlapping, pipelined exe- 1. Nicholas Carter, Schaum’s Outlines of Com-
cution, pipeline hazards, multiple-issue, super- puter Architecture, McGraw-Hill, 2002.
scalar and dynamically-scheduled pipelines. ISBN: 007136207X
. Memory Locality of reference, memory hi- 2. Sivarama P. Dandamudi, Guide to RISC
erarchies, cache design, interfacing with main Processors for Programmers and Engineers,
memory, cache performance, virtual memory, Springer 2005. ISBN: 0387210172
address translation, page management, page
faults, integration with cache. Rev 1.2