CHAPTER 4 (Part 1)
COMBINATIONAL LOGIC DEVICES
Lesson Outcome
At the end of the lesson, students
should be able to describe and
explain:
• Basic Combinational logic Circuits
• MSI Circuits Design
Arithmetic circuit – Adder (Half Adder, Full Adder, 4-bit parallel
Adder), substractor and multiplier
Comparator, 4-bit magnitude Comparator IC
Decoders (2-to-4, 3-to-8, 4-to-16, BCD-to-decimal, BCD-to-7-
segment, decoder ICs
Encoders (Decimal-to-BCD, Priority Encoder, Encoder ICs)
Code Converter
Data Selectors (Multiplexers, Demultiplexers, ICs)
• Simulation of Combinational Logic and MSI Circuits using Multisim
4.1 Basic Combinational logic circuits
• Combinational logic circuit is combination of
basic logic gate to serve certain functional
circuit
– Arithmetic circuit
– Comparator
– Decoder
– Encoder
– Multiplexer
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ARITHMETIC CIRCUITS
• Digital circuits are frequently used for
arithmetic operations
• Fundamental arithmetic operations on binary
numbers and digital circuits which perform
arithmetic operations will be examined.
– Half adder
– Full adder
– Parallel adder
– 2’s complement adder/subtractor
– Multiplier
– Comparator 145
Additional properties of XOR
XOR is also called modulo-2 addition
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
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Basic Adder
• Binary numbers are added like decimal
numbers.
• In decimal, when numbers sum more than 9
produce a carry result.
• Similarly, in binary when numbers sum more
than 1 a carry takes place.
• Addition is the basic arithmetic operation
used by digital devices to perform subtraction,
multiplication, and division
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Half Adder
• Half adder is a logical circuit that performs an
addition operation on two one-bit binary
numbers often written as A and B. It produces
a sum and an output carry. It cannot handle
input carry (Cin).
• The half adder output is a sum of the two
inputs usually represented with the signals
Cout (carry)and (sum)
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Half adder
149
Half adder
Step 1 : Truth Table
A B Cout
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Step 2
=A B Cout = AB
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Step 3
Half adder
• Half-adder only adds two bits.
• The problem with a half-adder is
it doesn’t handle carries.
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Full Adder
• Full adder is a logical circuit that performs an addition
operation on three one-bit binary numbers often written as
A, B, and Cin.
• The Full adder output The full adder produces a two-bit
output sum typically represented with the signals Carry Out
(Cout ) and Sum().
• Cascading – Connecting two or more similar devices in a
manner that expands the capability of one device.
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Full Adder
A full Adder has a Carry In
Construct a truth table of 3 inputs (2 numbers to be
added and carry in) and 2 outputs (sum and carry out).
Use algebraic methods or K-maps to simplify the
resulting SOP form.
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Full Adder
A B Carry in Carry out Sum
(Cout) ()
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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154
Full Adder
= (A B) Cin
Cout = AB + (A B)Cin
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Full Adder
• From the figures it shows that Full Adder is a
combination of 2 Half adder
Half adder
Full adder
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Full adder can be designed by combining 2 half adders and
OR gate
157
Parallel Adder
• Parallel adder Parallel adders are digital
circuits that compute the addition of variable
binary strings of equivalent or different size in
parallel.
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Parallel Adder
To add 2 bit numbers, we 2-bit parallel adder
need to combine 2 full
adders to become 2 bit A2 A1 01
parallel adder
B2 B1 11
3 2 1
100
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Parallel Adder
3-bit parallel adder
A3 A2 A1 101
B3 B2 B1 111
4 3 2 1
1100
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Parallel Adder
• The most common parallel adder is a 4 bit device
with 4 interconnected FAs and look-ahead Carry
circuits.
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Parallel Adder
• The A and B lines each represent 4 bit numbers to
be added. The C0 is the carry in, the C4 is the carry
out, and the lines are the sum of the 2 numbers.
4-bit parallel adder
A4 A3 A2 A1 1011
B4 B3 B2 B1 0110
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4-bit Parallel Adder IC – 74LS283 / 74LS83A
163
Example: Show how two 74LS283 (4-bit parallel adder) can be used
to form an 8-bit parallel adders. Show output bits for
the following 8-bit input numbers
A8 A7 A6 A5 A4 A3 A2 A1 10111001
B8 B7 B6 B5 B4 B3 B2 B1 10011110
A1 1 A5 1
A2 0 A6 1
A3 0 1 1 A7 0 1 5
A4 1 1 2 A8 1 0 6
B1 0 1 3 B5 1 1 7
B2 1 0 4 B6 0 0 8
B3 1 B7 0
B4 1 B8 1
1 9
GND
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2’s Complement Adder / Subtractor
• Addition of negative and positive numbers using adders is done by
placing the negative number into 2’s complement form and
performing normal addition.
• Subtraction is done by converting the number to be subtracted
(subtrahend) to 2’s complement and adding to the minuend.
• An adder can be used to perform addition and subtraction by
designing a way to take the 2’s complement for subtraction as
described in figure below
• C-B=A
• ; minuend (C) (the number from which the subtrahend is subtracted)
; subtrahend (B) (the number to be subtracted from the minuend)
; difference (A)
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Ex-or gate is used to invert the subtrahend (1’s complement)
and Cin was made ‘1’ and added to subtrahend (2’s
complement)
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For 2’s complement adder output verification
input
output
Note: The output of 2’s
complement adder is
same as per calculation
Minuend + 2’s complement of subtrahend , subtraction
was performed using adder circuit
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Multiplier.
Multiplier can be constructed using Full Adder and AND gates
To multiply two numbers :=
P1 = Product of A1 AND B1
P2 = (Product of A1 AND B2) +
(product of A2 AND B1) Multiplier Circuit
P3 = Carry from previous addition +
product of A2 AND B2
P4 = Carry from previous addition
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Comparator
The comparator compares two binary input quantities and
indicates whether the input bits are equal or not equal.
An EX-OR / EX-NOR gate is the easiest way to compare the
equality of 2 bits
A B 1 only when there are an odd
number of 1’s in (A,B). The same is true for
A B C 1
169
Comparing 2 bit-numbers using Ex-NOR
170
Magnitude comparator
A B F A=B A<B A>B
E L G
0 0 1 1 0 0
1-bit comparator
0 1 0 0 1 0
1 0 0 0 0 1
1 1 1 1 0 0
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2-bit magnitude comparator
1. Expression for G(Greater), E(Equal) and L(Less)
E=1 E ( A1 B1) ( A0 B0) E1 E 0
if all inputs A = all inputs B
G A1B1 ( A1 B1 A0 B0) A1B1 E1( A0 B0)
This means that A1=B1 AND A0=B0
L A1B1 ( A1 B1 A0B0) A1B1 E1( A0B0)
so E = ( A1 B1) ( A0 B0)
G=1 if A>B,
This means that [ A1>B1 OR ( A1=B1 AND A0>B0)]
So G= A1B1 ( A1 B1 A0B0 )
L=1 if A<B,
This means that [ A1<B1 OR ( A1=B1 AND A0<B0)]
So L= A1B1 ( A1 B1 A0B0 )
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2. Draw the logic circuit of the comparator
Example
Determine the expression G, E and L of 4-bit
comparator
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4-bit comparator
1. Expression for G(Greater), E(Equal) and L(Less)
E=1
if A=B
A3=B3 AND A2=B2 AND A1=B1 AND A0=B0
E ( A3 B3) ( A2 B2)( A1 B1) ( A0 B0) E1 E0
L=1
if A<B
(A3<B3) OR (A3=B3 AND A2<B2) OR
(A3=B3 AND A2=B2 AND A1<B1) OR
(A3=B3 AND A2=B2 AND A1=B1 AND A0<B0)
L A3B3 ( A3 B3 A2B2) ( A3 B3 A2 B2 A1B1) ( A3 B3 A2 B2 A1 B1 A0B0)
L A3B3 ( E3 A2B2) ( E3E 2 A1B1) ( E3E 2E1A0B0)
G=1
if A>B
(A3>B3) OR (A3=B3 AND A2>B2) OR
(A3=B3 AND A2=B2 AND A1>B1) OR
(A3=B3 AND A2=B2 AND A1=B1 AND A0>B0)
G A3B3 ( A3 B3 A2B2) ( A3 B3 A2 B2 A1B1) ( A3 B3 A2 B2 A1 B1 A0B0)
G A3B3 ( E3 A2B2) ( E3E 2 A1B1) ( E3E 2E1A0B0) 174
Integrated Circuit comparator 7485
Cascading inputs for expanding the comparison operation by
cascading two or more 4-bit comparators.
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Solution:
Given A = 0110 and B= 0011 . Determine the A=B, A>B, and A<B outputs for the
input number shown on the comparator in Figure below
A3 A2 A1 A0 B3 B2 B1 B0
0 1 1 0 0 0 1 1
‘1’ or ‘high’
‘0’ or ‘low’
‘0’ or ‘low’
CHECK BIT-BY-BIT
1. Start from MSB bit, check A>B or A<B
2. If A=B, check the next bit, A>B or A<B
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3. Until the last bit, A=B
Example
The numbers P and Q are applied to inputs of
7485. Determine the output for input:
a) P=1000 and Q=0100
b) P=0100 and Q=1000
c) P=1010 and Q=1000
d) P=1001 and Q=1001
e) P=1000 and Q=1001
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Example: Use 74LS85 comparators to compare the magnitudes of two 8 bit numbers.
Show the comparators with proper interconnections.
LSBs MSBs
To disable expansion A1 A5
inputs on LSB device
(A>B, A<B). Hence, the A2 A6
input bit is limited to A3 A7
four
A4 A8
+5V Output
B1 B5
B2 B6
B3 B7
B4 B8
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