Features of 8085
•1 Single +5 Power supply
•2 40 Pin IC
•3 0.8 micro second Instruction cycle
•4 On chip system controller
•5 64 KBytes Memory capacities
•6 One 8 bit accumulator
•7 Six 8 bit GPR's or three 16 bit register pair
•8 Serial In and Serial Output or slow speed transmission
•9 DMA(Direct Memory Access) for high speed transmission
•10 Multiplexed Address and Data Bus
•11 3 Vectored interrupt
•12 1 Non maskable interrupt
Basic System Timings
Memory Write Cycle
T1 T2 T3
A0-A15
Memory Address
AD0- AD7
A0-A7 Data form CPU
ALE
IO / M
WR
Memory Read Cycle
T1 T2 T3
A0-A15
Memory Address
AD0- AD7 A0-A7 Data form Memory
ALE
IO / M
RD
Instruction Set of 8085
•1 74 Operations
•2 246 Op-codes
•3 5 instruction groups
o1 Data Transfer instruction
•1 MVI, MOV, LXI, IN, OUT, LDA, STA…
o2 Arithmetic instructions
•1 ADD, SUB, ADI, SUI, INC, DED
o3 Logical Instruction
•1 ANA, ORA, XRA, RLC, RAR
o4 Branch Instruction
•1 JMP, JZ, CAL, RET (conditional)
o5 Stack and Machine control instruction
•1 EI, DI, RIM, SIM, HLT, NOP
•4 5 Flags
o1 Sign, Zero, Auxiliary Carry, Parity, Carry
•5 1+6 GPR’s
A (Accumulator) Flags
B C
D E
H L
Stack pointer (16 bit)
Program Counter (16 bit)
Simple Examples
ADDITION
---------
START: MVI A, 25H
ADI 55H
HLT
START: MVI A, 25H
MVI B, 55H
ADD B
HLT
16Bit addition
Start: LXI H, 1234H
LXI B, 4567H
DAD B
HLT
LXI H, 1234H
LXI B, 4567H
MOV A, L
ADD C
MOV L, A
MOV A, H
ADC B
MOV H, A
HLT
SUBSTRACTION
-------------
START: MVI A, 55H
SBI 25H
HLT
START: MVI A, 55H
MVI B, 25H
SUB B
HLT
16Bit subtraction
START: LXI H, 1234H
LXI B, 4567H
MOV A, L
SUB C
MOV L, A
MOV A, H
SBB B
MOV H, A
HLT
MULTIPLICATION of two 8-bit data giving 16-bit result
(Repetitive Addition)
----------------
START: LXI B, DATA1 ; Reg. B is zero and Reg C is 8 bit data
LXI D, DATA2 ; Reg. D is zero and Reg E is 8 bit data
LXI H, 00H ; Set result to zero
LOOP: DAD B ; Add Reg BC to HL
DCR E
JNZ LOOP
HLT
MULTIPLICATION of two 16 bit data giving 32 bit result
---------------- ; HL = BC * DE
START: LXI B, DATA1 ; Reg. BC 16 bit data
LXI D, DATA2 ; Reg. DE 16 bit data
LXI H, 00H ; Set result to zero, HL contain
PUXH H ; lower 16 bit result and stack has higher
; 16 bit result
LOOP: DAD B ; Add Reg BC to HL
JNC LOOP1
XCHG ; Exchange lower 16 bit with higer 16 bit
INX H ; add carry to higher 16 bit
XCHG ; make HL as lower 16 bit
LOOP1: DCX D ; decrement D, No flags is affected
MOV A, E ; Test DE is equal to zero
ORA D ;
JNZ LOOP ; repeat the addition if not zero
SHLD RSLT ; store the HL(lower 16bit) @ location Result
POP H ; store the higher 16 bit @ Result + 2
SHLD RSLT+2
HLT
DIVISION: 8 bit(repetitive subtraction)
----------
;Reg. A / Reg. B, Reg. D is Quotient, Reg. A is remainder
; Integer division
START: MVI A, 80H
MVI B, 5H
MVI D, 0H
CPI B, 0H
JZ LPEND
LOOP: CMP B
JC LPEND
SUB B
INC D
JMP LOOP
LPEND: HLT
BCD to Binary (Hexadecimal)
-------------------------- Algorithm
; BCD Bin Split the value into separate nibble
; 1 = 01h Higher nibble(10's) and lower
nibble(1's)
; 2 = 02h Add 0Ah higher nibble times
; 9 = 09h add lower nibble to the result
; 10 = 0Ah Ex.: Value is BCD 25
; 11 = 0Bh Higher nibble 2 and
; 15 = 0Fh Lower nibble 5
; 20 = 14H add 0Ah two time in binary
; to the result, add lower nibble
START:
MVI A, 25H ; BCD 25
MOV B, A
ANI 0FH
MOV C, A ; Reg. C is 05h
MOV A, B
ANI F0H ; Reg. A is 20h
RRC ; Shift higher nibble to
RRC ; lower nibble
RRC
RRC
MOV B, A ; Reg. B is 02h
ORA A ; Test Ten's Place, if zero, add
MVI A, 00H ; Lower nibble(One's place)
JZ LOOP1
LOOP: ADI 0AH
DCR B ; ADD 0AH, Reg. B times
JNZ LOOP
LOOP1: ADD C ; Add Reg. C to the result
HLT
8 bit Binary to BCD
-------------------
; Maximum value of 8 bit in decimal is 255
; 100th place is 2, Tens place is 5 and unit place is 5.
; Note: DAA(Decimal adjust after addition), works for Reg. A only
; Algorithm:
; Repetitively subtract 64h(100 in decimal) from the value until
; remainder is less than 64h. Count each subtraction using DAA. This
; gives 100's place.
; From the remainder, repeat the same procedure with 0Ah(10 in
; decimal)to get 10's place
; Shift the value to higher nibble & the remainder (1's place) to it.
;
; Reg A : Hexadecimal value
; Reg DE : Packed BCD
START: MVI A, 96H ; 150 in decimal
MVI C, 00H
LOOP: CPI 64H
JC LOOP1
SBI 64H
INC C
JMP LOOP
LOOP1: MOV D, C ; 100th place in D
MOV A, B ; get back remainder for finding 10’ value
MVI C, 00H
LOOP2: CPI 0AH
JC LOOP3
SBI 0AH
INC C
JMP LOOP2
LOOP3: MOV B, A
MOV A, C ; Get the 1o’s count in A
RLC ; move the count higher nibble
RLC
RLC
RLC
ADD A, C ; pack unit place value
MOV E, A
HLT
Subroutine/function for delay
LXI H, FFFFH HL = Count 10 T states
LOOP: DCX H 6
MOV A, H 4
ORA L 4
JNZ LOOP 10/7
RET 10
Delay in terms T states
= 10 T + 24 T * count + 10 T
= 20 + 24 * count
if count = FFFFH
Then delay is
= 20 + 24 * 65536
= 20 + 1572840
= 1572860 T.
If T is 1/(3.141 MHZ) then delay in seconds is 0.5007
