DSP TMS320F2812 Used as an Universal Decoder

Using PLL
[1] [2] [3]
Mr. Mohit Ravindra Thakur Miss. Amrita Arjunprasad Sah Mr. Viraj Vilas Kamble

Dept. of Electronics and Telecommunication, PVPP’s College of Engineering Sion, Mumbai

Abstract- There are various encoder and decoder are used with a huge bulky circuit. These can be reduced with the
help of DSP TMS320F2812. There are various digital encoding and decoding techniques which can be performed
with the help of DSP instead of the huge bulky combinations. This can also be used as Universal Decoder for a
Frequency channel. It can intelligently sense type of encoding done on a signal and give us a perfect decoded
output which will be applied at input of encoder.

Keywords:- Digital Signal Processor(DSP), Phase Lock Loop(PLL),Code Composer Studio(CCS).

mathematically manipulate them. A DSP is

I. INTRODUCTION designed for performing mathematical functions
The DSP used as Universal Decoder for various like "add", "subtract", "multiply" and "divide"
frequency using PLL. As we know when a signal very quickly A DSP's information can be used by
travels through any path there are some losses a computer to control such things as security,
present in it and its necessary to remove the losses telephone, home theater systems, and video
so we use PLL which locks the loop and remove compression. Signals may be compressed so that
noise over it. In DSP processor we can do the wave they can be transmitted quickly and more
analysis and form there equations. efficiently from one place to another (e.g.
Due to the equation form in DSP we can easily teleconferencing can transmit speech and video
detect its type and decode the signal. In this the via telephone lines). Signals may also be
implementation of digital phase lock loop on enhanced or manipulated to improve their
Digital Signal Processor(DSP) TMS320F2812 is quality or provide information that is not sensed
done . We studied about the basic block of PLL by humans (e.g. echo cancellation for cell
with its block diagram and simulation of each and phones or computer-enhanced medical images).
every block . Although real-world signals can be processed in
The PLL can be used in many applications of their analog form, processing signals digitally
power supplies, as encoder or decoder and also provides the advantages of high speed and
used to synchronize the power in grid line for accuracy.
future scopes.

 Aim of the project:

Our project aim is to get signal decoded for

various frequencies and also to achieve various
types of signal through a single circuit or by using
DSP ,it will act as an Universal decoder for
multiple frequency and multiple signal types. Block diagram of DSP
It can also be used as an spy watcher for the
sensitive frequency bands.

II. LITERATURE REVIEW 2).Digital PLL :

Digital PLL (DPLL) synthesizer is at the
1).Digital Signal Processor(DSP): Digital origin of most single loop synthesizers. It
Signal Processors (DSP) take real-world signals requires placing a digital divider in the loop
like voice, audio, video, temperature, pressure, between the VCO and the phase detector,
or position that have been digitized and then thereby making it able to run at a higher

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 frequency than that of the phase detector. This Because of the increase in the speed of the circuit
will in turn make the VCO frequency to be operation, there is a need of a PLL circuit with faster
divided by the division ratio of the divider, for locking ability.
instance n, and the VCO will run at n times the Many present communication systems operate in
phase comparison frequency. Changing the the GHz frequency range. Hence there is a necessity
division ratio of the divider, will also change of a PLL which must operate in the GHz range with
the output frequency of the oscillator. This less lock time.
makes the frequency synthesizer PLL is a mixed signal circuit as its architecture
programmable. involves both digital and analog signal processing
units.

Block diagram of Digital PLL

Block diagram of PLL

III. SYSTEM DEVELOPMENT 2). DSP (TMS350F2812):- Features

• High-performance static CMOS technology
– 150 MHz
– Low-power design

• JTAG boundary scan support

– IEEE Standard 1149.1
-1990 IEEE Standard Test Access Port and
Boundary
-Scan Architecture

• High-performance 32
1).Phase Locked Loops (PLL):-
-bit CPU (TMS320C28x)
– 16 × 16 and 32 × 32 MAC operations
The most versatile application of the phase locked
– 16 × 16 dual MAC
loops (PLL) is for clock generation and clock
– Harvard bus architecture
recovery in microprocessor, networking,
– Atomic operations
communication systems, and frequency synthesizers.
– Fast interrupt response and processing
– Unified memory programming model
Phase locked-loops (PLLs) are commonly used
– 4M linear program/data address reach
to generate well-timed on-chip clocks in high
– Code-efficient (in C/C++ and Assembly)
performance digital systems. Modern wireless
– TMS320F24x/LF240x processor source code
communication systems employ Phase Locked Loop
compatible
(PLL) mainly for synchronization, clock synthesis,
skew and jitter reduction.
• On-chip memory
– Up to 128K × 16 flash
– 1K × 16 OTP ROM
– L0 and L1: 2 blocks of 4K × 16 each

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 Single Access RAM (SARAM)
– H0: 1 block of 8K × 16 SARAM
– M0 and M1: 2 blocks of 1K × 16 each SARAM

• Boot ROM (4K × 16)

– With software boot modes
– Standard math tables

• External interface (F2812)

– Over 1M × 16 total memory
– Programmable wait states
– Programmable read/write strobe timing
– Three individual chip selects

• Clock and system control

– On-chip oscillator
– Watchdog timer module

• Three external interrupts

• Peripheral Interrupt Expansion (PIE) block that Display :

supports 45 peripheral interrupts Here we are using led 16*2 display as shown in fig.
In this we are going to show the signal message and the
• Three 32-bit CPU timers signal is decoded or not.

• 128-bit security key/lock The first line will be used for message to display
– Protects flash/OTP and L0/L1 SARAM whereas we are coding second line for the output to get
– Prevents firmware reverse-engineering • Motor displayed
control peripherals
– Two Event Managers (EVA, EVB)
– Compatible to 240xA devices

• Serial port peripherals

– Serial Peripheral Interface (SPI)
– Two Serial Communications Interfaces (SCIs),
standard UART
– Enhanced Controller Area Network (eCAN)
– Multichannel Buffered Serial Port (McBSP)

• 12-bit ADC, 16 channels IV. Encoding and decoding process

– 2 × 8 channel input multiplexer
– Two Sample-and-Hold Encoding is the process of converting data from one
– Single/simultaneous conversions form to another. While "encoding" can be used as a
– Fast conversion rate: 80 ns/12.5 MSPS verb, it is often used as a noun, and refers to a specific
type of encoded data. There are several types of
• Up to 56 General-Purpose I/O (GPIO) pins encoding, including image encoding, audio and video
encoding, and character encoding.
Media files are often encoded to save disk space. By
encoding digital audio, video, and image files, they can
be saved in a more efficient, compressed format.
Encoded media files are typically similar in quality to
their original uncompressed counterparts, but have
much smaller file sizes. For example, a WAVE (.WAV)
audio file that is converted to an MP3 (.MP3) file may
be 1/10 the size of the original WAVE file. Similarly,
an MPEG (.MPG) compressed video file may only

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require a fraction of the disk space as the original
digital video (.DV) file.

Decoding is the process of converting code into plain

text or any format that is useful for subsequent
processes. Decoding is the reverse of encoding. It
converts encoded data communication transmissions
and files to their original states.

V. REFERENCES

1. Texas Instruments Reference Guide of

TMS320F2812 DPS Processor
2. Texas Instruments Reference Guide of
TMS320F2812 Event Manager (EV).
3. IEEE Papers on DSP & PLL.