Mapua Institute of Technology
School of Electrical, Electronics and Computer Engineering
COE133L/C1
Alarm Clock
Submitted By:
Date Submitted: September 13, 2016
Instructor
Introduction
Hardware Description Language (HDL) is used to model, describe, and simulate the structure and
behavior of electronic circuits. There are two major types of hardware description language: VHDL, and
Verilog. The latter is used in this project. There are types of description in HDL. They are the dataflow,
structural, and behavioral. In Verilog, behavioral models contain procedural statements that control the
simulation and manipulate variables of the data types previously described. These statements are
contained within procedures. Each procedure has an activity flow associated with it. On the other hand,
structural modeling describes the interconnection between the components of a hardware module and the
design of the hardware by connecting various modules and gates, such as and, and or. Lastly, dataflow
modelling in Verilog allows a circuit to be designed in terms of the data flow between registers and how a
design processes data rather than instantiation of individual gates.
The project is limited to the creation of a digital alarm clock using Verilog HDL. The program has an
alarm function, which, when connected to a buzzer, will turn it on. On the other hand, when not
connected, it will yield a value of 1.
Program Code
module mux2b16(s,minm1,hrm1,minm2,hrm2,min_out,hr_out);
input [7:0]minm1,hrm1,minm2,hrm2;
output [7:0] min_out,hr_out;
input s;
assign {min_out, hr_out}= (s==0)?{minm1,hrm1}:{minm2,hrm2};
endmodule
module memory(reset, clk, sec_in ,min_in, hour_in, sec_out, min_out , hour_out);
input reset, clk;
input [7:0] sec_in ,min_in;
input [7:0] hour_in;
output reg [7:0] sec_out ,min_out;
output reg [7:0] hour_out;
always @(posedge clk or reset)//sec_in, min_in, hour_in)
begin
if(reset==1)
begin
sec_out <= 8'h0;
min_out <= 8'h0;
hour_out<= 8'h0;
end
else
begin
sec_out <= sec_in;
min_out <= min_in;
hour_out<=hour_in;
end
end
endmodule
module displaydecoder(reset, bcd_in, disp_out);
input reset;
input [3:0]bcd_in;
output reg [6:0]disp_out; //abcd efg
always @(posedge reset, bcd_in)
begin
if(reset==1)
disp_out = 7'b0000001;
else
case(bcd_in)
4'd0: disp_out = 7'b1111110;
4'd1: disp_out = 7'b0110000;
4'd2: disp_out = 7'b1101101;
4'd3: disp_out = 7'b1111001;
4'd4: disp_out = 7'b0110011;
4'd5: disp_out = 7'b1011011;
4'd6: disp_out = 7'b1011111;
4'd7: disp_out = 7'b1110000;
4'd8: disp_out = 7'b1111111;
4'd9: disp_out = 7'b1111011;
default: disp_out = 7'b0000001;
endcase
end
endmodule
module counter60(reset, clkin, count, tc);
input reset, clkin;
output reg [7:0]count;
output reg tc;
always @( posedge reset , posedge clkin)
begin
if(reset == 1)
begin
count<=8'h0;
tc <= 1'b0;
end
else
begin
if(count == 8'h59)
begin
count <= 8'h0;
tc <= 1'b1;
end
else
begin
count[3:0] = count[3:0] + 1'b1;
tc <= 1'b0;
if(count[3:0] == 4'd10)
begin
count[3:0] <= 4'd0;
count[7:4] <= count[7:4] + 4'h1;
end
end
end
end
endmodule
module counter24(reset, clkin, count, tc);
input reset, clkin;
output reg [7:0]count;
output reg tc;
always @( posedge reset , posedge clkin)
begin
if(reset == 1)
begin
count<=8'h0;
tc <= 1'b0;
end
else
begin
if(count == 8'h23)
begin
count <= 8'h0;
tc <= 1'b1;
end
else
begin
count[3:0] = count[3:0] + 1'b1;
tc <= 1'b0;
if(count[3:0] == 4'd10)
begin
count[3:0] <= 4'd0;
count[7:4] <= count[7:4] + 4'h1;
end
end
end
end
endmodule
module alarmunit(en,clk,almin,alhr,min,hr,assert);
input en, clk;
input [7:0] almin,alhr,min,hr;
output reg assert;
always@(posedge clk)
begin
if(en==0)
assert<=1'b0;
else if(almin==min && alhr ==alhr)
assert <= 1;
else
assert <=0;
end
endmodule
module clockunit(reset,clkin, clkout);
input reset,clkin;
output reg clkout;
reg [25:0]cnt;
always @(posedge clkin , posedge reset)
begin
if(reset==1)
begin
cnt = 26'd0;
clkout = 1'b1;
end
else
cnt = cnt + 1'b1 ;
if(cnt == 26'd2500)
begin
clkout = ~clkout;
cnt = 26'd0;
end
end
endmodule
module controlunit(reset, clk, mode, num, enablealarm, enabledisplay, setalarm, settime,min_out,hr_out);
input reset,clk;
input [3:0]num;
input [1:0]mode;
reg [7:0]min,hr;
output reg enablealarm,enabledisplay,setalarm,settime;
output reg [7:0]min_out,hr_out;
reg [2:0]currstate,nextstate;
parameter IDLE=3'd0,GOT1=3'd1,GOT2=3'd2,GOT3=3'd3,GOT4=3'd4;
parameter DISP=2'd0,SETT=2'd1,SETA=2'd2,DISA=2'd3;
always@(posedge reset or posedge clk )
begin
if(reset)
begin
enablealarm=1;
enabledisplay=1;
currstate<=IDLE;
nextstate<=IDLE;
settime<=0;
setalarm<=0;
min_out<=8'h0;
hr_out<=8'h0;
end
else
currstate<=nextstate;
end
always@(posedge clk)
begin
case(mode)
DISP:
begin
enabledisplay<=1;
nextstate<=IDLE;
settime<=0;
setalarm<=0;
end
//---------------------------
SETT:
begin
case(nextstate)
IDLE:
begin
enabledisplay<=0;
nextstate<=GOT1;
settime<=0;
setalarm<=0;
end
GOT1:
begin
enabledisplay<=0;
hr[7:4]<=num[3:0];
nextstate<=GOT2;
end
GOT2:
begin
enabledisplay<=0;
hr[3:0]<=num[3:0];
nextstate<=GOT3;
end
GOT3:
begin
enabledisplay<=0;
min[7:4]<=num[3:0];
nextstate<=GOT4;
end
GOT4:
begin
min[3:0]=num[3:0];
settime<=1;
min_out<=min;
hr_out <=hr;
nextstate<=IDLE;
enabledisplay<=1;
end
endcase
end
//-----------------------------------
SETA:
begin
case(nextstate)
IDLE:
begin
enabledisplay<=0;
nextstate<=GOT1;
settime<=0;
setalarm<=0;
end
GOT1:
begin
enabledisplay<=0;
hr[7:4]<=num[3:0];
nextstate<=GOT2;
end
GOT2:
begin
enabledisplay<=0;
hr[3:0]<=num[3:0];
nextstate<=GOT3;
end
GOT3:
begin
enabledisplay<=0;
min[7:4]<=num[3:0];
nextstate<=GOT4;
end
GOT4:
begin
enabledisplay<=1;
min[3:0]=num[3:0];
setalarm<=1;
min_out<=min;
hr_out <=hr;
nextstate<=IDLE;
end
endcase
end
//---------------------------------------
DISA:
begin
enablealarm<=0;
nextstate<=IDLE;
end
endcase
end
endmodule
module testbench;
reg system_clk, reset;
wire [7:0] alarmsec, alarmmin, alarmhr;
wire [7:0] seca, mina, hra,minm1,hrm1,minm2,hrm2,sec, min, hr; //a stands for asynchronous output
wire [6:0] disp;
wire sec_clk, tc_s, tc_m;
wire [1:0]mode;
wire [3:0]num;
wire enablealarm, enabledisplay, setalarm, settime, trigger;
wire [7:0]minset,hrset;
wire alert;
reg [7:0]alarmmin1,alarmhr1;
// load control to counter60, 24
// alarm function
initial
begin
system_clk=1'b1;
reset = 1'b1;
#1
reset = 1'b0;
alarmmin1=8'h01;
alarmhr1 =8'h00;
end
always
#10000 system_clk = ~system_clk;
clockunit clockunit1( reset, system_clk, sec_clk);
counter60 seconds(reset, sec_clk, seca, tc_s);
counter60 minutes(reset,tc_s, mina, tc_m);
counter24 hour(reset, tc_m, hra, tc_h);
mux2b16 mux1(settime,mina, hra, minset,hrset,minm1,hrm1);
memory timekeeper(reset,sec_clk, seca, minm1, hrm1,sec, min, hr);
displaydecoder dis(reset, sec[3:0] ,disp);
controlunit controlio(reset,trigger,mode,num,enablealarm, enabledisplay, setalarm,
settime,minset,hrset);
memory alarmkeeper(reset,setalarm, 8'h0, minset, hrset,alarmsec, alarmmin, alarmhr);
alarmunit alarm1(enablealarm,sec_clk, alarmmin1, alarmhr1,min,hr,alert);
endmodule
