Application Report

SPRACM9 – June 2019

EtherCAT Based Connected Servo Drive Using Fast

Current Loop on PMSM

Ramesh T Ramamoorthy

ABSTRACT
This application report helps to evaluate EtherCAT communication and to perform frequency response
analysis of fast current loop (FCL) enabled control loops of a connected servo drive using TI's
TMS320F28388D real-time controller. The platform used is TI's DesignDRIVE IDDK EVM kit and the
C2000Ware MotorControl SDK. Frequency response analysis is performed in software using TI's Software
Frequency Response Analyser (SFRA) library running in realtime on the control MCU F28388D. Besides
controlling the motor, the MCU also performs EtherCAT communication with a TwinCAT running on PC.
F2838x MCU is a part of the C2000™ family of microcontrollers. It has has two C28x CPU cores and an
Arm® Cortex®-M4 core for performing control and communication effectively using a range of powerful
peripherals for digital power and motor control applications. In servo drive space, it enables cost-effective
design of intelligent, high-bandwidth controllers for 3-phase motors, by reducing the system components
and increasing efficiency. The devices are appropriately supported by hardware accelerators to implement
FCL algorithms to rival or surpass similar implementations using FPGA in terms of performance, cost, and
development time.
The application report describes the following:
• Incremental build levels calling modular FCL and EtherCAT functions spread across CPU, M4 and CLA
cores
• Experimental results

Contents
1 Introduction ................................................................................................................... 3
2 Benefits of the TMS320F2838x MCU for High-Bandwidth Current Loop............................................. 3
3 Current Loops in Servo Drives ............................................................................................. 4
4 Outline of the Fast Current Loop Library ................................................................................. 5
5 Fast Current Loop Library Evaluation ..................................................................................... 7
6 Incremental Build Level 1 .................................................................................................. 9
7 Incremental Build Level 2 ................................................................................................. 12
8 Incremental Build Level 3 ................................................................................................. 16
9 Incremental Build Level 4 ................................................................................................ 20
10 Incremental Build Level 5 ................................................................................................. 22
11 Incremental Build Level 6 ................................................................................................. 24
12 Incremental Build Level 7 ................................................................................................ 34
13 Incremental Build Level 8 ................................................................................................ 41

List of Figures
1 Basic Scheme of FOC for AC Motor ...................................................................................... 4
2 Fast Current Loop Library Block Diagram ................................................................................ 5
3 Level 1 Block Diagram ..................................................................................................... 9
4 Expressions Window for Build Level 2 .................................................................................. 10
5 Voltage Angle and SVGEN Ta, Tb, and Tc ............................................................................ 11
6 DAC Outputs Showing Ta, Tb Waveforms ............................................................................. 12
7 Level 2 Block Diagram..................................................................................................... 13

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8 Scope Plot of Reference Angle and Rotor Position ................................................................... 14

9 Expressions Window....................................................................................................... 15
10 Level 3 Block Diagram Showing Inner Most Loop - FCL ............................................................. 17
11 Expressions Window Snapshot For Latency ........................................................................... 18
12 Scope Plot of ADCSoC and FCL Completion Events ................................................................. 19
13 Level 4 Block Diagram Showing Speed Loop With Inner FCL ....................................................... 20
14 Flux and Torque Components of the Stator Current in the Synchronous Reference Frame Under 0.33-pu
Step-Load and 0.3-pu Speed ............................................................................................. 21
15 Level 5 Block Diagram Showing Position Loop With Inner FCL ..................................................... 23
16 Scope Plot of Reference Position to Servo and Feedback Position................................................. 23
17 Level 6 Block Diagram..................................................................................................... 25
18 SFRA GUI ................................................................................................................... 27
19 SFRA GUI MC .............................................................................................................. 27
20 GUI Setup Diagram ........................................................................................................ 28
21 SFRA GUI Connected to the C2000 MCU ............................................................................. 29
22 SFRA Open Loop Bode Plots of the Current Loop Showing Magnitude and Phase Angle ...................... 30
23 SFRA Closed Loop Bode Plots of the Current Loop Showing Magnitude and Phase Angle .................... 31
24 SFRA Open Loop Bode Plots of the Current Loop - Current Feedback With High SNR ......................... 32
25 SFRA Closed Loop Bode Plots of the Current Loop - Current Feedback With High SNR ....................... 32
26 Plot of Gain Cross over Frequency vs Phase Margin as Experimentally Obtained ............................... 34
27 TwinCAT Config Mode Icon............................................................................................... 36
28 TcSwitchRunTime Window Activated ................................................................................... 36
29 TwinCAT Solution Explorer .............................................................................................. 38
30 TwinCAT EEPROM Window ............................................................................................. 39
31 TwinCAT Restart in Config Mode Icon ................................................................................. 39
32 EtherCAT Slave in OP Mode ............................................................................................ 40
33 TwinCAT Solution Explorer Inputs and Outputs ....................................................................... 40
34 F2838x CM EtherCAT Slave (SYSTEM) Input/Output Data .......................................................... 41

List of Tables
1 Summary of FCL Interface Functions ..................................................................................... 6
2 Functions Verified in Each Incremental System Build .................................................................. 8
3 Functional Modules Used in Each Incremental System Build ......................................................... 8
Trademarks
C2000 is a trademark of Texas Instruments.
Arm, Cortex are registered trademarks of Arm Limited.

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www.ti.com Introduction

1 Introduction
The concept of FOC of AC drives is well known and is already outlined in many earlier documents from TI.
Modern AC servo drives, depending on the end application, need high-bandwidth current control and
speed control to enable superior performance, such as in CNC machines or in fast and precision control
applications. Because of the high computational burden and the need for flexible PWMs, a combination of
FPGAs, fast external ADCs, and multiple MCUs are used by many designers.
With the TMS320F2838x MCU, due to its higher level of integration, it is possible to implement fast current
loop algorithms with the same external hardware used in classical FOC methods. TI has developed the
FCL algorithm on the F2838x MCU and implemented it on the Design DRIVE IDDK platform. With a 10-
kHz PWM carrier, the current loop gain crossover frequency is expected to exceed 3 kHz, and the closed
loop bandwidth is expected at about 5 KHz (per NEMA ICS 16 and Chinese GBT 16439-2009) and the
maximum duty cycle is expected to be approximately 96%. This document provides information needed to
evaluate this algorithm on the DesignDRIVE IDDK platform.
Besides control, TMS320F2838x MCU has an Arm Cortex-M4 based Connectivity Manager and an
EtherCAT Slave Control peripheral. This helps to seamlessly integrate control and communication in a
single chip to enable development of cost effective solutions for industrial servo drives.

1.1 Acronyms Used in This Document

• DMC – Digital Motor Control
• IDDK – Industrial Drive Development Kit (from TI)
• MCU – Microcontroller Unit
• FOC – Field-Oriented Control
• TMU – Trigonometric Mathematical Unit (in C2000 MCU)
• CLA – Control Law Accelerator (in C2000 MCU)
• CLB – Configurable Logic Block (in C2000 MCU)
• PMSM – Permanent Magnet Synchronous Motor
• ACIM – AC Induction Motor
• FCL – Fast Current Loop
• HVDMC – High Voltage DMC
• CMPSS – Comparator Subsystem peripheral (in C2000 MCU)
• CNC – Computer Numerical Control
• PWM – Pulse Width Modulation
• FPGA – Field Programmable Gate Array
• ADC – Analog-to-Digital Converter
• ePWM – Enhanced Pulse Width Modulator
• eQEP – Enhanced Quadrature Encoder Pulse Module
• eCAP – Enhanced Capture Module
• ECAT - EtherCAT

2 Benefits of the TMS320F2838x MCU for High-Bandwidth Current Loop

The C2000 MCU family of devices possesses the desired computation power to execute complex control
algorithms and the correct combination of peripherals to interface with the various components of the
DMC hardware, such as the ADC, ePWM, QEP, and eCAP. These peripherals have all the necessary
hooks to provide flexible PWM protection, such as trip zones for PWMs and comparators.
The F2838x MCU contains additional hardware features such as the following:
• Higher CPU and CLA clock frequency
• Four high-speed, 12- and 16-bit ADCs
• Trigonometric and Math Unit (TMU)
• Parallel processing block, such as the CLA
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• CLBs
Together, these features provide enough hardware support to increase computational bandwidth
compared to its predecessors and offer superior real-time control performance. In addition, the C2000
ecosystem of software (libraries and application software) and hardware (TMDXIDDK379D) help users
reduce the time and effort needed to develop a high-end digital motor control solution.

3 Current Loops in Servo Drives

Figure 1 shows the basic current loop used in FOC servo drives.

VDC
Inv. Park Tr.
iSqref VSqref VSaref
PI d,q
SV 3-phase
PWM Inverter
iSdref VSdref VSbref
PI a,b

q
q
iSq iSa ia
d,q a,b

iSd iSb ib
a,b a,b
Park Tr. Clarke Tr.

AC
Motor

Figure 1. Basic Scheme of FOC for AC Motor

Two motor phase currents are measured. These measurements feed the Clarke transformation module.
The outputs of this projection are designated isα and isβ. These two components of the current along with
the rotor flux position are the inputs of the Park transformation, which transform them to currents (isd and
isq) in d and q rotating reference frame. The isd and isq components are compared to the references isdref
(the flux reference) and isqref (the torque reference). At this point, the control structure shows an interesting
advantage; it can be used to control either synchronous or asynchronous machines by simply changing
the flux reference and obtaining the rotor flux position. In the synchronous permanent magnet motor, the
rotor flux is fixed as determined by the magnets, so there is no need to create it. Therefore, when
controlling a PMSM motor, isdref can be set to zero, except during field weakening.
Because ACIM motors need a rotor flux creation to operate, the flux reference must not be zero. This
conveniently solves one of the major drawbacks of the classic control structures: the portability from
asynchronous to synchronous drives. The torque command isqref can be connected to the output of the
speed regulator. The outputs of the current regulators are Vsdref and Vsqref. These outputs are applied to the
inverse Park transformation. Using the position of rotor flux, this projection generates Vsαref and Vsβref, which
are the components of the stator vector voltage in the stationary orthogonal reference frame. These
components are the inputs of the Space Vector PWM. The outputs of this block are the signals that drive
the inverter.

NOTE: Both Park and inverse Park transformations need the rotor flux position. Obtaining this rotor
flux position depends on the AC machine type (synchronous or asynchronous).

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www.ti.com Outline of the Fast Current Loop Library

4 Outline of the Fast Current Loop Library

The major challenge in digital motor control systems is the influence of sample and hold, as well as
transportation lag inside the loop that slows down the system, impacting its performance at higher
frequencies and running speeds. To overcome this problem, improve the current loop bandwidth, and
enable higher DC bus usage, the following are necessary:
• High computational power
• The correct set of control peripherals
• Superior control algorithm
While the TMS320F2838x provides the necessary hardware support for higher performance, TI's FCL
library, which runs on the C2000 MCU, provides the necessary algorithmic support.
To improve the operational range of FCLs, the latency between feedback sampling and the PWM update
must be as small as possible. Typically, a latency of 2 µS or less is considered acceptable in many
applications. Traditionally, this task is implemented using a combination of high-end FPGAs, external
ADCs, and MCUs.

PWM1 A/B

IqRef PWM2 A/B

IdRef PWM3 A/B

lsw
FAST CURRENT LOOP
Rg.Out Iph1 (Ia)

ElecTheta Iph2 (Ib)

MechTheta Iph3 (Ic)

QEP

Figure 2. Fast Current Loop Library Block Diagram

The FCL library uses the following features in the F2838x MCU:
• TMU
• Four high-speed 12- and 16-bit ADCs
• Multiple parallel processing blocks such as CLA
Figure 2 shows the block diagram of the FCL library with its inputs and outputs. The FCL library partitions
the algorithm across the CPU, CLA, and TMU to bring down the latency to under 1.0 µs compared to the
acceptable 2 µs. Further optimization is possible if the algorithm is written in assembly.
The FCL library supports two types of current regulators, a standard PI controller and a complex
controller. The complex controller can provide additional bandwidth over the standard PI controller at
higher speeds. Both current regulators are provided for user evaluation. In the example project, the
current regulator can be selected by setting the FCL_CNTLR macro appropriately and studying how they
compare.

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Table 1 lists the FCL API functions and their descriptions.

Table 1. Summary of FCL Interface Functions

API Function Description
uint32_t FCL_getSwVersion(void) Function that returns a 32-bit constant, and for this version the value returned is
0x00000006.
void FCL_runComplexCtrl(void) Function that performs the complex control as part of the FCL
void FCL_runPICtrl(void) Function that performs the PI control as part of the FCL
void FCL_runPICtrlWrap(void) Wrap up function to be called by the user application at the completion of FCL in
PI control mode before exiting ISR
void FCL_runQEPWrap(void) Function to be called by the user application to wrap up the QEP feedback
procedure. This function is used only in FCL_LEVE2.
void FCL_runComplexCtrlWrap(void) Wrap up function to be called by the user application at the completion of FCL in
complex control mode before exiting ISR
void FCL_initPWM( Function to initialize PWMs for the FCL operation, this will be called by the user
uint32_t basePhaseU, uint32_t basePhaseV, application during the initialization or setup process.
uint32_t basePhaseW
);
void FCL_resetController(void) This function is called to reset the FCL variables and is useful when you want to
stop the motor and restart the motor.
void FCL_initQEP(uint32_t baseA); This function initializes the eQEP peripheral for connecting to the QEP
void FCL_initADC(uint32_t resultBaseA, This function initializes the ADCs that are used to sense the motor phase
ADC_PPBNumber baseA_PPB, uint32_t currents
resultBaseB, ADC_PPBNumber baseB_PPB,
uint32_t adcBasePhaseW);

For more information on the library, see the Fast Current Loop MotorControl SDK Library User's Guide
available at:
\ti\c2000\C2000Ware_MotorControl_SDK_version\libraries\fcl\docs.

NOTE: The library is written in a modular format and is able to port over to user platforms using
F2837x / F2838x devices if the following conditions are met:
• Motor phase current feedbacks are read into variables internal to the library. However, D
axis and Q axis current feedbacks are available.
• PWM modules controlling motor phase A, B, and C are linked to the library.
• A QEP module connecting to the QEP sensor is linked to the library.
• CLA tasks one through four are used by the library. This must be accommodated in the
user application.

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www.ti.com Fast Current Loop Library Evaluation

5 Fast Current Loop Library Evaluation

TI provides the FCL algorithm software library for evaluation using the TMS320F2838x MCU on TI’s
DesignDRIVE IDDK platform. This section presents a step-by-step approach to evaluating the FCL
software library to control a permanent magnet synchronous motor using an example project.
Example project features:
• Sensored FOC of the PMSM motor
• FCL using the FCL library
• Position, speed, and torque control loops
• Position sensor support: incremental encoder (QEP)
• Current sensing: analog feedback using the ADC (from LEM sensors (Fluxgate/HALL))

5.1 Evaluation Setup

5.1.1 Hardware
The example project is evaluated on TI’s Design DRIVE Development Kit IDDK - TMDXIDDK379D. The
DesignDRIVE IDDK Hardware Reference Guide and DesignDRIVE IDDK User Guide for the kit can be
found at C:\ti\c2000\C2000Ware_MotorControl_SDK_version\solutions\tmdxiddk379d\docs\.
The DesignDRIVE IDDK Hardware Reference Guide gives an overview of the various hardware functional
blocks in the kit, discusses the various ground configurations it supports and the safety measures
necessary to work with the kit. It is important to understand the hardware and the safety aspects before
working with the kit.
The DesignDRIVE IDDK User Guide helps in setting up the hardware and in getting started with software,
connecting to the target platform and working with the debug environment using Code Composer Studio.

5.1.2 Software
When the MCSDK software package is installed, the FCL software library can be found at
C:\ti\c2000\C2000Ware_MotorControl_SDK_version\libraries\observers\fcl\lib.
The FCL example project can be found at:
C:\ti\c2000\C2000Ware_MotorControl_SDK_version\solutions\tmdxiddk379d\f2838x\ccs\sensored_foc
Here, a few more build levels are added to step through with integrating the FCL library to run the motor in
speed mode and position mode.

5.1.3 Incremental System Build

The system is gradually built up through various build levels verifying specific functionality at each level so
that at the final level, the system is fully verified and complete in all aspects. Eight levels of incremental
system build are designed to verify the various modules used in the system. Levels 1 through 5 build upto
a FCL enabled position controlled servo drive. Level 6 helps to perform the frequency response analysis
using SFRA. Levels 7 and 8 build upto a connected servo drive performing speed control or position
control.

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Table 2 and Table 3 summarizes the core functions integrated and tested at each build level as well as
the cores used to perform the tasks in each of the incremental builds.

Table 2. Functions Verified in Each Incremental System Build

Cores Used
Buildlevel CPU1 CM Functional Integration / Verification
LEVEL 1 √ Basic PWM generation
LEVEL 2 √ Open loop control of motor / calibration of feedbacks
LEVEL 3 √ CURRENT MODE - Closing current loop using FCL library
LEVEL 4 √ SPEED MODE - Closing speed loop using inner FCL verified in LEVEL 3
LEVEL 5 √ POSITION MODE - Closing position loop using inner speed loop verified in
LEVEL 4
LEVEL 6 √ SFRA ANALYSIS - Performing SFRA on current loop running motor in speed
mode (LEVEL 4)
LEVEL 7 √ √ ECAT loop back to TwinCAT - No motor control involved
LEVEL 8 √ √ Fully connected servo drive using TwinCAT to control the motor in speed mode
(LEVEL 4) or position mode (LEVEL 5)

Table 3. Functional Modules Used in Each Incremental System Build

Software
Module Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8
PWM √√ √ FCL lib FCL lib FCL lib FCL lib FCL lib
Generation
QEP √√ √ √ √ √ √
Interface in
CLA
FOC
√√ √ √ √ √
functions
SFRA √√
functions
ECAT √√ √
functions

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6 Incremental Build Level 1

The block diagram of the system built in BUILD LEVEL 1 is shown in Figure 3. During this step, keep the
motor disconnected.
Ds Ta Mfunc_C1 PWM1 A/B
VdTesting IPARK SVGEN
Alpha Ualpha
MACRO MACRO
Qs Tb Mfunc_C2
VqTesting PWM PWM PWM2 A/B
Beta Ubeta MACRO HW
Angle Tc Mfunc_C3 PWM3 A/B

RC RG
MACRO MACRO
TargetValue SetPointValue Freq
Watch
SpeedRef Window

DlogCh1

Var1 DATALOG DlogCh2

On chip Graph DlogCh3
Scope Var2
DACs Window
DlogCh4

Figure 3. Level 1 Block Diagram

Assuming the load and build steps described in the DesignDRIVE IDDK User Guide completed
successfully, this section describes the steps for a “minimum” system check-out which confirms operation
of system interrupt, the peripheral and target independent inverse park transformation and space vector
generator modules, and the PWM initializations and update modules.
1. Open fcl_qep_f2838x_tmdxiddk_settings_cpu1.h and select the level 1 incremental build option by
setting the BUILDLEVEL to FCL_LEVEL1 (#define BUILDLEVEL FCL_LEVEL1).
2. Right-click on the project name and click Rebuild Project.
3. When the build is complete, click on debug button, reset the CPU, restart, enable real time mode, and
run.
Add variables to the expressions window by right-clicking within the Expressions Window and
importing the fcl_f2838x_tmdxiddk_vars_cpu1.txt file from the debug directory. Figure 4 shows the
variables imported into the Expressions Window from this file. Ignore the values shown against the
variables for now.

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Figure 4. Expressions Window for Build Level 2

4. Set enableFlag to 1 in the watch window. The variable named isrTicker is incrementally increased, as
seen in the watch windows, to confirm the interrupt working properly.
In the software, the key variables to be adjusted are:
a. speedRef : for changing the rotor speed in per-unit.
b. VdTesting : for changing the d-qxis voltage in per-unit.
c. VqTesting : for changing the q-axis voltage in per-unit.

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6.1 SVGEN Test

The speedRef value is fed into the ramp control module to ramp up the speed command. The output of
the ramp module is fed into a ramp generator to generate the angle for sinewave generation. This angle
as well as the variables VdTesting and VqTesting feeds into inverse park transformation block which then
feeds into space vector modulation modules to generate three phase PWMs.
The outputs from space vector generation module can be viewed using the graph tool from the debug
environment by clicking Tools --> Graph --> Dual Time. Then, from the graph window, click Import and
browse to and select:
\solutions\tmdxiddk379d\f2838x\debug\fcl_f2838x_tmdxiddk_graph1.graphProp
This plots two graphs representing variables pointed by dlogCh1 and dlogCh2. Likewise, another graph
can be opened by selecting:
solutions\tmdxiddk379d\f2838x\debug\fcl_f2838x_tmdxiddk_graph2.graphProp
This plots two graphs representing variables pointed by dlogCh3 and dlogCh4.

Figure 5. Voltage Angle and SVGEN Ta, Tb, and Tc

These are shown in Figure 5. These are the voltage vector angle, and the pulse width values for the
phases A, B, and C and are denoted as Ta, Tb, and Tc, where Ta, Tb, and Tc waveforms are 120
degrees apart from each other. Specifically, Tb lags Ta by 120 degrees and Tc leads Ta by 120 degrees.
These are generated based on the values of speedRef, VdTesting and VqTesting. These values can be
changed to see the impact on these waveforms. Check the PWM test points on the board to observe
PWM pulses (PWM-1H to 3H and PWM-1L to 3L) and ensure that the PWM module is running properly.

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6.2 Testing SVGEN with DACs

To monitor internal signal values in real time, onchip DACs are used. DACs are part of the analog module.
DACs B and C are available for this purpose. This is shown in Figure 6.

Figure 6. DAC Outputs Showing Ta, Tb Waveforms

6.3 Inverter Functionality Verification

After verifying the space vector generation and PWM modules, the 3-phase inverter hardware can be
tested by looking at inverter outputs U, V, and W on a scope. This can be compared against the PWM
pulses (PWM-1H to 3H) fed into the inverter. It is advisable to gradually increase the DC bus voltage
during this test. Check inverter outputs U, V, and W using an oscilloscope with respect to the inverter
GND, while taking care of scope isolation requirements. This ensures that the inverter is working properly.

7 Incremental Build Level 2

Assuming build level 1 is completed successfully, this section verifies the overcurrent protection limits of
the inverter and QEP interface running out of the CLA. In this build, the motor is run in open loop.
The motor can be connected to the HVDMC board because the PWM signals are successfully proven
through the incremental build level 1.
1. Open fcl_qep_f2838x_tmdxiddk_settings_cpu1.h and select the level 2 incremental build option by
setting the BUILDLEVEL to FCL_LEVEL2 (#define BUILDLEVEL FCL_LEVEL2).
2. Select CURRENT_SENSE to LEM_CURRENT_SENSE and POSITION_ENCODER to
QEP_POS_ENCODER.
3. Right-click on the project name and click Rebuild Project.
4. When the build is complete, click Debug, reset the CPU, restart, enable real-time mode, and run.

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www.ti.com Incremental Build Level 2

Figure 7 shows the level 2 block diagram.

Level 2 Incremental System Build Block Diagram

Ds Ta Mfunc_C1 PWM1 A/B 3-Phase

VdTesting IPARK SVGEN
Alpha Ualpha Inverter
MACRO MACRO
Qs Tb Mfunc_C2 PWM PWM PWM2 A/B
VqTesting
Beta Ubeta MACRO HW
Angle Tc Mfunc_C3 PWM3 A/B

RC RG
MACRO MACRO
TargetValue SetPointValue Freq Out

Iph1 (Ia)

Iph2 (Ib)

Iph3 (Ic)

DlogCh1

DATALOG DlogCh2
Graph
DlogCh3
Window
DlogCh4

SPEED FR QEP
Var1 Speed
On MACRO
QEP Interface Incremental PM
Scope chip Var2 ElecTheta Module Encoder
SpeedRpm Motor
DACs (CLA) Interface

Level 2 verifies the QEP interface running on CLA.

Figure 7. Level 2 Block Diagram

5. Set enableFlag to 1 in the watch window. The variable named isrTicker is incrementally increased as
shown in the Expressions window to confirm the interrupt is working properly. Now set the variable
named runMotor to MOTOR_RUN; the motor starts spinning after a few seconds if enough voltage is
applied to the DC-Bus.
In the software, the key variables to be adjusted are same as in previous level and are given again
below for reference.
a. speedRef: for changing the rotor speed in per-unit
b. VdTesting: for changing the d-axis voltage in per-unit
c. VqTesting: for changing the q-axis voltage in per-unit
During the open loop tests, VqTesting, speedRef, and DC bus voltages must be adjusted carefully for
PM motors so that the generated Bemf is lower than the average voltage applied to motor winding.
This adjustment prevents the motor from stalling or vibrating.

7.1 Setting the Overcurrent Limit in the Software

The board has various current sense methods, such as shunt, LEM, and SDFM. Overcurrent monitoring is
provided for signals generated from shunt and LEM using an on-chip comparator subsystem (CMPSS)
module. The module has a programmable comparator and a programmable digital filter. The comparator
generates the protection signal. The reference to the comparator is user programmable for both positive
and negative currents. The digital filter module qualifies the comparator output signal, verifying its sanity
by periodically sampling and validating the signal for a certain count time within a certain count window,
where the periodicity, count, and count window are user programmable.
In the Expressions window, users can see the following variables:
• clkPrescale – sets the sampling frequency of the digital filter
• sampWin – sets the count window
• thresh – sets the minimum count to qualify the signal within sampWin
• curLimit – sets the permitted current maximum through both shunt and LEM current sensors

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tripFlagDMC is a flag variable that represents the overcurrent trip status of the inverter. If this flag is set,
then you can adjust the previous settings and try to rerun the inverter by setting clearTripFlagDMC to 1.
This clears tripFlagDMC and restarts the PWMs.
The default current limit setting is to shut down at 8 A. Any of these settings can be fine-tuned to suit your
system. When satisfactory values are identified, write them down, modify the code with these new values,
and rebuild and reload for further tests.
It is possible to shut down the inverter using a digital signal from an external source through H9. No code
is provided currently, but it can be used as an exercise to experiment and learn.

7.2 Current Sense Method

The CURRENT_SENSE method chosen for this library is LEM_CURRENT_SENSE. It is possible to use
the SHUNT_CURRENT_SENSE method in certain configurations, but it is not included in the library.

7.3 Voltage Sense Method

Voltage is sensed using the sigma delta filter module 3. Look out for the variable FCL_params.Vdcbus in
the Expressions window. Vary the DC bus voltage slowly and verify whether this variable tracks this
change properly. For example, a 100-V DC voltage should be shown as 100.0 by this variable.

7.4 Setting Current Regulator Limits

The outputs of the current regulators control the voltages applied on both the d-axis and q-axis. The vector
sum of the d and q outputs must be less than 1.0, which refers to the maximum duty cycle for the SVGEN
macro. In this particular application, the maximum allowed duty cycle is set to 0.96. Higher computational
speeds allow higher duty cycle operation and better use of the DC bus voltage.
The current regulator output is represented by the same variable pi_id.out and pi_iq.out in both PI and
complex controller modes. The regulator limits are set by pi_id.Umax/min and pi_iq.Umax/min.
Bring the system to a safe stop by reducing the bus voltage to zero, taking the controller out of real-time
mode, and resetting.

7.5 Position Encoder Feedback and runSpeedFR() Test

During all the previous tests, the position encoder interface was continuously estimating position
information. Therefore, no new code is needed to verify the position encoder interface. When the motor is
commanded to run, it is subjected to an initial alignment stage where the electrical angle and the QEP
angle count are set to zero. If a resolver or absolute encoder (EnDat or BiSS-C) is used, its initial position
at electrical angle zero is identified for run-time corrections. Estimated position information is made
available on DAC-C, while the reference position (rg1.Out) used to perform open-loop motor control is
displayed on DAC-B. Figure 8 shows these signals brought out on H10 on the IDDK, and their scope
plots.

Figure 8. Scope Plot of Reference Angle and Rotor Position

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The waveform of channel 2 represents the reference position, while channel 1 represents the estimated
position. The ripple in position estimate is indicative of the fact that the motor runs with some minor speed
oscillation. Because of open-loop control, the rotor position and reference position may not align.
However, it is important to ensure that the sense of change of the estimated angle is the same as that of
the reference; otherwise, it indicates that the motor has a reverse sense of rotation. This can be fixed by
either swapping any two wires connecting to the motor, or reversing the angle estimate as in the
pseudocode in the software (see Equation 1).
angle = 1.0 – angle (1)
To ensure that the function runSpeedFR() works, change the speedRef variable in the Expressions
window, as shown in Figure 9, and check whether the estimated speed variable, speed1.Speed, follows
the commanded speed. Because the motor is a PM motor, where there is no slip, the running speed
follows the commanded speed regardless of the control being open loop.

Figure 9. Expressions Window

When the tests are complete, bring the system to a safe stop by reducing the bus voltage, taking the
controller out of real-time mode, and resetting it. Now, the motor stops.

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8 Incremental Build Level 3

Assuming the previous section is completed successfully, this section verifies the dq-axis current
regulation performed by the FCL. One of the two current controllers can be chosen: PI or complex. The
bandwidth of the controllers can be set in the debug window.

NOTE: In this build, control is done based on the actual rotor position; therefore, the motor can run
at higher speeds if the commanded IqRef is higher and there is no load on the motor. TI
advises to either add some mechanical load on the motor before the test or apply lower
values of IqRef. When the motor is commanded to run, it is subjected to an initial alignment
stage where the electrical angle and the QEP angle count are set to zero. They are then
forced to run based on an enforced angle until the QEP index pulse is received. Then the
motor runs in full self-control mode based on its own angular position.

1. Open fcl_qep_f2838x_tmdxiddk_settings_cpu1.h and select the level 3 incremental build option by

setting BUILDLEVEL to FCL_LEVEL3 (#define BUILDLEVEL FCL_LEVEL3).
The current loop regulator can be selected to be the PI controller or the complex controller by setting
FCL_CNTLR to PI_CNTLR or CMPLX_CNTLR. The CURRENT_SENSE method chosen for this library
is LEM_CURRENT_SENSE. The current and position feedbacks can be sampled once or twice per
PWM period, depending on the sampling method. The sampling is synchronized to the carrier
maximum in the single sampling method, and to the carrier maximum and carrier zero in the double
sampling method. This sample method selection is done in the example by selecting
SAMPLING_METHOD to SINGLE_SAMPLING or SAMPLING_METHOD to DOUBLE_SAMPLING.
The maximum modulation index changes from 0.98 in the SINGLE_SAMPLING method to 0.96 in the
DOUBLE_SAMPLING method. If the PWM_FREQUENCY is changed from 10 kHz, the maximum
modulation index also changes.
2. Right-click on the project name, and then click Rebuild Project. When the build is complete, click the
Debug button, reset the CPU, restart, enable real-time mode, and run.
In the software, the key variables to add, adjust, or monitor are summarized as follows:
• maxModIndex : maximum modulation index
• IdRef : changes the d-axis voltage in per-unit
• IqRef : changes the q-axis voltage in per-unit
• FCL_params.WccD : preferred bandwidth of d-axis current loop
• FCL_params.WccQ : preferred bandwidth of q-axis current loop
• fclLatencyInMicroSec : shows latency between ADC and QEP sampling, and PWM in µs
• fclClrCntr : flag to clear the variable fclLatencyInMicroSec and let it refresh
• runMotor : flag to RUN or STOP the motor

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Figure 10 shows the level 3 block diagram.

Level 3 Incremental System Build Block Diagram

lsw=0
Constant 0 PWM1 A/B
3-Phase
IqRef IqRef PWM2 A/B Inverter
lsw=1, 2

IdRef IdRef PWM3 A/B

RC RG lsw lsw
MACRO MACRO
TargetValue SetPointValue Freq Out FAST CURRENT LOOP
Rg.Out Iph1 (Ia)

ElecTheta Iph2 (Ib)

MechTheta Iph3 (Ic)

SPEED FR
Speed MACRO

SpeedRpm QEP

PM
Motor

Level 3 verifies the dq-axis current regulation performed by PI modules and speed measurement modules.

Figure 10. Level 3 Block Diagram Showing Inner Most Loop - FCL

The key steps are explained as follows:

1. Set enableFlag to 1 in the watch window. The isrTicker variable is incrementally increased, as seen in
watch windows to confirm the interrupt is working properly.
2. Verify if the maxModIndex value is either 0.96 in double-sampling method or 0.98 in single-sampling
method.
3. Set speedRef to 0.3 pu (or another suitable value if the base speed is different), IdRef to zero, and
IqRef to 0.03 pu (or another suitable value). speedRef helps only until the QEP index pulse is received.
Thereafter, the motor is controlled based on its rotor position.
4. Gradually increase voltage at variac / DC power supply to, for example, 20% of the rated voltage.
5. lsw is a state machine variable representing the functional state of interacting with quadrature encoder.
Its various states are as follows:
a. lsw = QEP_ALIGNMENT --> lock the rotor of the motor
b. lsw = QEP_WAIT_FOR_INDEX --> motor in run mode and waiting for the first instance of QEP
index pulse
c. lsw = QEP_GOT_INDEX --> motor in run mode - QEP index pulse occurred
6. Set runMotor flag to MOTOR_RUN to run the motor.
7. Notice that lsw state is autopromoted in a sequence (code is inside the FCL library)
8. Check pi_id.fbk in the watch windows with the continuous refresh feature and see if it can track IdRef.
9. Check pi_iq.fbk in the watch windows with the continuous refresh feature and see if it can track IqRef.
10. To confirm these two current regulator modules, try different values of pi_id.ref and pi_iq.ref, by
changing the values of IdRef and IqRef, respectively.
11. Try different bandwidths for the current loop by tweaking the values of FCL_params.wccD and
FCL_params.wccQ. The default setting for the bandwidth is 1/18 of the sampling frequency.
12. If the motor shaft can be held tight, then the IqRef value can be changed back and forth from 0.5 to
–0.5, to study the effect of loop bandwidth.
13. Bring the system to a safe stop by reducing the bus voltage, taking the controller out of real-time
mode, and resetting. Now the motor stops.

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8.1 Observation One – PWM Update Latency

8.1.1 From the Expressions Window

While running the motor in this build level and subsequent build levels, observe the variable
fclLatencyInMicroSec in the Expressions window.
Figure 11 shows a snapshot of the Expressions window.

Figure 11. Expressions Window Snapshot For Latency

This variable indicates the amount of time elapsed between the feedback sampling and PWM updating.
The elapsed time, or latency, is computed based on the count of the EPWM timer right after the PWM
update. The value shown here is more than the actual update time by a few clock cycles. Immediately
after setting the runMotor flag to MOTOR_RUN and the motor begins to run, the latency time shows up as
nearly 1.25 µS due to initial setup in the code. This amount of latency occurs at a time when the duty
cycle is moderate and is therefore acceptable. After this period, you can refresh the latency time by setting
fclClrCntr to 1. Regardless of SAMPLING_METHOD, latency remains the same for a given FCL_CNTLR.
When FCL_CNTLR is a PI_CNTLR, the latency is about 0.96 µs compared to 0.98 µs with a
CMPLX_CNTLR (see the following note).

NOTE:
• These times can be reduced further by around 0.1-µs range using code inline and other
optimization techniques. Because the evaluation code is in library format, it has certain
overheads.
• The sampling window for ADC is kept wide enough to ensure a cleaner signal
acquisition. Depending on board layout and circuits feeding in to ADC channels, it may
be possible to reduce this time window by nearly 60%.

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8.1.2 From the Scope Plot

NOTE: Because H7 is not populated, GPIO16 and GPIO18 are used for timing purposes instead of
for designed functional assignment. If H7 is to become populated, comment out the
associated code and restore the functional assignment.

Figure 12 shows the latency discussed previously in the form of a scope plot, where the rising edge of the
channel 2 and channel 1 waveforms signify the instances of the ADC SoC event and completion of all
PWM updates, respectively. These events are brought out over GPIO16 and GPIO18, and may be probed
over [Main]-R31 and [Main]-R33, respectively. The time seen in the scope plot may be slightly more than
fclLatencyInMicroSec. This additional time is needed for the CPU to return from FCL library and to set
GPIO .

Figure 12. Scope Plot of ADCSoC and FCL Completion Events

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9 Incremental Build Level 4

Assuming the previous section is completed successfully, this section verifies the speed PI module and
speed loop. When the motor is commanded to run, it is subjected to an initial alignment stage where the
electrical angle and the QEP angle count are set to zero. After ensuring a stable alignment, the motor
starts running.
1. Open fcl_qep_f2838x_tmdxiddk_settings_cpu1.h and select the level 4 incremental build option by
setting the BUILDLEVEL to FCL_LEVEL4 (#define BUILDLEVEL FCL_LEVEL4). The current loop
regulator can be selected to be PI controller or complex controller by setting FCL_CNTLR to
PI_CNTLR or CMPLX_CNTLR. The CURRENT_SENSE method chosen for this library is
LEM_CURRENT_SENSE.
2. Right-click on the project name, and then click Rebuild Project. When the build is complete, click the
Debug button, reset the CPU, restart, enable real-time mode, and run.
In the software, the key variables to be adjusted are summarized as follows:
• speedRef: for changing the rotor speed in per-unit.
• IdRef: for changing the d-axis voltage in per-unit.
• IqRef: for changing the q-axis voltage in per-unit.
Figure 13 shows the implementation block diagram.
Level 4 Incremental System Build Block Diagram

Auto switched
Constant 0 lsw=0
from start
PWM1 A/B
Ref IqRef lsw=1
SpeedRef PI 3-Phase
MACRO lsw=2 IqRef PWM2 A/B Inverter
Fbk
Spd Reg
IdRef IdRef PWM3 A/B

RC RG lsw lsw
MACRO MACRO
TargetValue SetPointValue Freq Out FAST CURRENT LOOP
Rg.Out Iph1 (Ia)

ElecTheta Iph2 (Ib)

MechTheta Iph3 (Ic)

SPEED FR
Speed MACRO

SpeedRpm QEP

PM
Motor
Level 4 verifies the speed PI module and speed loop.

Figure 13. Level 4 Block Diagram Showing Speed Loop With Inner FCL

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The key steps are explained as follows:

1. Set enableFlag to 1 in the watch window. The isrTicker variable is incrementally increased as seen in
watch windows to confirm the interrupt is working properly.
2. Set speedRef to 0.3 pu (or another suitable value if the base speed is different).
3. Add pid_spd variable to the Expressions window
4. Gradually increase voltage at variac to get an appropriate DC-bus voltage.
5. Set runMotor to MOTOR_RUN
6. Notice that the state machine variable (lsw) is autopromoted in a sequence, its states are as follows:
a. lsw = QEP_ALIGNMENT --> lock the rotor of the motor
b. lsw = QEP_WAIT_FOR_INDEX --> motor in run mode and waiting for the first instance of QEP
index pulse
c. lsw = QEP_GOT_INDEX --> motor in run mode - QEP index pulse occurred
7. Compare the speed (speed1.Speed) with speedRef in the watch windows with the continuous refresh
feature to see whether or not it is nearly the same.
8. To confirm this speed PID module, try different values of speedRef (positive or negative). The P, I, and
D gains may be tweaked to get a satisfactory response.
9. At a very low speed range, the performance of the speed response relies heavily on the good rotor
position angle provided by the QEP encoder.
10. Bring the system to a safe stop by reducing the bus voltage, taking the controller out of real-time
mode, and resetting. Now the motor stops.
Figure 14 shows flux and torque components of the stator current in the synchronous reference frame.

Figure 14. Flux and Torque Components of the Stator Current in the Synchronous Reference Frame
Under 0.33-pu Step-Load and 0.3-pu Speed

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9.1 Observation
In the default set up, the current loop bandwidth is set up as 1/18 of the SAMPLING FREQUENCY for
both CMPLX_CNTLR and PI_CNTLR. As the bandwidth is increased, control becomes stiff and the motor
operation becomes noisier as the controller reacts to tiny perturbations in the feedback trying to correct
them, see the note below. The gain cross over frequency (or open loop bandwidth) can be taken up to 1/6
of the SAMPLING_FREQUENCY and still get good transient response over the entire speed range
including higher speeds. If the motor rotation direction is reversed occasionally due to any malfunction, try
restarting it by setting runMotor to MOTOR_STOP and then MOTOR_RUN again. It may need some fine
tuning in transitioning from lsw = QEP_WAIT_FOR_INDEX to lsw = GOT_INDEX. This can be used as an
exercise to fix it.

NOTE: The fast current loop is a high bandwidth enabler. When the designed bandwidth is high, the
loop gains can also be high. This pretty much ties the loop performance to the quality of
current feedback. If the SNR of current feedback signal into the digital domain is poor, then
the loop can be very audibly noisy as the controller tries to minimise the error. If the noise is
bothersome, the user may be required to reduce the bandwidth to avoid the audible noise.

10 Incremental Build Level 5

This section verifies the position PI module and position loop with a QEP. For this loop to work properly,
the speed loop must have been completed successfully. When the motor is commanded to run, it is
subjected to an initial alignment stage where the electrical angle and the QEP angle count are set to zero.
After ensuring a stable alignment, the motor starts to run.
1. Open fcl_qep_f2838x_tmdxiddk_settings_cpu1.h and select the level 5 incremental build option by
setting the BUILDLEVEL to FCL_LEVEL5 (#define BUILDLEVEL FCL_LEVEL5). The current loop
regulator can be selected to be PI controller or complex controller by setting FCL_CNTLR to
PI_CNTLR or CMPLX_CNTLR. The CURRENT_SENSE method chosen for this library is
LEM_CURRENT_SENSE.
2. Right-click on the project name, and then click Rebuild Project. When the build is complete, click the
Debug button, reset the CPU, restart, enable real-time mode, and run. Set runMotor to MOTOR_RUN
in the Expressions window. Setting this flag runs the motor through predefined motion profiles and
position settings as set by the refPosGen() module. This module basically cycles the position reference
through a set of values as defined in an array posArray. These values represent the number of the
rotations and turns with respect to the initial alignment position. Once a certain position value as
defined in the array is reached, it pauses for a while before slewing toward the next position in the
array. Therefore, these array values can be referred to as parking positions. During transition from one
parking position to the next, the rate of transition (or speed) is set by posSlewRate. The number of
positions in posArray through which it passes before restarting from the first value is decided by
ptrMax. Hence, add the variables posArray, ptrMax, and posSlewRate to the Expressions window.
The key steps are explained as follows:
1. Set enableFlag to 1 in the watch window. The isrTicker variable is incrementally increased as seen in
the watch windows to confirm the interrupt is working properly.
2. Add variables pi_pos, posArray, ptrMax, and posSlewRate to the Expressions window.
3. Gradually increase voltage at variac to get an appropriate DC-bus voltage.
4. Set runMotor to MOTOR_RUN to run the motor. The motor must be turning to follow the commanded
position (see the following note if the motor does not turn properly).
5. The parking positions in posArray can be changed to different values to determine if the motor turns as
many rotations as set.
6. The number of parking positions ptrMax can also be changed to set a rotation pattern.
7. The position slew rate can be changed using posSlewRate. This rate represents the angle (in pu) per
sampling instant.
8. The proportional and integral gains of the speed and position PI controllers may be returned to get
satisfactory responses. TI advises to first tune the speed loop and then the position loop.

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9. Bring the system to a safe stop by reducing the bus voltage, taking the controller out of real-time mode
and reset. Now the motor stops.
Figure 15 shows the implementation block diagram.
Level 5 Incremental System Build Block Diagram

Auto switched
Ref from start
PositionRef Constant 0 lsw=0 PWM1 A/B
PI Ref
SpeedRef
MACRO PI IqRef lsw=1 3-Phase
Fbk IqRef PWM2 A/B
Pos Reg MACRO lsw=2 Inverter
Fbk
Spd Reg
IdRef IdRef PWM3 A/B

RC RG lsw lsw
MACRO MACRO
TargetValue SetPointValue Freq Out FAST CURRENT LOOP
Rg.Out Iph1 (Ia)

ElecTheta Iph2 (Ib)

MechTheta Iph3 (Ic)

SPEED FR
Speed MACRO

SpeedRpm QEP

PM
Motor
Level 5 verifies the position PI module and position loop.

Figure 15. Level 5 Block Diagram Showing Position Loop With Inner FCL

In the scope plot shown in Figure 16, the position reference, and position feedback are plotted. They are
aligned with negligible lag, which may be attributed to software. If the Kp and Ki gains of the position loop
controller are not chosen properly, this may lead to oscillations in the feedback or a lagged response.

Figure 16. Scope Plot of Reference Position to Servo and Feedback Position

NOTE:
• If the motor response is erratic, then the sense of turn of the motor shaft and the
encoder may be opposite. Swap any two phase connections to the motor and repeat the
test.
• The position control implemented here is based on an initial aligned electrical position (=
0). If the motor has multiple pole pairs, then this alignment can leave the shaft in
different mechanical positions depending on the prestart mechanical position of the
rotor. If the mechanical position repeatability or consistency is needed, then the QEP
index pulse must be used to set a reference point. This may be taken as an exercise.

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11 Incremental Build Level 6

Assuming the previous build level is successfully completed, this build level attempts to study the
frequency response analysis of the Fast Current Loop using C2000’s Software Frequency Response
Analyzer (SFRA) tool, available as a library in the DigitalPower SDK.

11.1 Integrating SFRA Library

The user's guide (C2000™ Software Frequency Response Analyzer (SFRA) Library and Compensation
Designer in SDK Framework) that describes the SFRA tool and guides the user in integrating it into the
C2000 platform can be found at:
C:\ti\c2000\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra\Doc
The embedded firmware is available as a library in the DigitalPower SDK at:
C:\ti\c2000\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra
The SFRA GUIs are available as executable applications in the DigitalPower SDK at:
C:\ti\c2000\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra\gui
Some example projects to understand SFRA are available at:
c:\ti\c2000\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra\examples
In the ISR code, there are two functions that inject noise for SFRA and then collect the feedback data from
the loop, they are:
• injectSFRA()
• collectSFRA()
The roles of these functions are self-explanatory from their names. They should be used in the
sequence they are used in the code to collect the data in right sequence.

NOTE:
• The disturbances due to analog signal path and quantization will impact the loop
performance and hinder high bandwidth selections that can be verified using SFRA
results. Therefore it is important to provide a current feedback with a higher SNR.
• When evaluating current loops, if it is possible to hold the motor speed constant, it will
help to minimize the impact of speed jitter related errors in the SFRA results. This is
particularly useful when studying the Iq loop. If the voltage decoupling of current loop is
good, then this requirement may not matter.

This tool provides the ability to study the D-axis or Q-axis current loops or the speed loop. The motor can
be run at different speed / load conditions and at different bandwidths and the performance can be
evaluated at each of these conditions. It can be seen that the controller can provide the designed
bandwidth under all these conditions with a certain tolerance.

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SFRA
Control PWM1 A/B
SpeedRef
PI
Fbk MACRO IqRef PWM2 A/B
3-Phase
Spd Reg
+ IdRef
Inverter
PWM3 A/B
Auto switched
lsw
from start
FAST CURRENT LOOP
Rg.Out Iph1 (Ia)
SPEED FR
Speed MACRO ElecTheta Iph2 (Ib)

MechTheta Iph3 (Ic)

QEP

PM
Motor
QEP

Figure 17. Level 6 Block Diagram

The implementation block diagram is given in Figure 17. The SFRA tool injects noise signal into the
system at various frequencies and analyzes the system response and provides a Bode Plot of the actual
physical system as seen during the test.

11.2 Initial Setup Before Starting SFRA

The setting up involves co-ordination between the debug environment and the SFRA GUI. Until getting
familiar with connecting the SFRA GUIs to the target platform, it is a good idea to turn off the high voltage
power input to the target platform. Open ’fcl_qep_f2838x_tmdxiddk_settings_cpu1.h’ and select level 6
incremental build option by setting the BUILDLEVEL to FCL_LEVEL6 (#define BUILDLEVEL
FCL_LEVEL6).
Open ’fcl_f2838x_sfra_settings_cpu1.h’ and watch out for the definitions:
• SFRA_FREQ_START
• SFRA_FREQ_LENGTH
• FREQ_STEP_MULTIPLY
These definitions inform the GUI about the starting value of noise frequency, number of different noise
frequencies to sweep and the ratio between successive sweep frequencies respectively. More information
is available in the C2000™ Software Frequency Response Analyzer (SFRA) Library and Compensation
Designer User's Guide associated with SFRA. In the context of this evaluation project, it is important to
know and appreciate these parameters to tweak them for further repeat tests.
In this motor control project, SFRA can be performed on any of the three control loops such as the speed
loop, D axis current loop and Q axis current loop. Technically, this could be performed on position loop as
well, but is not included in this project scope and the user can take it as an experiment if desired.
Right click on the project name and click Rebuild Project. Once the build is complete click on debug
button, reset CPU, restart, enable real time mode and run. From the debug environment, the steps to be
followed are shown below:
Add the following variable in the ‘Expressions Window’:
• sfraTestLoop : for selecting the control loop on which to evaluate SFRA, letting you choose between:
– SFRA_TEST_D_AXIS - D axis current loop
– SFRA_TEST_Q_AXIS - Q axis current loop
– SFRA_TEST_SPEEDLOOP - speed loop

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The key steps can be explained as follows:

1. Set enableFlag to 1 in the watch window. The variable named IsrTicker will be incrementally increased
as seen in watch windows to confirm the interrupt working properly.
2. The SCI initialisations needed to communicate with the GUIs should be all done by now.
3. Further steps with the debug window will follow after setting up the GUIs to connect to target platform.

11.3 SFRA GUIs

There are two GUIs available to perform the frequency response analysis, one (SFRA_GUI) to plot open
loop and plant Bode diagram, and another (SFRA_GUI_MC) to plot open loop and closed loop Bode
diagram. They can be invoked and connected to the target platform to study the control loops. The GUI
executables are available in the location as mentioned in Section 11.1.
Double click on the choice of GUI executable and the GUI screen will appear as shown in Figure 18 for
SFRA_GUI or in Figure 19 for SFRA_GUI_MC. They look almost identical, the difference is in the pull
down menu under 'FRA Settings' starting with the label 'Open Loop'.
• In the SFRA_GUI, this pull down menu helps to select between Open Loop Model and Plant Model.
• In the SFRA_GUI_MC, this pull down menu helps to select between Open Loop Model and Closed
Loop Model.

NOTE: The GUIs interpretation of bandwidth is different.

• In the SFRA_GUI, bandwidth is defined as the open loop gain cross over frequency
• In SFRA_GUI_MC, bandwidth is defined according to Chinese standard GBT 16439-
2009 and NEMA ICS 16 (Speed Loop) for servo drives. It defines bandwidth as the
frequency where the closed loop output magnitude drops by 3dB or the phase shift lag
exceed 90 degrees for the speed loop. It is suggestive that bandwidth is the frequency
where the first of these two instances would occur. This approach is used to analyze
current loops as well in this demo.

This demo uses the GUI 'SFRA_GUI_MC'. However, the user is encouraged to experiment with the other
GUI as well to study the plant. With the SFRA_GUI, the user can plot the same graph as in
SFRA_GUI_MC by passing the argument 'SFRA_GUI_PLOT_GH_CL' in the function configureSFRA() as
shown in the code snippet below.
configureSFRA(SFRA_GUI_PLOT_GH_CL, ISR_FREQUENCY); // to plot GH and CL plots using SFRA_GUI

But the inferences from the plots are not according to that in SFRA_GUI_MC. Therefore, we advice to
configure SFRA for 'SFRA_GUI_PLOT_GH_H' so that the user can see open loop, closed loop and plant
model plots using these two GUIs, by using one at a time. For digital power applications, SFRA_GUI_MC
inferences may not apply and so SFRA_GUI can be used to display closed loop plots as well.

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Figure 18. SFRA GUI

Figure 19. SFRA GUI MC

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11.4 Setting Up the GUIs to Connect to Target Platform

Both GUIs have identical procedures to connect to the target platform. The GUI lets the user select
appropriate settings based on the target platform and development computer.
The following is a list of things to do on the GUI before starting the analysis.
1. Math Mode: Depending on the target C2000 development platform, either the fixed point or floating
point option is chosen. For F2837x or later C2000 MCUs, select the ‘Floating Point’ option
2. Since the USB port on the control card / launch pad is already connected to the computer for JTAG
purposes, no additional connection is required. However, for a standalone operation, an USB
connector needs to be connected to the target board. In the XDS100 emulator present on the control
card / launch pad, in addition to a JTAG link, an SCI port link is also provided and the GUI uses this
link to connect to the SCI port of the target platform. While the debug environment of CCS is using
JTAG, the GUI can also use SCI at the same time.
3. Click on the Setup button at the bottom right corner. This will pop open a Setup Connection window as
shown in Figure 20.

Figure 20. GUI Setup Diagram

4. Click ‘Refresh Comports’ button to get the Comport number show up in the window.
5. Select the Comport representing the connection to the target C2000 board.
6. Uncheck ‘Boot on Connect’
7. Click OK button

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8. This should establish the connection to the MCU control card/launchpad and the GUI will appear as
shown in Figure 21 indicating the connection status at the bottom left corner.

Figure 21. SFRA GUI Connected to the C2000 MCU

9. The frequency sweep related settings are shown in ‘FRA Settings’ Panel. These values are already
pre-filled from the C2000 device and they can be left as is.
10. As mentioned earlier, the visual difference between the two GUIs is in the pull down menu under 'FRA
Settings' starting with Open Loop.
a. In the SFRA_GUI, this pull down menu helps to select between Open Loop Model and Plant Model
b. In the SFRA_GUI_MC, this pull down menu helps to select between Open Loop Model and Closed
Loop Model
c. This menu becomes relevant after a complete noise injection sweep of the system at various
frequencies. Then the user can pick and view the plot of choice using this menu.
d. Bandwidth reporting is different as mentioned earlier. Gain cross over frequency is reported in the
open loop plot of the SFRA_GUI_MC instead of bandwidth as in SFRA_GUI.
This completes the initial setup of GUI environment.

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11.5 Running the SFRA GUIs

If the high voltage (HV) power input to the target platform is turned off before, restore it back now. From
the debug environment, the steps to be followed are as shown below:
1. Verify that sfraTestLoop is set to SFRA_TEST_D_AXIS so as to test Id loop.
2. Set FCL_params.wccD to the desired value, within limits, (when test is performed for Q axis, adjust
this parameter for Q axis - FCL_params.wccQ)
3. Set speedRef = 0.05 (in pu, 1 pu = 250Hz) and then set runMotor = MOTOR_RUN to run the motor.
Now motor shaft should start spinning and settle at the commanded speed.
4. The state machine variable (lsw) is auto-promoted in a sequence, its states are as follows:
a. lsw = QEP_ALIGNMENT --> lock the rotor of the motor
b. lsw = QEP_WAIT_FOR_INDEX --> motor in run mode and waiting for the first instance of QEP
index pulse
c. lsw = QEP_GOT_INDEX --> motor in run mode - QEP index pulse occurred
5. Now the GUI can be called into perform a frequency sweep of the D axis current loop by clicking on
the 'Start Sweep' button in the GUI. The sweep progress will be indicated by a green bar in the location
marked as ‘NO DATA’.
6. When the frequency sweep is fully done, it will compute the Bode plot and display the results as shown
in Figure 22 and Figure 23.
7. The GUI also computes and displays the loop bandwidth, gain margin and phase margin.
8. Repeat the test, if desired, by chaning FCL_params.wccD, and at different speed and load conditions.
9. To disconnect the GUI, click the 'Disconnect' button on the GUI.
10. To stop the motor, reduce the HV dc input voltage and set runMotor to MOTOR_STOP.
11. After the motor stops, take the controller out of real-time mode and reset.

Figure 22. SFRA Open Loop Bode Plots of the Current Loop Showing Magnitude and Phase Angle

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Figure 23. SFRA Closed Loop Bode Plots of the Current Loop Showing Magnitude and Phase Angle

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11.6 Influence of Current Feedback SNR

The fast current loop is a high bandwidth enabler. When the designed bandwidth is high, the loop gains
can also be high. This pretty much ties the loop performance to the quality of current feedback. If the SNR
of current feedback signal into the digital domain is poor, then the loop can be very audibly noisy as the
controller tries to minimise the error. If the noise is bothersome, the user may be required to reduce the
bandwidth to avoid the audible noise. Therefore, for a higher bandwidth and higher performance, the
feedbacks should be of higher SNR to get the frequency responses a shown in Figure 24 and Figure 25.

Figure 24. SFRA Open Loop Bode Plots of the Current Loop - Current Feedback With High SNR

Figure 25. SFRA Closed Loop Bode Plots of the Current Loop - Current Feedback With High SNR

NOTE: With the hardware platform IDDK, there is scope for improving the SNR of the current signal
feeding into the ADCs of the MCU. Therefore, higher bandwidth tests can be more noisier
(chattering in nature) on this platform.

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11.7 Inferences

11.7.1 Bandwidth Determination From Closed Loop Plot

The controller implemented for the open loop and closed loop plots shown in Figure 24 and Figure 25 is a
dead beat controller where the output catches up to the input in just one sample cycle without any
overshoots or requiring multiple cycles. From the closed loop plot, it is clear that the closed loop gain is
always 0dB (unity gain) at all frequencies and therefore, magnitude based bandwidth determination is not
practical. Hence, the phase plot is chosen as reference, and the frequency at which the phase lag goes
beyond 90 deg is taken as bandwidth per the Chinese standard GBT 16439-2009 or NEMA ICS 16 (speed
loop). In this test case, the PWM frequency is chosen as 10KHz and the sampling frequency is 20KHz and
the current loop bandwidth obtained from the closed loop plot is about 5000Hz per these guidelines.

11.7.2 Phase Margin Determination From Open Loop Plot

From the open loop plots, the phase margin obtained is about 65 degrees. Such a high margin should
give a very robust performance across the frequency ranges within the bandwidth obtained.

11.7.3 Maximum Modulation Index Determination From PWM Updtate Time

From Section 8.1, the time lapse between feedback sampling instantiation to PWM update is about 0.9 µs.
In this system where the PWM frequency is 10 KHz, the maximum modulation index is limited by the
sampling method as follows
• Double sampling - just above 96%
• Single sampling - just about 98%
This is quite comparable to FPGA based systems where the entire algorithm is implemented in hardware.

11.7.4 Voltage Decoupling in Current Loop

The SFRA test can be performed at zero speed (by rigidly locking the shaft if needed) to get one plot as
reference. The gain crossover frequency and phase margin at zero speed may be noted down. Then at
different speeds and load conditions, this test can be repeated to verify if there is any change in bandwidth
or phase margin. Any variation in the plot at different speed is indicative of the quality of decoupling in
current loops.

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11.8 Phase Margin vs Gain Crossover Frequency

By varying the control bandwidth and repeating these tests and noting down the resulting gain cross over
frequency and phase margin, a set of plots are obtained for Id loop as shown in Figure 26. Two sets of
tests are performed, one based on classical current control method, and the other based on FCL. Both
these tests were performed using different current regulators. They all gave converging results.

Figure 26. Plot of Gain Cross over Frequency vs Phase Margin as Experimentally Obtained

The group of plots at the bottom is obtained for conventional control, and it is obvious that the gain cross
over frequency is too low and that as the gain cross over frequency is increased, the phase margin drops
a lot faster.
The group of plots at the top is obtained with FCL. The gain cross over frequency is nearly thrice that of
the classical method for a given phase margin. And also, as the gain cross over frequency is increased,
the relative drop in phase margin is very low compared to the classical method. This effectively means
that FCL can provide a higher bandwidth or gain cross over frequency at a higher phase margin.

12 Incremental Build Level 7

This build level deals with setting up the EtherCAT slave in F2838x device to link up with TwinCAT master
in a PC. Among the three cores of F2838x MCU (two C28x™ CPU cores (CPU1/2) + one Arm® Cortex-
M4 core (CM)), the EtherCAT peripheral can be connected to CPU1 or M4. In the example here, M4 (also
called as connectivity manager (CM)) is chosen to interact with the EtherCAT peripheral, while the C28x™
core (CPU1) will perform all control functions for the servo drive. The setup procedure involves CPU1
setting up the GPIOs and clocking required for EtherCAT and then allocating the EtherCAT ownership to
the Connectivity Manager (CM). Then a dedicated code on CM is required to pass the data between the
EtherCAT slave and the CPU1 though inter processor communication peripheral (IPC). This is all taken
care of in FCL_LEVEL7.

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12.1 Run the Code on CPU1 to Allocate ECAT to CM

1. Open ’fcl_qep_f2838x_tmdxiddk_settings_cpu1.h’ and select level 7 incremental build option by setting
the BUILDLEVEL to FCL_LEVEL7 (#define BUILDLEVEL FCL_LEVEL7). Right-click on the project
name, and then click Rebuild Project.

NOTE: Control power supply to the IDDK is alone needed for this build level therefore the user may
turn off the high voltage dc power to the kit.

2. When the build is complete, click the Debug button, reset the CPU, restart, enable real-time mode, and
run.
3. Add the following variable in the ‘Expressions Window’:
a. countMainLoop : counter to just show activity in ECAT main loop function
b. ipcCMToCPUDataBuffer : data buffer written by CM for use by CPU1
c. ipcCPUToCMDataBuffer : data buffer written by CPU1 for use by CM
d. dataBufferFromCM : buffer copy of message from CM
e. dataBuffertoCM : buffer copy of messge to CM
4. Running the code will enable the GPIOs needed for EtherCAT and also passed over the ownership of
EtherCAT slave peripheral to CM, besides setting up the IPC on CPU1 side for data transfer between
CPU1 and CM. Now is the time to load / run the code on CM to initialize the EtherCAT peripheral.

NOTE: If ever the EtherCAT was assigned to CPU1 in any of the immediate previous evaluation
projects and is now being assigned to CM, then make sure to power cycle the controlCARD
before running the CM project to ensure that CPU1 has fully relinquished the EtherCAT
peripheral.

12.2 Run the Code on CM to Setup ECAT

The scope of the demo example is to emulate a debug panel for the servo drive using ECAT to feed
certain command settings and to retrieve the status of certain drive parameters. Therefore, the demo
example on CM is a precompiled demonstration of the EtherCAT slave stack code tweaked for this
application.

NOTE: Any modifications to the requirement given in demo will require the generation of new slave
stack files via the SSC tool and also corresponding changes to the application source code.
This will have to be rebuilt to get a new executable for loading into the CM.
The source files given by TI for EtherCAT support are only HAL files needed for this function
and will not be sufficient to compile and generate an executable. However, if the user
generates a slave stack, the CM project provided here will be able to generate an
executable.

Here are the steps to follow:

1. Ensure that CPU1 is actively running the project described in the previous section handing off the
EtherCAT ownership to CM
2. Besides USB connection between controlCARD and computer for JTAG purposes, connect an
Ethernet cable between controlCARD RJ45 Port 0 and computer
3. Run f2838x_connected_drive_ssc_file_and_demo.exe installer to extract the F2838x SSC
configuration, device system files required by the SSC tool and the demo executable that will run on
CM. These will be located in the newly created ssc_configuration directory.
4. From within the debug window, click on Cortex_M4, right click and select Connect Target. This will
facilitate downloading the M4 executable.
5. From within the CCS debug perspective, click Run --> Load --> Load Program and browse to the
executable fcl_qep_f2838x_ecat_cm.out available at
\solutions\tmdxiddk379d\f2838x\ssc_configuration\cm. This is extracted in step 3 above.

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6. Run the code. This would configure the ECAT slave controller and also the IPC on CM side for data
transfer between CM and CPU1.
Now the ECAT slave controller is ready to connect to ECAT master, and in this demo, the ECAT master is
TwinCAT running on the user's development computer.

12.3 Setup TwinCAT

The TwinCAT software turns almost any compatible PC into a real-time controller with a multi-PLC
system, NC axis control, programming environment and operating station. TwinCAT is a PC software
functioning as an EtherCAT master to control various EtherCAT slave nodes connected to the PC. Here
below are the steps to setup TwinCAT
1. Optional: Install Microsoft Visual Studio. This isn’t required since TwinCAT will install a Visual Studio
shell if no Visual Studio installation is found.
a. Download and install Microsoft Visual Studio
b. TwinCAT supports integration into Visual Studio 2010/2012/2013/2015/2017
2. Download and install TwinCAT3 from the Beckhoff
a. Follow the left sidebar to Download->Software->TwinCAT 3->TE1xxx | Engineering and select the
software product TwinCAT 3.1 eXtended Automation Engineering (XAE)
3. Once installation is complete, verify that the TwinCAT Runtime is active
a. Check that the TwinCAT Config Mode icon is shown in the Windows notification panel as shown in
Figure 28.

Figure 27. TwinCAT Config Mode Icon

b. Right click on this icon and select Tools->TwinCAT Switch Runtime. From the Tc- SwitchRuntime
window, verify that it is active. When active, it will only provide the option to Deactivate. Don’t
Deactivate!

Figure 28. TcSwitchRunTime Window Activated

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c. If the icon is not present, then locate the TwinCAT Runtime executable from the file system.
(Default installation location is typically: C:/TwinCAT/TcSwitchRuntime)
4. Start up Visual Studio with TwinCAT using one of the following methods:
a. Recommended: Right click the TwinCAT Config Mode icon from the Windows notification panel
and select TwinCAT XAE
b. installed desktop icon: TwinCAT XAE
c. Use installed Start Menu icon under Beckhoff folder: TwinCAT XAE
5. Once Visual Studio running, verify that the main toolbar has options TwinCAT and PLC shown. If these
aren’t present, then the TwinCAT Switch Runtime isn’t active.
6. Within Visual Studio, create a new EtherCAT project. Select File -> New -> Project and under
templates select TwinCAT Projects then TwinCAT XAE Project (XML format). Fill in a name (say
f2838x_iddk) and click OK.
7. Now that the project is created, verify that a realtime Ethernet adapter is installed.
a. In Visual Studio, select the TwinCAT menu from the main toolbar and select Show Realtime
Ethernet Compatible Devices
b. In the popup window, under Installed and ready to use devices (realtime capable) category, if no
connections are shown, select one from the list of Compatible devices and click Install.
8. TwinCAT setup is now complete.

12.4 Scanning for EtherCAT Devices via TwinCAT

Here below are the steps to scan EtherCAT devices via TwinCAT.
1. Open the TwinCAT project created in Section 12.3 (f2838x_iddk)
2. Verify that the controlCARD is running the demo code (CM running fcl_qep_f2838x_ecat_cm.out) as
described in Section 12.2 and that the development computer (running TwinCAT) is connected via an
Ethernet cable to port 0 connection in controlCARD.

NOTE: Port 0 is the top Ethernet port on the side of the controlCARD with two Ethernet connections.

3. In Visual Studio on the left side solution explorer, expand the Project, then expand I/O
4. Right click on Devices and select Scan
a. A dialog will popup stating that Not all types of devices can be found automatically. Click OK.
5. Once scanning is complete, a popup window will appear. The following options may appear:
a. A popup stating that 1 new I/O devices found where the device is Device 2 (EtherCAT Automation
Protocol). This or any other device numbers besides Device 1 is correct, click OK.
b. A popup stating that no devices have been found or stating that 1 new I/O devices found where the
device is Device 1 (EtherCAT Automation Protocol). This means some setup is incorrect. Verify
that the example is running on the device (or at least has gone through the GPIO setup and reset
of the EtherCAT IP). If the procedure is followed correctly, it should have identified Device 2. The
setup procedure may be repeated again carefully.
6. After clicking OK, another popup will ask to Scan for boxes. Click Yes.
7. After clicking Yes, another popup will ask to Activate Free Run. Click Yes.
8. In the solution explorer on the left, under devices you should see Device 2 (EtherCAT). Under that,
there will be a Box #. This Box is the controlCARD ESC.
9. The EtherCAT master communication is now setup with the slave device.

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Figure 29. TwinCAT Solution Explorer

12.5 Program ControlCard EEPROM for ESC

Verify first that TwinCAT has discovered the ESC as described in Section 12.4. Also, make sure to copy
the ESC XML file into TwinCAT directory before starting off to program the EEPROM.
1. Copy the ESI file (F2838x CM EtherCAT Slave (System).xml available at
\solutions\tmdxiddk379d\f2838x\ssc_configuration) into the TwinCAT directory (Default location:
C:\TwinCAT\3.1\Config\Io\EtherCAT). If TwinCAT was already open, it has to be closed and re-opened
again for it to see new XML file(s).
2. In the Visual Studio solution explorer, double click on Box # under Device 2 (EtherCAT).
3. The TwinCAT project window should be open to the right of the solution explorer and have some tabs
such as General, EtherCAT, and so forth
4. Select the EtherCAT tab and then click on Advanced Settings
5. In the new window, expand the ESC Access menu, then expand the E2PROM menu. Click on Smart
View
6. Click on Write E2PROM and expand the Texas Instruments Incorporated menu within the Available
EEPROM Descriptions window.
7. Expand TI C28xx Slave Devices and select F2838x CM EtherCAT Slave. Click OK.
8. Visual Studio will indicate that the EEPROM is being programmed. When it completes, if the Smart
View doesn’t automatically update with the new contents, you can select Read E2PROM to read back
the newly programmed values.
9. The Product Code for this CM application is 0x10003101
10. Once EEPROM is programmed, disconnect and power cycle the controller.

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Figure 30. TwinCAT EEPROM Window

12.6 Running the Application

This section deals with running the application.
1. Verify/ restore the connections if disconnected before.
2. Reload CPU1 and CM applications
3. Run CPU1 first and hand-off the EtherCAT peripheral to CM
4. Run the CM next to setup the EtherCAT connection with master and IPC link with CPU1
5. From TwinCAT window, rescan for devices, and restart TwinCAT in config mode.

Figure 31. TwinCAT Restart in Config Mode Icon

6. To observe the ECAT messages as variables in CCS, right-click within the CCS Expressions window
and choose Import. Then browse to and select fcl_f2838x_tmdxiddk_ecat_vars.txt file from the debug
directory.

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7. Within TwinCAT, double-click on the discovered EtherCAT box and observe that the EtherCAT slave is
running in OP mode.

Figure 32. EtherCAT Slave in OP Mode

8. Within TwinCAT, expand the explorer to the EtherCAT box (I/O --> Devices -->Device 2 (EtherCAT) -->
Box 1 (F2838x CM EtherCAT Slave(SYSTEM))) and find the various output/input mappings as shown
in Figure 33. Double click on Box1 to get the F2838x CM slave input /output data window as shown in
Figure 34.
a. Select Input mapping 0 to view all the status feedback from the drive. The following are the drive
parameters monitored through EtherCAT
a. SpeedStatus
b. PositionStatus
c. TorqueStatus
d. DriveStatus
b. Select Output mapping 0 to view and enter all the commands to the drive
a. DriveCommand
b. SpeedReference
c. PositionReference

Figure 33. TwinCAT Solution Explorer Inputs and Outputs

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Figure 34. F2838x CM EtherCAT Slave (SYSTEM) Input/Output Data

9. This build level is a loop back example to verify the EtherCAT functionality. So, if the command data
entered in a certain output mapping variable is returned back in a certain input mapping variable, it
confirms the functionality of EtherCAT slave on the F2838x. The loop back association is as follows:
a. SpeedReference --> SpeedStatus
b. PositionReference --> PositionStatus
c. DriveCommand --> DriveStatus
For example, the data entered in 'SpeedReference' in output mapping should return back to show up in
'SpeedStatus' in input mapping if EtherCAT slave is functioning properly.

13 Incremental Build Level 8

Assuming the previous build level is successfully completed, this build level attempts to control the drive
by feeding in commands from the TwinCAT window and monitoring the status feedback from the drive
using the same through ECAT.

13.1 Run the Code on CPU1 to Allocate ECAT to CM

1. Open ’fcl_qep_f2838x_tmdxiddk_settings_cpu1.h’ and select level 8 incremental build option by setting
the BUILDLEVEL to FCL_LEVEL8 (#define BUILDLEVEL FCL_LEVEL8). Right-click on the project
name, and then click Rebuild Project.
2. When the build is complete, click the Debug button, reset the CPU, restart, enable real-time mode, and
run.

NOTE: Since this build level attempts to drive the motor, high voltage dc power to the kit should be
restored at this point.

3. CPU1 should have given the ownership of ECAT to CM

4. CPU1 would be waiting to receive commands from CM through IPC channel.

13.2 Run the Code on CM to Setup ECAT

This build level uses the same precompiled executable of CM that is used in the previous build level.
Here, CM is used as a conduit to pass information between TwinCAT and drive controller.

NOTE: Any modifications to the requirement given in demo will require the generation of new slave
stack files via the SSC tool and also corresponding changes to the application source code.
This will have to be rebuilt to get a new executable for loading into the CM.

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Here are the steps to follow:

1. Ensure that CPU1 is actively running the project (described in Section 13.1) handing off the EtherCAT
ownership to CM
2. Besides USB connection between controlCARD and computer for JTAG purposes, connect an
Ethernet cable between controlCARD RJ45 Port 0 and computer
3. From within the CCS debug perspective, click Run --> Load --> Load Program and browse to the
executable fcl_qep_f2838x_ecat_cm.out available at \solutions\tmdxiddk379d\f2838x\ccs\sensored_foc
4. Run the code. This will configure the ECAT slave controller and the IPC on CM side for data transfer
between CM and CPU1.
Now the ECAT slave controller is ready to connect to ECAT master, which is the TwinCAT running on
user's development computer.

13.3 Running the Application

1. Follow the same procedure given in Section 12.4 to bring up the TwinCAT and to scan the EtherCAT
devices connected to it.
2. Follow the same procedure given in Section 12.6 to interact with the drive to feed in command
references and to get the status back.
3. Unlike the previous build level, here the commands received by the controller are not looped back and
are used to actually set the operational mode or references for the drive. The operational status of the
drive is sent back via IPC --> CM --> TwinCAT.
4. The output mapping in TwinCAT sets the commands and references for the drive while the input
mapping reveals the operating status of the drive.
5. Under output mapping, 'DriveCommand' sets three different operating modes. It can take a value of 0,
1 or 2 and its significance is as follows
a. 0 - STOP motor
b. 1 - RUN the motor in SPEED mode --> outer loop is speed loop (as in BUILDLEVEL 4).
'SpeedReference' under output mapping will act as the speed reference setting for this mode
c. 2 - RUN the motor in POSITION mode --> outer loop is position loop (as in BUILDLEVEL 5).
'PositionReference' under output mapping will act as the position reference setting for this mode
d. any other value --> defaults to STOP motor
6. 'SpeedReference' and 'PositionReference' take values in a 1000 point scale (between 0 and +/-1000)
as command. Values outside this range will be clamped in control side software (CPU1) to fit within
range in the drive controller. These are then converted into per unit by CPU1, which is the default
format used by the control software.
7. As the motor runs, it reports the speed feedback in speed mode and position feedback in position
mode. Try varying the drive commands by editing the parameters under output mapping, and see the
drive response in input mapping. Position feedback will always be given as a positive number within 0
and 1000. For example, if 'PositionReference' is given as -200, the feedback 'PositionStatus' will
display a value close to 800. In angular terms, they represent the same position.

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