Tempus Text Command Reference Timing Analysis Commands Warning clock_clipping_gate clock_clipping_frea clock_erossing May 2017 Description Warning : Clock clipping possible due to wrong gate type or wrong trigger for data input. Warning : Clock clipping possible due to incompatible clock signal and data signal frequencies. Warning : Clock domains interact ‘Comments: Checks clock interactions between multiple clock domains in the design. When you specify this parameter, the Timing Check Crossing Clocks report shows the interaction of clocks in the design and indicates whether the paths between the clocks are False or Partial False. Ita clock launches one or more paths, which are captured by other clocks, the report lists all pairs of crossing clocks. © This includes inferred clock gating with different reference and signal clock. © Ifa path has been disabled using the set_disable_timing command, crossing clocks on that path are not reported. Ifall the paths between two clocks are false paths or they are exclusive/asynchronous clocks, the path is marked as False . The false path can be defined on clocks, for example, se:_false_path -clock_to CLK or on pins or ports, such as, rough buf1/Y. Ifonly part of paths are set as false paths or exclusive/asynchronous clocks, the path is marked as partial False. Tat Product Version 17.1Tempus Text Command Reference Timing Analysis Commands clock_gating_controlling_edge_unknown May 2017 © Ifa false path is defined only for one check type (say, setup), the crossing clocks are marked as Partial ¥alse if the simultaneous setup hold mode is set to on . The crossing clocks are marked raise if the analysis type is setup and the simultaneous setup hold mode is set to of¢ © Ionly one edge (risefall) of a particular clock pair has false paths (say, using -clock_fa11), then the path is marked as a Partial False. Warning: Clock not found where clock is expected Comments: Indicates that no clock signal is defined at the clock pin. See create_clock . Warning: Unknown controlling edge to perform clock gating check. Comments: Reports library cells with complex functions (MUX or AOI) where controlling edge of signal to perform clock gating check cannot be determined automatically. You need to specify correct edge by -high / -1ow option using the set_clock_gat.ing_check command to resolve such warning. Note: The software does not report this warning when either: © set. applied on such pins, or |isable_clock_gatin g_check command is ® global settings to disable clock gating checks are on. 732 Product Version 17.1Tempus Text Command Reference Timing Analysis Commands clock_gating_no_data Warning: No data signal reaching clock gating enable pin Comments: Reports clock gating enable pins where no valid data signal arrives. You need to do either of the following: © specify valid data signal to reach enable pin of clock gating cells, or © remove any path exceptions or disabled checks that blocks valid data signal to reach enable pin Note: The software does not report this warning when either © set_disable_clock_gatin ¢_check is applied on such pins, or © global settings to disable clock gating checks are on. clocks_masked_py_another_clock Warning: Clock(s) in fanin cone are dropped due to another clock Comments: Reported timing pins on which creation of a regular or a generated clock causes clock(s) in fanins of such pins have been blocked or masked from propagating further. However, for pins having only master clock waveform on the fanin, this warning is not reported, You can use the detailed mode ( -verbose option) to report names of all the incoming clock waveforms that have been blocked. May 2017 733 Product Version 17.1Tempus Text Command Reference Timing Analysis Commands clock missing_at_sequential_output propagated constant_clock_pin const_collision data_check_multiple_reference_signal May 2017 Warning: Found latency phase at sequential output on clock tree instead of clock phase Comments: Reports output pins of sequential elements that lie on source clock tree for the generated clocks created downstream and do not have any valid clock phase. This indicates possible missing clock related checks (e.g., clock gating) on downstream clock tree You can add clocks on this pin or downstream clock tree only if no valid clock exists until downstream generated clock creation point. Warning: Clock not propagated Comments: Reports ideal clocks reaching the reference pin of a timing check. Warning: Clock missing due to constant. Comments: Reports clock pins with constant values. Any constants (from SDC/Verilog ) at register clock pins will be reported. Warning: Constant collision Comments: See set_case_analysis . Warning: Multiple clocked signals are reaching data check reference pin Comments: Reports on reference pins for non sequential timing check (data check) where more than one reference data arrives. 734 Product Version 17.1Tempus Text Command Reference Timing Analysis Commands data_check_no_reference_signal ideal_clock_waveform inval id_pl1_configuration latch_fanow loop May 2017 Warning: No clocked signal is reaching data check reference pin Comments: Reports reference pins for non- sequential timing check (data check) where no valid reference signal (data phase) arrives. You can do one of the following to resolve such warnings: * add valid reference signals to reach at such reference pins © remove path exceptions or disabled arcs that are blocking such reference signals Warning: Clock waveform is ideal Comments: Reports clocks that are ideal and are not propagated. This warning type is reported by default (unless -exciude_warning OF ~check_only parameter is specified). You can use the set_propagated_clock command to avoid this waming. Warning: No valid path exists from output pin to feedback pin of PLL Comments : Shows PLL (phase locked loop) check warnings. These checks allow you to identify and fix, issues in the PLL flow. Warning : Latch and its fanout latch work on same. clock. Comments : Checks for a latch and its fanout latch(es) that works on the same clock. Warning: Timing loop found in the design Comments: Indicates that there are timing loops in the design. It also includes loops caused by generated clocks. 738 Product Version 17.1Tempus Text Command Reference Timing Analysis Commands master_clk_edge_not_reaching partial_input_delay pulse_non-pulse_clock_merge maltiple_clock no_input_delay May 2017 Warning: Master clock edge does not reach the generated clock target. Comments: This warning means that rise/fall latency edge is not reaching to create generated clock root from the master clock. You can verify if the path thatis seeing this warning is actually broken, or edge is somewhere disabled earlier on this path. There is a global timing_enable_genclk_edge_based_source_latency that controls how the software chooses generated clock source latency paths. Details of this global can be found at Tempus text command reference. Warning: Indicates that a rise or fall input delay assertion is not applied Warning : Merge of pulse and non-pulse clock paths. Comments : Reports points where a pulse clock and a non-pulse clock merges. Warning: Missing specific (rise/fall) drive constraint Comments: Either a rise or fall drive constraint is applied and the other one is missing. Warning: Multiple clocks are reaching clock reference pin.. Comments: Reports clock pins of sequential or clock gating cells where more than one clock waveform arrives. This warning is for information only and the software performs timing analysis with respect to all such clocks. Warning: No input delay assertion with or without - clock option specified. Comments: See set_inpul_delay . 736 Product Version 17.1no_drive no_gen_clock_source signal_tevel uncons_endpoint Examples Here are some examples. Tempus Text Command Reference Timing Analysis Commands Warning: No drive constraint Comments: See set_driving_cell and set_drive. Warning: No clock source found for generated clock ‘Comments: Indicates that the source pin of the clock generated by the create_clock command is not driven by a clock source. Warning: Driver pin voltage value do not match with sink pin voltage level Comments: Reports net driver/receiver pin pairs for which the pin voltage does not match. Warning: No constrained signal reaching pin. Comments: For output ports: Primary output port has no implicit timing check. Use set_output_delay , set_max_delay , or set_min_delay to create a valid constraint. For register data pins: There is no valid clock reaching the CK pin of the register data pin. Check for missing create_clock for the clock network. The endpoints are reported as unconstrained in both in early and late timing. This does not cover all the cases and scenarios because of which endpoints can become unconstrained. To cover all possible cases, you can use the alysis_coverage command. * Consider the following example: buf buf2 May 2017 rar Product Version 17.1Tempus Text Command Reference Timing Analysis Commands The Timing Check Crossing Clocks reports False or Partial False in some of the scenarios given below: 2) set_iaput_delay with respect to CLK1 on in and set_output_delay with respect to CLK2 on out: From Clock Crossing Clocks cLKL cuK2 b) sct_input_delay with respect to CLK1 on in, set_output_delay with respect to CLK2 on out, and set_false_path -to CLK2 (clock-based false path) From Clock Crossing Clocks cuKi cLK2 (False) ¢) Ifthe set_false_path becomes set_false_path -rise_to CLK2, the following is reported: From Clock crossing Clocks cLKL cuK2 (P ial False) The following command displays the default summary report: tempus> check_timing TIMING CHECK SUMMARY Warning Warning Description Number of Warnings May 2017 738 Product Version 17.1Tempus Text Command Reference Timing Analysis Commands ideal_clock waveform Clock waveform is ideal 1 clock_expected Clock not found where clock is expected 3 naster_clk_¢ Master clock edge does not reach the generated clock target 2 No drive assertion 8 No input delay assertion with respect to clock 4 uncons_enépoint Unconstrained signal arriving at end point 5 © The following command displays a specified type of waming using the -type option if a timing loop is found in the design: tempus> check_timing -type loops MING CHECK SUMMARY Warning ng Description Number of Warnings oop Timing loop found in the design 0 © The following command provides more information about problems and prints a summary using the -verbose option: tempus> check_timing -verbose ¢ CHECK SUMMARY Warning Warning Description Number of Warnings May 2017 739 Product Version 17.1Tempus Text Command Reference Timing Analysis Commands deal_clock_waveform Clock waveform is ideal clock_expected Clock not found where clock is expected 3 master_clk_edge_not_reaching Master clock edge does not reach the generated clock targ 2 no_drive No drive assertion 8 no_input_delay No input delay assertion with respect to clock 4 uncons_endpoint Unconstrained signal arriving at end point 5 PIMING CHECK DETAIL Pin Warning 098 /CK Clock not found where clock is expected u8/CK Clock not found where clock is expected u8/CX Clock not found where clock is expected 08/0 Master clock edge does not reach the target for generated clock GCLK4 cuxi No drive assertion inl No drive assertion inl No input delay assertion with respect to clock out Unconstrained signal arriving at end point ‘TIMING CHECK IDEAL CLOCKS Clock Waveform May 2017 740 Product Version 17.1