ENGIN 112
Intro to Electrical and Computer Engineering
Lecture 28
Timing Analysis
ENGIN112 L28: Timing Analysis November 7, 2003
Overview
° Circuits do not respond instantaneously to input
changes
° Predictable delay in transferring inputs to outputs
• Propagation delay
° Sequential circuits require a periodic clock
° Goal: analyze clock circuit to determine maximum
clock frequency
• Requires analysis of paths from flip-flop outputs to flip-flop inputs
° Even after inputs change, output signal of circuit
maintains original output for short time
• Contamination delay
ENGIN112 L28: Timing Analysis November 7, 2003
Sequential Circuits
° Sequential circuits can contain both combinational
logic and edge-triggered flip flops
° A clock signal determines when data is stored in flip
flops
° Goal: How fast can the circuit operate?
• Minimum clock period: Tmin
• Maximum clock frequency: fmax
° Maximum clock frequency is the inverse of the
minimum clock period
• 1/Tmin = fmax Clock
Period
Clock
ENGIN112 L28: Timing Analysis November 7, 2003
Combinational Logic Timing: Inverter
A Y Y
t cd
t pd
° Combinational logic is made from electronic circuits
• An input change takes time to propagate to the output
° The output remains unchanged for a time period
equal to the contamination delay, tcd
° The new output value is guaranteed to valid after a
time period equal to the propagation delay, tpd
ENGIN112 L28: Timing Analysis November 7, 2003
Combinational Logic Timing: XNOR Gate
A
A
B C
B
C
t cd
t pd
° The output is guaranteed to be stable with old
value until the contamination delay
• Unknown values shown in waveforms as Xs
° The output is guaranteed to be stable with the new
value after the propagation delay
ENGIN112 L28: Timing Analysis November 7, 2003
Combinational Logic Timing: complex circuits
Tpd = 2ns
Tcd = 1ns
Circuit X
Tpd = 3ns
Tcd = 1ns
A
C A
Circuit X C
B
Tpd = 5ns
B Tcd = 1ns
° Propagation delays are additive
• Locate the longest combination of tpd
° Contamination delays may not be additive
• Locate the shortest path of tcd
° Find propagation and contamination delay of new,
combined circuit
ENGIN112 L28: Timing Analysis November 7, 2003
Clocked Device: Contamination and Propagation Delay
D Q
D
Clk
Q
tcd
tClk-Q
° Timing parameters for clocked devices are specified
in relation to the clock input (rising edge)
° Output unchanged for a time period equal to the
contamination delay, tcd after the rising clock edge
° New output guaranteed valid after time equal to
the propagation delay, tClk-Q
• Follows rising clock edge
ENGIN112 L28: Timing Analysis November 7, 2003
Clocked Devices: Setup and Hold Times
ts th
D Q
D
Clk
° Timing parameters for clocked devices are specified
in relation to the clock input (rising edge)
° D input must be valid at least ts (setup time) before
the rising clock edge
° D input must be held steady th (hold time) after
rising clock edge
° Setup and hold are input restrictions
• Failure to meet restrictions causes circuit to operate incorrectly
ENGIN112 L28: Timing Analysis November 7, 2003
Edge-Triggered Flip Flop Timing
CLK
th = hold time
ts = setup time
° The logic driving the flip flop must ensure that
setup and hold are met
° Timing values (tcd tpd tClk-Q ts th)
ENGIN112 L28: Timing Analysis November 7, 2003
Analyzing Sequential Circuits
TClk-Q = 5ns Tpd = 5ns TClk-Q = 5 ns
Ts = 2 ns
D X Y
Comb.
D Q D Q Z
Logic
FFA FFB
G
CLK
° What is the minimum time between rising clock
edges?
• Tmin = TCLK-Q (FFA) + Tpd (G) + Ts (FFB)
° Trace propagation delays from FFA to FFB
° Draw the waveforms! Fmax = _______
ENGIN112 L28: Timing Analysis November 7, 2003
Analyzing Sequential Circuits
Tpd = 4ns
Comb.
Logic F
X Y
Comb.
D Q D Q Z
Logic H
FFA FFB
Tpd = 5ns
CLK
TClk-Q = 5ns
TClk-Q = 4 ns
Ts = 2 ns
° What is the minimum clock period (Tmin) of this
circuit? Hint: evaluate all FF to FF paths
° Maximum clock frequency is 1/T min
ENGIN112 L28: Timing Analysis November 7, 2003
Analyzing Sequential Circuits
Tpd = 4ns
Comb.
Fmax = _______ Logic F
X Y
Comb.
D Q D Q Z
Logic H
FFA FFB
Tpd = 5ns
CLK
TClk-Q = 5ns
TClk-Q = 4 ns
Ts = 2 ns
° Path FFA to FFB
• TClk-Q(FFA) + Tpd(H) + Ts(FFB) = 5ns + 5ns + 2ns = 12ns
° Path FFB to FFB
• TCLK-Q(FFB) + Tpd(F) + Tpd(H) + Ts(FFB) = 4ns + 4ns + 5ns + 2ns
ENGIN112 L28: Timing Analysis November 7, 2003
Analyzing Sequential Circuits: Hold Time Violation
Tcd = 1ns Tcd = 2ns Th = 2 ns
D X Y
Comb.
D Q D Q Z
Logic
FFA FFB
G
CLK
° One more issue: make sure Y remains stable for hold
time (Th) after rising clock edge
° Remember: contamination delay ensures signal
doesn’t change
° How long before first change arrives at Y?
• Tcd(FFA) + Tcd(G) >= Th
• 1ns + 2ns > 2ns
ENGIN112 L28: Timing Analysis November 7, 2003
Analyzing Sequential Circuits: Hold Time Violations
Tcd = 1ns
All paths must satisfy requirements
Comb.
Logic F
X Y
Comb.
D Q D Q Z
Logic H
FFA FFB
Tcd = 2ns
CLK
TClD = 1ns
TClD = 1 ns
Th = 2 ns
° Path FFA to FFB
• TCD(FFA) + TCD(H) > Th(FFB) = 1 ns + 2ns > 2ns
° Path FFB to FFB
• TCD(FFB) + TCD(F) + TCd(H) > Th(FFB) = 1ns + 1ns + 2ns > 2ns
ENGIN112 L28: Timing Analysis November 7, 2003
Summary
° Maximum clock frequency is a fundamental parameter
in sequential computer systems
° Possible to determined clock frequency from
propagation delays and setup time
° The longest path determines the clock frequenct
° All flip-flop to flip-flop paths must be checked
° Hold time are satisfied by examining contamination
delays
° The shortest contamination delay path determines if
hold times are met
° Check handout for more details and examples.
ENGIN112 L28: Timing Analysis November 7, 2003
