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EXPERIMENT 8 Verilog

The document describes an experiment to implement 2-bit, 4-bit, and 8-bit comparators in Verilog. It includes the logic equations and circuits for 2-bit and 4-bit comparators. Verilog code was written for each comparator and their designs were simulated and tested. Results including waveform simulations, RTL schematics, technology schematics, and area reports are presented for each comparator. The document concludes that Verilog code was successfully implemented for 2-bit, 4-bit, and 8-bit comparators and their simulations were tested.

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58 views6 pages

EXPERIMENT 8 Verilog

The document describes an experiment to implement 2-bit, 4-bit, and 8-bit comparators in Verilog. It includes the logic equations and circuits for 2-bit and 4-bit comparators. Verilog code was written for each comparator and their designs were simulated and tested. Results including waveform simulations, RTL schematics, technology schematics, and area reports are presented for each comparator. The document concludes that Verilog code was successfully implemented for 2-bit, 4-bit, and 8-bit comparators and their simulations were tested.

Uploaded by

uday
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT 8

Aim: Verilog Implementation of 2-bit, 4-bit 8-bit comparators


Important Concept/ Theory:
A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers in order
to find out whether one binary number is equal, less than or greater than the other binary number. We logically
design a circuit for which we will have two inputs one for A and other for B and have three output terminals,
one for A > B condition, one for A = B condition and one for A < B condition.

2-bit Comparator:

Logical Equations:
A>B:A1B1’ + A0B1’B0’ + A1A0B0’
Fig.1: Logic Circuit of 2-bit Comparator A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 +
Table 1: Truth Table for 2-bit Comparator A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 +
A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A<B:A1’B1 + A0’B1B0 + A1’A0’B0

4-bit Comparator:

Logic Equation:

Fig.2: Logic Circuit of 4-bit Comparator


Table 2: Truth Table for 4-bit Comparator

Design Analysis:
Codes:
1. 2-bit Comparator:

2. 4-bit Comparator:
3. 8-bit Comparator:

Results/Discussions:
Simulation (Waveforms)
1. 2-bit Comparator:

2. 4-bit Comparator:

3. 8-bit Comparator:
RTL Schematic:
1. 2-bit Comparator:

2. 4-bit Comparator:

3. 8-bit Comparator:

Tech Schematic:
1. 2-bit Comparator:

2. 4-bit Comparator:
3. 8-bit Comparator:

Area Report:
1. 2-bit Comparator:

2. 4-bit Comparator:
3. 8-bit Comparator:

Conclusion:
Verilog HDL code for 2-bit, 4-bit & 8-bit comparator has been implemented and their
simulation with signals has been tested.
Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6

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