IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO.

10, OCTOBER 2016 2435

A 106 nW 10 b 80 kS/s SAR ADC With Duty-Cycled

Reference Generation in 65 nm CMOS
Maoqiang Liu, Student Member, IEEE, Kevin Pelzers, Rainier van Dommele,
Arthur van Roermund, Senior Member, IEEE, and Pieter Harpe, Senior Member, IEEE

Abstract— This paper presents a 10 b 80 kS/s SAR ADC a stable, well-defined reference voltage with good PSRR.
with low-power duty-cycled reference generation. It generates However, most existing low-power RVGs consume a power in
a stable reference voltage on chip for the SAR ADC and imparts the order of 32–200 nW [6]–[9], which is beyond the power
very good immunity against power supply interference to the
ADC. A 0.62 V-VDD 25 nW CMOS reference voltage generator needed for a power-efficient low-speed SAR ADC. Thus, this
(RVG) is presented, which has only ±1.5% variation over process work introduces a duty-cycled RVG integrated with a low-
corners. A duty-cycling technique is applied to enable 10% duty- power SAR ADC to obtain an overall solution that is power-
cycling of the RVG, resulting in negligible power consumption efficient and accurate, independent of the external supply [10].
of the RVG compared to that of the ADC. Furthermore, a bi- In terms of RVGs, bandgap reference (BGR) circuits are
directional dynamic preamplifier is adopted in the SAR ADC,
which consumes about half the power compared with a regular favorable for reference generation thanks to their high accu-
dynamic structure and maintains noise and gain performance. racy over process corners as the output reference voltage
Compared with prior-art low-power ADCs, this work is the first is determined by the bandgap voltage of silicon. For the
to integrate the reference generation and include it in the power conventional BGR [11], the output voltage is about 1.2 V and
consumption while maintaining a competitive 2.4 fJ/conversion- the power supply needs to be higher than 1.4 V, which makes
step FoM. The chip is fabricated in 65 nm CMOS technology.
this BGR impossible for low-VDD (< 1 V) applications.
Index Terms— CMOS, duty-cycle, dynamic comparator, Several BGRs [6]–[8] are developed to operate at sub-1 V
reference voltage generator, SAR ADC. VDD, and their power consumption could be as low as 32 nW.
As an alternative to BGRs, CMOS RVGs can more easily
I. I NTRODUCTION achieve sub-1 V VDD and low power operation. However, the
output reference voltage of many CMOS RVGs [9], [12] highly
A UTONOMOUS wireless sensor networks have been a
prevailing research topic during the past few years.
A wide range of promising applications could be realized
depends on the absolute value of the MOSFET threshold
voltage, which is sensitive to process variations. Though [13]
based on these networks in areas like health care, security, claims that a DTMOST-based RVG could reduce this depen-
logistics and so on. In these sensor networks, low-power, dency by a factor of two, this advantage may become smaller
low-speed, moderate-resolution ADCs are usually needed with technology scaling as the back-gate tends to have less
to digitize the sensed signals. State-of-the-art SAR ADCs impact on the MOSFETs depletion region.
can accomplish this goal with very good power-efficiency This paper presents a low-power low-VDD CMOS RVG
(<10 fJ/conversion-step) [1]–[5]. At the same time, the ref- based on the threshold voltage difference between normal- and
erence voltage is very important for precise digitization of high-Vt transistors, which is easier to control [14] compared
sensor information, but this aspect is usually ignored in low- with the absolute threshold voltage, thus leading to a more
power ADC publications where the VDD is typically used accurate reference over process corners.
as reference. However, as the VDD is usually provided by The power consumption of an ADC scales down with its
a battery or energy harvesting, this results in an unstable sampling frequency, but the power consumption of an RVG is
reference. In addition, the ADC faces a lot of crosstalk noise static, which may be comparable or higher than that of a low-
from other circuit blocks through this shared VDD. Another speed ADC. In order to reduce the RVG power consumption, a
solution for creating a reference voltage is to integrate a duty-cycling technique using a 3-stage S&H is applied, which
reference voltage generator (RVG) on chip. It can provide overcomes the slow start-up of the RVG and achieves 10%
duty-cycling.
Manuscript received January 18, 2016; revised April 22, 2016; accepted For low-speed SAR ADCs, the power consumption of the
June 23, 2016. Date of publication July 28, 2016; date of current version
September 30, 2016. This paper was approved by Guest Editor Aaron DAC and the comparator dominates the total power consump-
Buchwald. tion. The SAR ADC in this work adopts very small unit capac-
The authors are with the Department of Mixed-signal Microelec- itors (250 aF) to save DAC power. Further, a bi-directional
tronics, Eindhoven University of Technology, Eindhoven University
of Technology, De Zaale, Eindhoven, The Netherlands (e-mail: dynamic comparator makes use of both charging and discharg-
[email protected]; [email protected]; [email protected]; ing phases to perform amplification so that about half of the
[email protected]; [email protected]). preamplifier power is saved.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. This paper is organized as follows. Section II explains
Digital Object Identifier 10.1109/JSSC.2016.2587688 the architecture of the SAR ADC with duty-cycled reference
1558-173X © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2436 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

Fig. 1. Architecture of the SAR ADC with reference generation.

generation. Section III describes the details of the CMOS

RVG. In Section IV, the duty-cycling technique is introduced.
Section V shows the design of the LDO regulator driving the
SAR ADC. The 10 b SAR ADC is depicted in Section VI,
including the bi-directional comparator. Measurement results Fig. 2. Simulated variation of Vt,nvt , Vt,DTMOS and (Vt,hvt – Vt,nvt )
of both the stand-alone RVG and the SAR ADC with duty- in 3 process corners.
cycled RVG are shown in Section VII, and Section VIII
concludes this paper.
the bandgap voltage of silicon. For CMOS design, an obvious
II. SAR ADC A RCHITECTURE W ITH D UTY-C YCLED voltage unit is the threshold voltage, which can be expressed
R EFERENCE G ENERATION as follows for a normal-Vt NMOS:
QSS |Qd |
In order to meet the ADC requirements in wireless sensor Vt,nvt = VFB − + 2 |P | + (1)
networks, a moderate resolution (10 b), low-speed (80 kHz) COX COX
SAR ADC is developed that operates at a minimum VDD where Vt,nvt is the threshold voltage of a normal-Vt NMOS,
of 0.6 V to save power. For an SAR ADC with reference VFB is the flat-band voltage, QSS is the surface charge per
generation, besides the RVG, an LDO is also needed to drive unit area, COX is the gate-oxide capacitance, 2|P | is the
the SAR ADC. Due to the inevitable LDO dropout, which is voltage required for strong conversion, and Qd is the charge
in practice at least 200 mV, the power supply of the system is per unit area in the inversion layer [14]. In (1), every term
set to 0.8 V for the sake of low-power operation, requiring the is process-dependent, leading to a process-sensitive threshold
RVG to operate at this low power supply while producing a voltage. As shown in Fig. 2, at three corners (typical, slow,
controlled 0.6 V output voltage. For the consideration of power fast), the simulated process variation divided by the average
consumption, it is reasonable that the power consumption of value is calculated to evaluate the effect of process variations
the supporting blocks (RVG and LDO) is smaller than that of for various transistor sizes. The Vt,nvt varies about 15% in
the main function (ADC). Thus, low-power low-VDD RVG this particular 65 nm CMOS technology. For most CMOS
and LDO blocks are required in this integrated system. RVG publications based on the absolute threshold voltage,
The SAR ADC with reference generation is shown in Fig. 1. measurements of multiple samples reveal smaller variation as
It comprises an RVG, a 3-stage S&H for duty-cycling, an LDO those samples usually come from the same die and have the
and a SAR ADC. The system operates at one single external same process corner. However, for a robust design, an RVG
0.8 V VDD. The RVG generates a 0.4 V reference voltage should provide a stable reference voltage over different process
and is duty-cycled by CLK1 to save power. With a 3-stage corners. In [13], the authors claim that DTMOS (a MOS
S&H block, a continuously stable reference voltage is provided with the back-gate connected to the gate) could improve the
to the LDO. The LDO then multiplies the reference voltage threshold voltage stability over process corners by a factor of
to 0.6 V and powers the SAR ADC. An off-chip capacitor is 2, but in the simulations based on the utilized 65 nm technol-
used to stabilize the LDO. The LDO is always-on to provide ogy, the improvement is only about 20% (Fig. 2, Vt,DTMOS ).
a stable supply and reference to the ADC during both tracking In many modern CMOS technologies, the foundry provides
and conversion phases of the ADC. transistors with a higher threshold voltage by applying an extra
ion implantation step, while the oxide thickness remains the
III. L OW-P OWER L OW-VDD CMOS RVG same. The threshold voltage shift due to this ion implantation
can be expressed as
A. Process Characteristics of MOSFETs’ Threshold Voltage
 |Qd |
A perfect RVG needs to provide a reference voltage inde- Vt = Vt,hvt − Vt,nvt = 2 |P | + (2)
pendent of process, power supply and temperature, of which COX
process-independence is the most challenging as process vari- where Vt,hvt is the threshold voltage of the high-Vt NMOS.
ations are usually inevitable and there is not much to do about For a given implantation energy and a large tox , when tox
it from the aspect of circuit design. Hence, it is advantageous decreases, there will be more ions implanted into the substrate,
if an RVG can be based on a voltage unit from a well- leading to a larger Vt . However, when tox becomes suffi-
defined physical mechanism, for example, a BGR based on ciently small and all the ions have penetrated into the substrate,
LIU et al.: 106 nW 10 b 80 kS/s SAR ADC WITH DUTY-CYCLED REFERENCE GENERATION IN 65 nm CMOS 2437

Fig. 3. Measurement setup for the test pair, creating a temperature-insensitive

reference voltage VTG .

a further decreasing tox will result in a smaller Vt . Thus, in

the vicinity of a certain tox with certain implantation energy,
the threshold voltage shift Vt should be independent of
tox [14], and thus becomes less sensitive to process variations.
This is confirmed in the simulations based on the utilized
65 nm technology (Fig. 2, Vt,hvt – Vt,nvt ). The Vt varies only
by 3%, which is a 5x process stability improvement compared
to Vt,nvt . The above improvements are seen independent of
sizing (W, L). To summarize, Vt is a more suitable voltage
unit for CMOS RVGs as it is much more stable over process
corners compared to Vt,nvt or Vt,DTMOS. Fig. 4. (a) Measured and (b) simulated VTG of the test pair with different
current ratios.

B. Temperature Characteristics of  Vt
In [15], the temperature dependency of Vt is derived where the first term is CTAT and the second term is PTAT. By
by calculating ∂Vt /∂T. For a shallower implanted depth properly setting the current ratio k (IT2 /IT1 ) of MT1,T2, the
than the depletion edge, Vt is CTAT (Complementary To TCs (Temperature Coefficient) of these two terms can cancel
Absolute Temperature). This CTAT effect was confirmed by out each other, which makes VTG insensitive to temperature.
measurements. The measurement setup is shown in Fig. 3. In Fig. 3, two branches of current (IT1 = 8nA, IT2 = k · IT1 )
MT1,T2 are normal-Vt and high-Vt transistors respectively, are pushed into the drains of MT1,T2 and the gate voltages
fabricated in 65 nm technology. They are diode-connected VTG1,TG2 are measured with a different current ratio k from
and biased in the subthreshold region. Large transistor sizes −25 ◦ C to 110 ◦ C [Fig. 4 (a)]. The measured results fit well
(W/L = 5 μm/12 μm) are chosen for both transistors as this with the simulations in Cadence [Fig. 4 (b)]. Corresponding to
is advantageous for matching and avoids short-channel and (4), with an increasing current ratio, the TC of VTG varies
narrow-channel effects which will introduce a more complex from negative to positive. By optimizing this ratio (e.g., 1.4
temperature dependency. in this case), a temperature-insensitive VTG can be achieved.
When VTG1,TG2 >> VT (VT is the thermal voltage), the
current flowing in MT1,T2 could simply be expressed as C. CMOS RVG
W VGS − Vt Now that a temperature- and process-insensitive VG can
Id = μn COX (η − 1)V2T exp( ) (3)
L ηVT be achieved according to the previous discussion, the next
where μn is the carrier mobility, COX is the gate–oxide step is to generate a reference voltage relative to ground.
capacitance, W and L are the width and length of the transistor The RVG core is shown in Fig. 5 (right-hand side). M1,2
respectively, η is the subthreshold slope factor, VT is the are normal-Vt and high-Vt transistors, respectively. They are
thermal voltage, VGS is the gate–source voltage, and Vt is diode-connected and operate in sub-threshold as the test pair.
the threshold voltage [16]. Hence, the gate voltage difference Since the size (11.2 μm/12 μm) of M1,2 is different from the
of MT1 and MT2 could be expressed as test pair, the optimized k (1.5) for a temperature-insensitive
  VG (VG2 – VG1 ) is also slightly different. A negative feed-
VTG = VTG2 − VTG1 = Vt,hvt − Vt,nvt back loop using an OPAMP forces VP to equal VG2 , so that
 W 
IT2 μn1 COX1 the voltage drop over resistor R1 equals VG . By copying
L 1
+ ln · · · W  · ηVT (4) current I1 , a temperature-insensitive VREF , which only depends
IT1 μn2 COX2 L 2 on temperature-insensitive current and resistor ratios as well
2438 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

Fig. 5. CMOS RVG without duty-cycling.

as the temperature-insensitive VG is achieved as follows: 720 mV among 5 process corners from −25 ◦ C to 110 ◦ C,
I0 R0 which means this RVG is suitable for sensor networks and
VREF = I0 · R0 = · · VG (5) other sub-1 V systems.
I1 R1
where R0 equals the sum of R0a and R0b . Since VREF is
E. Power Consumption
temperature-insensitive while VP is CTAT as VP tracks the
CTAT threshold voltage, the accuracy of a single-transistor From Fig. 5, it is found that the power consumption of
current copy will be dramatically affected by the drain-source this RVG is proportional to I1 . In order to suppress the power
voltage, introducing a complex TC to VREF . Hence, as shown consumption, a large R1 is required at the expense of chip area.
in Fig. 5, a cascode structure is chosen here to achieve On the other hand, current I1 must force M1,2 to operate in
an accurately copied current. The transistors comprising the the subthreshold region and be large enough to make (3) valid.
cascode structure operate in the sub-threshold region and the As a tradeoff between chip area, temperature performance and
drain-source voltage is designed to be larger than 100 mV to power consumption, R1 is set to 17 M and R0 is set to
diminish channel length modulation effects. VG is generated 48.5 M, leading to I1 of 8.25 nA. The simulated power
by the feedback loop and VRB is a fraction of VREF so consumption of the RVG at 0.8 V VDD is about 40 nW.
the cascode structure does not consume too much voltage Since VG changes little with process, power supply and
headroom, making it compatible with low-VDD operation. temperature, the current consumption of the RVG is also stable
The OPAMP composing the negative feedback is shown over PVT corners.
in Fig. 5 (left-hand side). It consists of two stages whose
gain is large enough to guarantee VP is close enough to VG2 . F. Process Stability
RC-miller compensation is adopted to make sure the stability The complete RVG is also simulated at different cor-
of the negative feedback loop. The bias for the OPAMP is ners (Fig. 6). The simulated VREF varies about only ±1.5%
generated by a copy of current I1 , which is approximately (3% variation range) over five corners, well corresponding to
expressed as VG /R1 . the threshold voltage simulations in Section III-A. This implies
that the presented threshold voltage difference-based RVG
D. Minimum VDD reveals much better process stability than absolute threshold
From Fig. 5, it is easy to observe that the minimum voltage-based RVGs.
operational VDD for the RVG core is
IV. D UTY-C YCLING T ECHNIQUE
VDDmin,core = VG2 + VDS4 + VDS8 (6)
A. Duty-Cycling and Start-up of the RVG
where VG2 is the gate voltage of M2 and VDS4,8 are the As discussed in Section II, the RVG will be duty-cycled
drain–source voltage drop of M4,8 respectively. Similarly, the in order to save power, which means the RVG should be
minimum operational VDD for the OPAMP is switched on and off while VDD remains on. Switch transistors
VDDmin,OPAMP = VSG14 + VDS12 + VDS11 (7) are inserted in each branch between PMOS and NMOS as
shown in Fig. 7. While not shown in the figure, the current
where VSG14 is the source–gate voltage of M14 , and VDS11,12 paths in the OPAMP are disabled in a similar way. To boost
are the drain–source voltage drop of M11,12 respectively. The duty-cycling speed, voltages VG and VBias should be restored
minimum power supply of the RVG is determined by the quickly. To do so, two switched capacitors CS1,S2 are placed
smaller of (6) and (7). Due to the subthreshold operation of at these nodes to save and restore their levels when the RVG
M2,14 , voltages VG2 and VSG14 are smaller than the absolute is duty-cycled.
threshold voltage value of M2,14 . VDS4,8,11,12 need to be at Besides this duty-cycling technique, the RVG also needs
least about 100 mV. The simulated minimum VDD is about a start-up circuit to guarantee correct start-up of the circuit
LIU et al.: 106 nW 10 b 80 kS/s SAR ADC WITH DUTY-CYCLED REFERENCE GENERATION IN 65 nm CMOS 2439

Fig. 8. Architecture and waveforms of a one-stage S&H.

Fig. 6. Simulated VREF in 5 process corners.

Fig. 7. RVG with start-up circuit and duty-cycling switches.

Fig. 9. Architecture and waveforms of a three-stage S&H.
when VDD is switched on for the very first time. The start-up
circuit is shown in Fig. 7. Assuming the duty-cycling switches
are on, the moment VDD is switched on, VS will jump to a of VREF , the output of the RVG. When RVG and SA are
high voltage level due to CS being discharged prior to this switched off and CA begins to hold the sampled voltage, due to
moment, and thus open transistor MS2 . VG is then discharged the voltage drop over NMOS switch SA , there will be leakage
and M3∼6 are switched on gradually, enabling current flow and through SA causing droop of VA . As a result, voltage VA
functionality of the circuit. As soon as VBias rises sufficiently, is neither stable nor accurate for most of the time, which
MS1 will pull VS to ground to switch off MS2 and disable the will cause performance loss of the SAR ADC compared to
start-up circuit. The RVG core takes over and will settle to operation with a non-duty-cycled RVG.
the proper operation state. The start-up time is approximately
1.5 ms. In case the duty-cycling switches are not on (or already C. Three-Stage Dual-Clock Sample-and-Hold
duty-cycled) during the moment VDD is switched on, correct
To solve the above problems, a three-stage dual-clock S&H
start-up is still ensured, but the initial start-up will take longer
is presented as shown in Fig. 9. Compared with Fig. 8, two
due to the duty-cycled operation.
more switched capacitors controlled by CLK2 are inserted
between node A and the LDO. CLK1 and CLK2 have the
B. One-Stage Sample-and-Hold same frequency but different pulse widths. CLK1 switches the
As discussed in Section II, even though the RVG is duty- RVG and SA on simultaneously as before, thus VA will be
cycled, a continuously stable reference voltage is required for stable after some start-up time. At that time, CLK2 switches
the LDO as it is switched on all of the time. A one-stage S&H SB and SC on, so that voltage VB and VC are refreshed
could be adopted to sample and hold the reference voltage from the stable VA . In this way, VC is isolated from the
of the RVG as shown in Fig. 8. The RVG and the switched start-up behavior of the RVG. Subsequently, CLK1 and CLK2
capacitor network (SA , CA ) are controlled by the same clock switch the RVG and SA,B,C off simultaneously and the hold
CLK1 and voltage VA is provided to the LDO. This scheme phase starts. As before, the leakage through SA causes an
suffers from two problems. The moment CLK1 switches the unstable VA . However, the voltage drop over SB is smaller
RVG and SA on, VA would experience a large start-up ripple than that of SA leading to smaller leakage from node B
2440 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

because the leakage of a MOS switch is proportional to

the voltage drop between drain and source. Furthermore, the
voltage drop over SC is again smaller than that of SB so that
the leakage from node C becomes very small. As a result, a
very stable VC is achieved during the entire clock period, and
the simulated maximum ripple is merely 0.1 mV. Considering
the target application is a 10 b SAR ADC with an LSB step of
approximately 1 mV, this ripple of 0.1 mV is acceptable. The
above discussion indicates that a too high or too low VREF
will either make the leakage in the S&H switches too high, or
will increase the RC time, which would slow down the settling
time and thus degrade the duty-cycling speed. As a result, a
VREF of 400 mV is chosen here.
Fig. 10. LDO with continuous biasing generation.
The performance requirements for node A, B and C
are different as it is more important to start-up fast at
node A and B than to leak slightly, while small leakage is
more important to enable longer hold time and better stability
at node C. However, a small CB will lead to a large leakage
at node B and increase the leakage on CC subsequently.
Consequently, the value of CA,B,C is set to 12.5 pF, 25 pF
and 50 pF respectively. SA is set to about 5 times the size of
SB,C and SB,C have the same size.
In this work, the duty-cycle clocks CLK1 and CLK2 are
generated externally from an FPGA. The frequency is 20 Hz
and the pulse widths are 5 ms and 2.5 ms respectively. This
frequency is determined by the maximum hold time the duty-
cycling could achieve plus the start-up time and refresh time
needed. Because of the low frequency of operation and the Fig. 11. Architecture of the 10 b SAR ADC.
insensitivity to the exact timing, they could be generated
on chip with little power consumption. According to sim-
ulations, this logic would consume only 2 nW and occupy very low frequency so no extra compensation is needed here
only 50 μm x 12 μm. to guarantee the loop stability. As discussed previously, the
LDO is always-on, which requires an always-on bias voltage
V. L OW D ROPOUT R EGULATOR for M19,25. Looking back at Fig. 7, VBias is duty-cycled
and CS1 stores the voltage of VBias to make the rebuilding
Since the VREF generated by the RVG is small (∼ 0.4 V)
faster. Similar to the duty-cycling block, another S&H (CSB )
without driving capability, an LDO regulator is required to
controlled by CLK2 is inserted to generate continuous biasing
multiply the VREF to 0.6 V and drive the SAR ADC. For
voltage for M19,25. The current consumption of the LDO
an N-bit SAR ADC, it usually takes N comparison and DAC
is 1.35I1.
switching cycles for each conversion, which puts forward strict
requirements for the LDOs as they have to respond fast enough VI. SAR ADC W ITH L OW-P OWER B I -D IRECTIONAL
to settle the DAC outputs at more than N times the sampling DYNAMIC C OMPARATOR
frequency. As a result, the power consumption of the LDOs
The 10 b asynchronous SAR ADC is shown in Fig. 11. The
(or buffers) is usually several times or even more than 10 times
clock for the logic is generated internally as in [4] hence only
higher than that of ADCs [17], [18].
the sample clock is required externally. The DAC is segmented
In this work, we adopt an off-chip capacitor (10 μF) to
into three thermal encoded MSBs and Seven binary encoded
ease the strict response and power consumption requirements
LSBs, reducing power consumption and avoiding large MSB
for the LDO. The SAR ADC in this work is primarily using
errors. Lateral metal-metal capacitors [20] are adopted to
dynamic circuits, which have little static power but require
implement the DAC and the total capacitance is 256 fF for
large current peaks once in a while. Since the feedback loop
high power-efficiency. The power-efficiency of the SAR ADC
of the LDO is too slow to respond to this load change,
is further improved by a low-power bi-directional dynamic
the off-chip capacitor will provide those current peaks with
comparator.
slight voltage drop. As a result, the LDO only needs to
provide a nearly constant current equal to the average current
consumption of the SAR ADC. A. Typical Dynamic Comparator With Integration-Based
As shown in Fig. 10, the reference voltage VC of the LDO Preamplifier
is taken from CC (Fig. 9). A 2-stage OPAMP is utilized to The schematic and operation of a typical dynamic com-
achieve high loop gain. Since the impedance at the output of parator [19] are shown in Fig. 12. It comprises an integration-
the LDO is very high, the resulting main pole locates at a based preamplifier and a latch. During the reset phase, the
LIU et al.: 106 nW 10 b 80 kS/s SAR ADC WITH DUTY-CYCLED REFERENCE GENERATION IN 65 nm CMOS 2441

Fig. 12. Prior-art dynamic comparator [19] and waveforms of key nodes. Fig. 13. Bi-directional dynamic comparator.

parasitic capacitors CPP , PN are charged to VDD by M4,3 .

The comparison starts when CLK goes high. CPP , PN are
discharged through input pair M2,1 and VAP,AN will drop
according to the input voltages VINP , INN . In time, the common
mode of VAP,AN is gradually decreasing while the differential
input signal is gradually amplified. When the common mode
of VAP,AN reaches the threshold of the latch, the latch will
take over and output the comparison result. Next, CLK will
go low and the pre-amplifier and latch are reset to their initial Fig. 14. Key nodes waveforms of the bi-directional dynamic comparator.
conditions. Thanks to the amplification of the preamplifier,
the noise and power efficiency of the overall comparator are
dominated by the preamplifier. The equivalent input noise of comparison starts, VAP,AN are pushed to ground by M6,7 .
this preamplifier equals [19] Then, the PMOS input pair M3,4 is enabled first by switching
 on tail transistor M5 . CPP , PN are charged and VAP,AN increase
8 1 1
σv ≈ k · T · ·   ∼ √ (8) according to the input signal. An OR gate is utilized to detect
q C · (V
PP − V )
thlatch DD
QC when VAP or VAN reaches half VDD. At that point, the
PMOS pair M3,4 is disabled by switching off M5 while M0 is
where Vthlatch is the threshold voltage of the latch and QC rep- switched on to enable NMOS pair M1,2 together with the latch.
resents the absolute value of average transferred charge on From this moment onwards, this bi-directional comparator
parasitic capacitor CPP,PN before the latch takes over. The operates as the typical structure and achieves the same gain
preamplifier energy dissipation of one comparison equals (see Fig. 14). A further advantage of this comparator is that
VAP,AN return inherently to their initial condition (GND) at
EC = 2 · CPP · V2DD . (9)
the end of the comparison, which avoids a reset cycle. An RST
From (8) and (9), the tradeoff between noise and energy signal is still present to avoid floating VAP,AN between cycles.
consumption can be observed. For fixed VDD and Vthlatch , For this bi-directional preamplifier, the sum of absolute value
the equivalent input noise of the preamplifier is proportional of average transferred charge on CPP,PN during charging and
to (CPP )−0.5 , while the energy consumption is proportional discharging is

 

to CPP . If one wishes to reduce the noise by a factor of 2, the  VDD   VDD 

QCB = CPP · − 0  + CPP · Vthlatch −
2 
consumed energy has to be quadrupled.
2
= CPP · (VDD − Vthlatch ) = QC (10)
B. Bi-Directional Dynamic Comparator
which means that with the same CPP,PN , the bi-directional
When reflecting on the operation of the dynamic compara-
preamplifier has the same noise performance as the typical
tor (Fig. 12), one can note that the discharging slope of CPP,PN
structure. However, as CPP,PN are only charged to one-half
is used to perform dynamic amplification. On the other hand,
VDD rather than VDD, the energy consumption of the
the charging slope of CPP,PN is not used for amplification, but
bi-directional preamplifier is
only to reset the comparator. The bi-directional preamplifier
takes advantage of both slopes to perform amplification and VDD
EB = 2 · CPP · · VDD = CPP · V2DD (11)
can thus improve the power-efficiency by a factor of two. 2
As shown in Figs. 13 and 14, a PMOS input stage M3,4 which is only half of (9). Note that the threshold of the OR gate
is inserted in parallel with NMOS pair M1,2 . Before the does not have to be very precise as it only changes the noise
2442 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

Fig. 18. Measured PSRR of the RVG.

Fig. 15. Die photograph in 65 nm CMOS technology.

Fig. 19. Measured temperature dependency of 15 samples.

Fig. 16. Measured output reference voltage of the RVG versus power supply. A. Stand-Alone RVG
A total of 15 RVG samples was measured. They all begin
to operate from a minimum VDD between 0.60 ∼ 0.62 V.
A sample with 0.62 V minimum VDD is selected for the
measurements shown here. Figs. 16 and 17 display the VREF
and current consumption as function of VDD. From 0.62 V
to 2.0 V, the line sensitivity is 0.07%/V. At 0.8 V VDD, the
measured power consumption is only 38 nW. At the minimum
supply of 0.62 V, the measured power consumption is 25 nW.
The PSRR is measured by measuring the transfer from a tone
at VDD to the output of the RVG. The measured PSRR of
the RVG is better than −49 dB up to near Nyquist frequency
as shown in Fig. 18. The temperature dependency of the 15
Fig. 17. Measured current consumption of the RVG versus power supply.
samples is shown in Fig. 19. From −25 ◦ C to 110 ◦ C, the
TCs vary from 44 to 248 ppm/◦ C with an average TC of
performance and consumption slightly. For the whole dynamic 108 ppm/◦ C. At 25 ◦ C, the average output reference voltage
comparator, the power consumption ratio of preamplifier and is 389.9 mV with a 4.0 mV standard deviation. According to
latch is about 3:1, which suggests this bi-directional compara- Monte-Carlo simulations, the dominant reason for part-to-part
tor saves about 37.5% of the power of the typical comparator. variation is mismatch in the OPAMP and the current mirror
In practice, the additional logic causes 4.5% overhead, which M3−5,7−9. Table I compares this RVG with other low power
is mostly due to short-circuit current in the OR gate, thus CMOS and BJT RVGs. After applying duty-cycling, this
saving 33% overall. RVG consumes lower power. Besides, the sample-to-sample
variation is comparable to BJT RVGs and substantially better
than Vt -based CMOS RVGs. Further, the PSRR at 100 Hz is
VII. M EASUREMENT R ESULTS equal or better than other listed work.
The SAR ADC with duty-cycled reference generation was
B. SAR ADC With Duty-Cycled Reference Generation
implemented in a 65 nm CMOS technology and occupies
0.266 mm2 due to the large resistors used in the RVG and The power breakdown and ENOB of the reference-included
LDO (Fig. 15). First, a stand-alone RVG is measured without ADC (operating at 80 kS/s) with different duty-cycling rates
duty-cycling. Then, the measurements of the SAR ADC with are shown in Figs. 20 and 21. At 10% duty-cycle of the
duty-cycled reference generation are shown. RVG, the power consumption of the RVG is 3.7 nW from
LIU et al.: 106 nW 10 b 80 kS/s SAR ADC WITH DUTY-CYCLED REFERENCE GENERATION IN 65 nm CMOS 2443

TABLE I
RVG P ERFORMANCE S UMMARY AND C OMPARISON

Fig. 23. Measured spectrum of the ADC powered by a 10% duty-cycled

RVG and LDO with 1 kHz 150 mVPP interference imposed on the external
power supply (0.8 V).

Fig. 24. Measured DNL of the ADC with 10% duty-cycled RVG.

Fig. 20. Measured power breakdown of the reference-included 10 b ADC

at 80 kS/s versus different duty-cycling rates.

Fig. 25. Measured INL of the ADC with 10% duty-cycled RVG.

FoM of 2.4 fJ/conversion-step. Note that since the LDO is

always-on, the power consumption and the inevitable dropout
loss due to the voltage drop between power supply and output
Fig. 21. Measured near-Nyquist ENOB of the reference-included 10 b ADC
at 80 kS/s versus different duty-cycling rates. of the LDO takes about 1/3 of the total power consumption.
In order to demonstrate the PSRR of the whole system, the
ADC is measured with an intentional interference imposed
on the external power supply while all decoupling capacitors
are removed. First, the ADC without RVG/LDO powered by
external power supply (0.6 V) imposed with 1 kHz 150 mVPP
interference is measured, where the input signal is modulated
by the interference and two large spurs at Fsig ± FVDD are
observed (Fig. 22). Along with other noise from the external
power supply, the ADC achieves a poor SNDR (30.2 dB) and
SFDR (34.2 dB). Fig. 23 displays the spectrum of the ADC
powered by a 10% duty-cycled RVG and LDO with the same
interference imposed on the external power supply (0.8 V),
Fig. 22. Measured spectrum of the ADC powered by external power which reveals 64.4 dB suppression on the intermodulation
supply (0.6 V) imposed with 1 kHz 150 mVPP interference. spurs at Fsig ±FVDD and better noise suppression. The achieved
SNDR and SFDR are the same as the case with an ideal clean
supply powering the ADC directly. With 10% duty-cycling,
0.8 V supply, which is far less than that of the ADC core. other performances of the SAR ADC are also measured. The
Meanwhile, the ENOB (measured near Nyquist at 80 kS/s) maximum DNL is 0.94 LSB (Fig. 24) and the maximum INL
remains 9.1 bit regardless of the duty-cycling, resulting in a is 0.60 LSB (Fig. 25). At near Nyquist input, the SNDR
2444 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

block. Dual-clock control protects the output from the start-

up behavior of the RVG and the multi-stage structure dimin-
ishes the leakage, enabling 10% duty-cycling of the RVG.
A low-power bi-directional dynamic comparator is adopted
in the SAR ADC, which makes use of both charging and
discharging to perform the pre-amplification, resulting in high
power-efficiency. Compared to a typical comparator [19], this
bi-directional comparator reduces the power by 33% including
Fig. 26. Measured spectrum of the ADC with 10% duty-cycled RVG.
the power of extra logic circuits while maintaining the same
noise performance. With the above techniques, the reference-
included SAR ADC achieves a FoM of 2.4 fJ/conversion-step.

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[19] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, Rainier Van Dommele received the B.Eng. degree
E. A. M. Klumperink, and B. Nauta, “A 10-bit charge-redistribution in engineering from the Fontys Hogeschool
ADC consuming 1.9 μW at 1 MS/s,” IEEE J. Solid-State Circuits, Eindhoven, The Netherlands.
vol. 45, no. 5, pp. 1007–1015, May 2010. In 2007, he started as technician within the Radio
[20] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot, communications (ECR) group at the Eindhoven
“A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC University of Technology, Eindhoven, The
in 90nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2010, Netherlands. Since 2012, he has been a Technician
pp. 388–389. within the Mixed-signal Microelectronics (MsM)
group at the Eindhoven University of Technology,
The Netherlands.

Arthur van Roermund (SM’95) was born in

Delft, The Netherlands, in 1951. He received the
M.Sc. degree in electrical engineering from Delft
University of Technology, Delft, The Netherlands,
in 1975, and the Ph.D. degree in applied sciences
Maoqiang Liu (S’13) received the B.Sc. and from K.U.Leuven, Leuven, Belgium, in 1987.
M.Sc. degrees from Peking University, Beijing, From 1975 to 1992 he was with Philips Research
China, in 2010 and 2013, respectively. He is Laboratories in Eindhoven, The Netherlands. From
currently working toward the Ph.D. degree at 1992 to 1999, he has been a Full Professor with
Eindhoven University of Technology, Eindhoven, the Electrical Engineering Department of Delft Uni-
The Netherlands. versity of Technology. In October 1999 he joined
He is currently working on low-power mixed- Eindhoven University of Technology. Since then, he is Chairman of the Mixed-
signal circuits, with a main focus on the low-power signal Microelectronics group. He was Director of research of the Electrical
reference voltage generator, low-power SAR ADCs Engineering Department (2002-2012). He has over 600 publications, 25 books
and the integration of these two aspects in a system. and is co-editor of another 10 books.
He was co-organiser of the yearly workshop on Advanced Analog Circuit
Design (AACD, 2001-2012). In 2004 he achieved the ’Simon Stevin Meester’
award for his scientific and technological achievements. He was member of
three international assessment panels: Politecnico di Milano, Italy, 2007; Aalto
University, Finland, 2009; KTH, Stockholm, Sweden, 2012.

Pieter Harpe (SM’15) received the M.Sc. and

Ph.D. degrees from the Eindhoven University of
Technology, Eindhoven, The Netherlands.
In 2008, he started as a Researcher at Holst Cen-
Kevin Pelzers received the Ing. degree in mecha- tre/imec, The Netherlands. Since then, he has been
tronics from Fontys University of Applied Sci- working on ultra low-power wireless transceivers,
ences, The Netherlands. He is currently working with a main focus on ADC research and design.
toward the M.S. degree in electrical engineering In April 2011, he joined Eindhoven University of
at Eindhoven University of Technology, Eindhoven, Technology as an Assistant Professor on low-power
The Netherlands. mixed-signal circuits.
During his education, he followed an internal Dr. Harpe has been co-organizer of the yearly
internship at the Mixed Signal Microelectronics workshop on Advances in Analog Circuit Design (AACD). In 2013, he
group on the subject of MOSFET threshold voltage became a member of the Technical Program Committees of ISSCC and
drift. ESSCIRC. In 2013, he received a VENI grant from the Dutch Technology
Foundation STW for research on multi-functional ADCs.