Received February 21, 2020, accepted March 11, 2020, date of publication March 16, 2020, date of current

version March 26, 2020.

Digital Object Identifier 10.1109/ACCESS.2020.2980926

An Analytical Scalable Lumped-Element Model

for GaN on Si Inductors
MARIO SAN MIGUEL MONTESDEOCA 1,2 , SERGIO MATEOS ANGULO 1,2 ,

DANIEL MAYOR DUARTE 1,2 , JAVIER DEL PINO 2 , (Member, IEEE),

JAVIER A. GARCÍA Y GARCÍA 2 , (Member, IEEE), AND
SUNIL L. KHEMCHANDANI 2 , (Member, IEEE)
1 Wireless Innovative MMIC (WIMMIC), 35004 Las Palmas de Gran Canaria, Spain
2 Institute for Applied Microelectronics (IUMA), University of Las Palmas de Gran Canaria, 35017 Las Palmas de Gran Canaria, Spain
Corresponding author: Mario San Miguel Montesdeoca ([email protected])
This work was supported in part by the Spanish Ministry of Science, Innovation and Universities under Grant RTI2018-099189-B-C22, and
in part by the Canary Agency for Research, Innovation and Information Society (ACIISI), Canary Islands Government under
Grant ProID2017010067.

ABSTRACT In this paper, a wide-band distributed model that can approximate the behaviour of square and
octagonal inductors, both with and without tapering, is presented. This paper also presents a novel way of
accurately modelling the lateral coupling in the substrate. The presented model can be applied to any foundry
process, and its validity has been demonstrated using a novel technology, the D01GH GaN process developed
by OMMIC, which has a high resistivity substrate. To do so, seventeen inductors have been designed
and manufactured. The proposed model has been verified against EM simulations and measurements of
the designed inductors. Comparisons show that the model can correctly estimate the behaviour of the
inductor, improving the results of the EM simulations for most cases. The root mean square (RMS) error
calculated across the samples when estimating the inductance is 0.0565. The RMS error for the quality
factor results (2.2727) is also adequate, although there is more deviation when comparing the results with
the measurements.

INDEX TERMS Inductor model, lateral coupling, octagonal inductor, square inductor, tapered inductor.

I. INTRODUCTION gradual decrease of the width of each turn of the inductor so

Integrated inductors are a key component in RFIC and MMIC that the outer turns are wider, reducing the ohmic losses of
designs, since they have a significant impact on the size the inductor, and the inner turns are narrower, maximising
and performance of the overall system. Because of this, esti- the magnetic field flowing through the inner hole of the
mating the behaviour of these components has been a topic inductor.
of interest for the integrated design community for the last Numerous effects must be accounted for when modelling
two decades. Several works found in the literature provide an inductor, especially a tapered one, such as DC inductance,
different models and techniques to model the behaviour of skin effects, eddy currents and lateral coupling of the sub-
manufactured inductors [1]–[4]. However, the growing inter- strate. The first three effects have been widely analysed in the
est in GaN processes in the last years has increased the need past [8]–[11]. [12] deems lateral coupling as not significant or
for a model that can correctly predict the behaviour of an negligible on high-resistivity substrates, like the ones on GaN
inductor layed out on a high-resistivity substrate. or GaAs processes. Many papers have attempted to emulate
Additionally, an accurate model for tapered inductors the effect of lateral coupling using resistors and capacitors
would be welcome in the circuit designer community. Taper- (RM and CM ), but the calculation of their values has always
ing is a well-known and widely discussed approach for been based on adjustment parameters or by applying extrac-
increasing the quality factor (Q) of an inductor [5]–[7]. The tion methods [13]–[16]. The model presented in this paper
quality factor of an inductor is the ratio of its reactance to includes mathematical formulation for modelling lateral cou-
its series resistance. The tapering technique consists on the pling and its impact on a high-resistivity substrate has been
demonstrated.
The associate editor coordinating the review of this manuscript and This paper proposes a model that can be utilised to pre-
approving it for publication was Yue Zhang . dict the behaviour of square and octagonal inductors, both

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
VOLUME 8, 2020 52863
 M. San Miguel Montesdeoca et al.: Analytical Scalable Lumped-Element Model for GaN on Si Inductors

FIGURE 1. Generic inductor inset in the D01GH process.

FIGURE 2. Proposed inductor model for the inductor shown in Fig.1.

tapered and non-tapered. The model and its equations are In addition to the utilised technology, several parame-
explained in Section II, whereas a comparison between ters have to be taken into account when developing the
the results of the model, electromagnetic (EM) simulations inductor model. Among these parameters are the shape of the
and measurements for different manufactured inductors is inductor (square, octagonal, circular), its number of turns or
shown in Section III. Finally, some conclusions are drawn segments, the length and width of each segment (important
in Section IV. for the case of tapered inductors), the length and width of
the underpass and the materials of the different metal lay-
ers that make up the inductor. Once these parameters have
II. PROPOSED INDUCTOR MODEL been properly defined, the equivalent inductor model shown
The first aspect to consider when developing the model of an in Fig.2 can be applied. In this scalable model, the number
inductor is the different materials involved in the definition of segments is mainly defined by the number of turns of the
of the technology and their distribution. The D01GH GaN inductor. Therefore, for an inductor with two turns, there will
process developed by OMMIC follows a similar composi- be two segments, whereas for an inductor with two and a half
tion to other GaN on Si technologies. A simplified version turns like the one shown in Fig.1, the number of segments
of the cross-section for this process including an octago- will be three.
nal inductor is shown in Fig.1. In this case, the inductor
is constructed on the IN metal layer. The underpass of the A. SEGMENT BLOCK MODELLING
inductor is defined in the Metal 1 (MET1) layer. Between The schematic for the Segment block of the model is shown
these metal layers are two additional layers, SiN and SiO2 , in Fig.3. In this model, RSKIN (i) and L(i) represent the skin
which act as dielectric materials. Under the MET1 layer, and proximity effects of the inductor [1], [8] [12] for the seg-
two high resistivity layers (AlGaN and Interface) can be ment. The total DC inductance of the inductor is split evenly
found. Finally, the Silicon (Si) substrate occupies the bottom across the segments, while the resistance of each segment is
layer. calculated using (1) [1], where l(i) and w(i) are the length and

52864 VOLUME 8, 2020

M. San Miguel Montesdeoca et al.: Analytical Scalable Lumped-Element Model for GaN on Si Inductors

FIGURE 3. Schematic of the SEGMENT block. FIGURE 4. Schematic of the UNDERPASS block.

width of the segment, σ is the conductivity of the metal of the that the characteristics and properties (thickness, permitivity
inductor (IN), tIN is the thickness of said metal and δEFF is and resistivity) of each layer are different. Since this is a
the effective skin depth, calculated using (2). distributed model, the capacitors that account for the capaci-
tance of each layer are divided by two, as it can be observed
 
l(i)
RSKIN (i) = in the model shown in Fig.3. The resistors are multiplied by
2 · σ · w(i) · δ
     two for the same reason [18].
sinh δtEFF
IN
+ sin δtEFF
IN

· (1) A(i)
CSiN (i) = ε0 · εSiN ·

(3)
  
cosh δtEFFIN
+ cos δtEFF
IN
tSiN
A(i)
= ε0 · εSiO2 ·
s
(4)
r r
3 tIN 3 tIN 2 CSiO2(i)
δEFF = ·δ = · (2) tSiO2
w w µσ ω0 2 · ε0 · εAlGaN · A(i)
CS.AlGaN = √ (5)
In (2), w is the maximum width of the inductor, µ is the
q
2 · tAlGaN + v − 4 · tAlGaN 2 +v
magnetic permeability of the material and ω0 is the angular ρAlGaN · ε0 · εAlGaN
frequency. In this model, it is assumed that the magnetic field RS.AlGaN (i) = (6)
CS.AlGaN (i)
is spread evenly across the substrate and that no elements
are placed under the inductors. This is a common practice in
MMIC design. B. INPUT/OUTPUT STRIPS AND UNDERPASS
To properly model the substrate of the inductor, all the BLOCK MODELLING
process layers should be considered in order to have the most This model also takes into account the resistance of the
accurate model possible. Thus, the capacitance of the SiN input and output strips of metal (RIS and ROS ) used to con-
and SiO2 layers under the IN metal area occupied by each nect the inductor, as well as the resistance of the under-
segment (A(i) ) of the inductor had to be modelled. To do pass of the inductor (RU ), which is implemented in the
so, (3) and (4) are utilised, where t is the thickness of the MET1 layer, as stated above. These values can be calculated
material. The AlGaN, Inter and Si layers found below the using (7)–(9), where ρ is the resistivity of the material, l is
MET1 layer are also considered. Since this process has a high the length of the strip or underpass and w is the width of
resistivity substrate, where ρSi is 5k· cm and ρAlGaN and said strip/underpass [17]. The effects of the underpass on the
ρInter are 100k· cm, the resistance of each of these layers substrate are also considered, as shown in Fig.4, where the
must also be considered. The capacitances and resistances of resistances and capacitances are obtained using (5) and (6).
each layer can be obtained by applying (5) and (6) [1], [17].
In these equations, v = A(i) /π. The equations for the Inter ρIN · lIS
RIS = (7)
and Si layers are the same as for AlGaN, but keeping in mind tIN · wIS

VOLUME 8, 2020 52865

 M. San Miguel Montesdeoca et al.: Analytical Scalable Lumped-Element Model for GaN on Si Inductors

ρIN · lOS
ROS = (8) resistance generated between the edges of the internal hole of
tIN · wOS the inductor and between the edges of the different turns. This
ρMET · lU way, it could be theorised that RM is the series connection
RU = (9)
tMET · wU of the resistance between the edges of each turn and the
Another important aspect of this inductor model is that resistance between the edges of the internal hole. There-
it also considers the parasitic capacitances generated by the fore, if the equation for the resistance of a three-dimensional
coupling between the metal strips of the inductor and the conductor (16) is utilised as a reference and modified accord-
underpass. This effect can be modelled as a simple plane ingly, RM could be calculated as shown in (17), where lIND is
parallel capacitor [19], [20], which is the typical widespread the total length of the inductor.
solution. In the case of OMMIC’s D01GH process, the SiN l l
R=ρ· =ρ· (16)
and SiO2 layers found between the IN and MET1 layers A w·t
(which is used for the underpass) produce capacitive effects lIND
RM = ρSi · (17)
due to their dielectric characteristics. Therefore, two series ASEP + AINT
capacitors (CPSiN and CPSiO2 ) are included to model the For the calculation of CM , the equation of a parallel-plate
overlaps between the IN and MET1 layer for each segment of capacitor, shown in (18) was considered [21]. In this case and
the inductor. The combination of these two capacitors is cal- in a similar fashion to the calculation of RM , the lateral capac-
culated for each segment and represented as CUNDERPASS(i) in itance can be considered as the series combination of the
the model shown in Fig.2. The equations for both capacitors capacitances that result of the parasitic coupling between the
are shown in (10) and (11) [1]. edges of the turns of the inductor in the substrate and between
CPSiN = ε0 · εSiN · tSiN · w(i) · wUNDERPASS (10) the sides of the inner hole. Since the resulting capacitance
CPSiO2 = ε0 · εSiO2 · tSiO2 · w(i) · wUNDERPASS (11) in the series connection of capacitors is always determined
by the smallest capacitor, in this case CM is equivalent to
C. LATERAL COUPLING MODEL the capacitance between the sides of the internal hole of the
inductor. The resulting equation for this case is (19), where
Finally, the formulation of the CM and RM elements that
di is the diameter of the internal hole of the inductor.
model the lateral coupling in the substrate will also be
explained. Although these elements have already been pre- ε·A
C = (18)
sented in previous publications [12]–[16], in those cases d
CM and RM were obtained via extraction or by using for- ε0 · εSi · AINT
CM = (19)
mulae with empirical adjustment factors, whereas in this di
model they are obtained purely from the dimensions of the
inductor and physical properties of the materials that con- III. MODEL VERIFICATION
form the substrate. In order to explain the formulation for In order to demonstrate that the developed model
CM and RM , the area of the lines that conform the inductor can correctly estimate the behaviour inductors of the
(ALINES ), the area of the internal hole of the inductor (AINT ) OMMIC D01GH GaN-on-Si process, seventeen induc-
and the area occupied by the separation of the turns of the tors of different shapes (tapered and non-tapered square
inductor (ASEP ) must be calculated. Based on these areas, and octagonal inductors) and sizes were simulated using
the total area occupied by the inductor can be defined as Keysight Momentum 3D EM Simulator and manufactured.
shown in (12). The equations for the different areas for an The main characteristics of these inductors are shown
octagonal inductor are shown in (13)-(15). For other types of in Table 1.
inductors, such as square ones, the equations for the inter-
nal square calculation and separation area must be modified TABLE 1. Physical characteristics of the inductors.
accordingly. In (15), s is the separation between the turns
of the inductor and n represents the number of turns of said
inductor.
ATOTAL = ALINES + AINT + ASEP (12)
XN
ALINES = l(i) · w(i) (13)
i=1
h i
ASEP = 2π · (n·rEXT · s) − (w(1) · (2n − s − 1)) + 1.5s2
(14)
AINT = π · rINT
2
(15)
When modelling the lateral coupling through the sub-
strate, the main aspects to consider are the capacitance and

52866 VOLUME 8, 2020

M. San Miguel Montesdeoca et al.: Analytical Scalable Lumped-Element Model for GaN on Si Inductors

FIGURE 5. EM simulation and microphotograph of the manufactured inductors.

The inductors were simulated up to 50GHz with a high EM simulations, the measurements and the developed model
meshing resolution in order to guarantee that a correct anal- for the four inductors shown in Fig. 5. Additionally, Table 2
ysis was performed. Fig. 5 shows four of the manufactured shows the model parameters for the four inductors shown
inductors (one of each type), as well as current density in Fig. 5.
simulation results for each one at the frequency where the From the results shown in Fig. 6, it can be observed that
maximum quality factor is reached. the developed model provides excellent results for the esti-
As it can be observed, all the manufactured inductors mation of the inductance, most of the times delivering a more
have input and output GSG pads, so they can be measured accurate result than the EM simulation, both in magnitude
directly on-wafer and not be affected by the parasitic effects and frequency response. The quality factor results, however,
caused by bonding. The measurements were performed using show more variability. In some cases, the model is not as
the Agilent 8720ES S-Parameter Network Analyzer, which precise as the EM simulation result at low frequencies for
permits the measurement of circuits up to 20GHz. All mea- the octagonal inductors. However, for the other types of
surement results were obtained by de-embedding the effects inductors, the model matches or improves the results of the
of the probes, the GSG pad parasitics and the inductive effects EM simulations.
of the metal lines reaching to and from the inductors by using In order to have a more analytical view of the results and
open, short and thru structures that were on the same die perform a more detailed analysis, Table 3 has been filled
as the inductors. Fig. 6 shows the comparison between the out. In this table, the measured results for the inductance and

VOLUME 8, 2020 52867

 M. San Miguel Montesdeoca et al.: Analytical Scalable Lumped-Element Model for GaN on Si Inductors

FIGURE 6. Comparison between the model, EM and simulation results for each inductor shown in Fig. 5.

quality factor have been compared with the results obtained been compared at the frequency at which the maximum
in the EM simulations and with the model presented in measured (MM) quality factor (fQMM ) is obtained. This way,
this paper. To perform this comparison, the results have it can be verified whether the model is valid at a critical point

52868 VOLUME 8, 2020

M. San Miguel Montesdeoca et al.: Analytical Scalable Lumped-Element Model for GaN on Si Inductors

TABLE 2. Model parameters for the inductors shown in Fig. 5. The results shown in the table demonstrate that the model
can correctly predict the inductance of the manufactured
inductors, showing a maximum positive error of 9.57% when
compared to the measured value at fQMM . This error is
lower than the maximum positive one obtained in the EM
simulations, 12.24% for the same inductor (L15). In general,
it can be observed that the results are better for the model,
although the results are better for the EM simulation for
the case of the non-tapered and tapered square inductors.
However, the results of the inductance estimation are evenly
matched for both the model and the EM simulations. Based
on these results, it can be stated that the model can correctly
estimate the inductance of the four types of inductors that
have been tested.
Regarding the quality factor, the results are worse than
the ones obtained for the inductance, as observed in Fig. 5
and Table 3. In this case, the maximum relative error of
the model is obtained for inductor L13, with a result of
−37.93%. For the same inductor, the EM simulation relative
error is −17.59%, which is a far better estimation. However,
if the results are analysed for each type of inductor, the error
results of the model are in line with the ones obtained for the
EM simulations. Even though the relative errors of the quality
factor are greater for both the model and the EM simulation
of the inductors, some of this deviation may be due to process
variability.
After careful analysis of the discrepancies between the
measurements and the results of the model and the EM
simulation, it could be articulated that the model provides a
better estimation of the inductance and quality factor than
the EM simulation for most cases. In fact, the root mean
square (RMS) error of all samples for the inductance is
practically the same for the model (0.0565) than for the EM
simulation (0.0544). The RMS error of the quality factor of
all samples is a bit lower for the model (2.2727) than for
the EM simulation (2.4776). Based on these results, it could
be stated that this model could be utilised to estimate the
inductance and quality factor of an inductor manufactured
with the D01GH GaN process and, possibly, other processes,
both with and without high-resistivity substrates.

IV. CONCLUSION
This paper presents an accurate analytical model for tapered
and non-tapered square and octagonal inductors. In this case,
the model has been verified by applying it to OMMIC’s
D01GH GaN process, a novel process that has a high resis-
tivity substrate. A comparison between the measurements
of 17 manufactured inductors, their model and their EM
simulations was carried out to determine the validity of the
model. The results show that the model achieves low error
of each inductor or not. It must be noted that inductor L5 is a values when compared to the measurement results. These
variation of inductor L4, but with an additional metalization errors are very similar to the ones obtained when comparing
layer that was not included in the model. Therefore, this the EM simulations and the measurements. This proves that
inductor and its results are not considered in the overall the model is valid and properly estimates the inductance and
analysis. quality factor of the manufactured inductors. In light of these

VOLUME 8, 2020 52869

 M. San Miguel Montesdeoca et al.: Analytical Scalable Lumped-Element Model for GaN on Si Inductors

TABLE 3. Quality factor, inductance and relative error results for the measurements, EM simulations and model of all inductors.

results, it can be stated that the developed model can be [10] R.-J. Chan and J.-C. Guo, ‘‘Analysis and modeling of skin and proximity
applied for the estimation of the characteristics of an inductor effects for millimeter-wave inductors design in nanoscale Si CMOS,’’
in Proc. 9th Eur. Microw. Integr. Circuit Conf., Rome, Italy, Oct. 2014,
on a GaN on Si process like the D01GH process developed pp. 13–16, doi: 10.1109/EuMIC.2014.6997779.
by OMMIC. Further analyses on other technologies will be [11] J. Sathyasree, V. Vanukuru, D. Nair, and A. Chakravorty, ‘‘Com-
performed in the future to check if this model can be extended pact modeling of proximity effect in high-Q tapered spiral inductors,’’
IEEE Electron Device Lett., vol. 39, no. 4, pp. 588–590, Apr. 2018,
to other processes. doi: 10.1109/LED.2018.2809787.
[12] J. Sathyasree, V. Vanukuru, D. R. Nair, and A. Chakravorty, ‘‘A sub-
REFERENCES strate model for on-chip tapered spiral inductors with forward and reverse
excitations,’’ IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 802–805,
[1] J. R. Sendra, J. del Pino, A. Hernández, B. Gonzalez, J. Garcia,
Jan. 2019, doi: 10.1109/TED.2018.2873796.
A. Garcia-Alonso, and A. Nunez, ‘‘Integrated inductors modeling for
[13] F. Y. Huang, J. X. Lu, D. M. Jiang, X. C. Wang, and N. Jiang, ‘‘A novel ana-
library development and layout generation,’’ Analog Integr. Circuits Sig-
lytical approach to parameter extraction for on-chip spiral inductors taking
nal Process, vol. 35, nos. 2–3, pp. 121–132, May 2003, doi: 10.1023/
into account high-order parasitic effect,’’ Solid-State Electron., vol. 50,
A:1024122430963.
nos. 9–10, pp. 1557–1562, Sep. 2006, doi: 10.1016/j.sse.2006.07.018.
[2] F. M. Rotella, V. Blaschke, and D. Howard, ‘‘A broad-band scal-
able lumped-element inductor model using analytic expressions to [14] F. Huang, J. Lu, Y. Zhu, N. Jiang, X. Wang, and Y. Chi, ‘‘Effect of sub-
incorporate skin effect, substrate loss, and proximity effect,’’ in strate parasitic inductance on silicon-based transmission lines and on-chip
IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2003, pp. 471–474, inductors,’’ IEEE Electron Device Lett., vol. 28, no. 11, pp. 1025–1028,
doi: 10.1109/IEDM.2002.1175881. Nov. 2007, doi: 10.1109/LED.2007.906800.
[3] J. Gil and H. Shin, ‘‘Simple wide-band on-chip inductor model for [15] A. O. Adan, M. Fukumi, K. Higashi, T. Suyama, M. Miyamoto, and
silicon-based RF ICs,’’ in Int. Conf. Simul. Semiconductor Processes M. Hayashi, ‘‘Electromagnetic coupling effects in RFCMOS circuits,’’ in
Devices (SISPAD), Boston, MA, USA, Sep. 2003, pp. 35–38, doi: IEEE MTT-S Int. Microw. Symp. Dig., Seattle, WA, USA, vol. 1, Jun. 2002,
10.1109/SISPAD.2003.1233631. pp. 39–42, doi: 10.1109/MWSYM.2002.1011553.
[4] S. S. Mohan, M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, ‘‘Simple [16] J. Zheng, Y.-C. Hahm, V. K. Tripathi, and A. Weisshaar, ‘‘CAD-oriented
accurate expressions for planar spiral inductances,’’ IEEE J. Solid-State equivalent-circuit modeling of on-chip interconnects on lossy silicon sub-
Circuits, vol. 34, no. 10, pp. 1419–1424, Oct. 1999, doi: 10.1109/4.792620. strate,’’ IEEE Trans. Microw. Theory Techn., vol. 48, no. 9, pp. 1443–1451,
[5] J. M. Lopez-Villegas, J. Samitier, C. Cane, P. Losantos, and J. Bausells, Sep. 2000, doi: 10.1109/22.868993.
‘‘Improvement of the quality factor of RF integrated inductors by lay- [17] A. Goni, J. del Pino, B. Gonzalez, and A. Hernandez, ‘‘An analytical
out optimization,’’ IEEE Trans. Microw. Theory Techn., vol. 48, no. 1, model of electric substrate losses for planar spiral inductors on silicon,’’
pp. 76–83, Jan. 2000, doi: 10.1109/22.817474. IEEE Trans. Electron Devices, vol. 54, no. 3, pp. 546–553, Mar. 2007,
[6] V. N. R. Vanukuru and A. Chakravorty, ‘‘High-Q characteristics of doi: 10.1109/TED.2006.890366.
variable width inductors with reverse excitation,’’ IEEE Trans. Elec- [18] Y. Cao, R. A. Groves, X. Huang, N. D. Zamdmer, J. O. Plouchart,
tron Devices, vol. 61, no. 9, pp. 3350–3354, Sep. 2014, doi: 10.1109/ R. A. Wachnik, T. J. King, and C. Hu, ‘‘Frequency-independent
TED.2014.2340901. equivalent-circuit model for on-chip spiral inductors,’’ IEEE J.
[7] V. N. R. Vanukuru, ‘‘High-Q inductors utilizing thick metals and Solid-State Circuits, vol. 38, no. 3, pp. 419–426, Mar. 2003, doi:
dense-tapered spirals,’’ IEEE Trans. Electron Devices, vol. 62, no. 9, 10.1109/TED.2003.810474.
pp. 3095–3099, Sep. 2015, doi: 10.1109/TED.2015.2458772. [19] T. H. Lee, The Design of CMOS RF Integrated Circuits, 2nd ed. New York,
[8] F. Passos, M. H. Fino, and E. R. Moreno, ‘‘Fully analytical characterization NY, USA: Cambridge Univ. Press, 2006.
of the series inductance of tapered integrated inductors,’’ Int. J. Electron. [20] C. P. Yue and S. S. Wong, ‘‘Physical modeling of spiral inductors on
Telecommun., vol. 60, no. 1, pp. 65–69, Mar. 2014, doi: 10.2478/eletel- silicon,’’ IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 560–568,
2014-0007. Mar. 2000, doi: 10.1109/16.824729.
[9] J. N. Burghartz and B. Rejaei, ‘‘On the design of RF spiral inductors [21] H. Nishiyama and M. Nakamura, ‘‘Form and capacitance of parallel-plate
on silicon,’’ IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 718–729, capacitors,’’ IEEE Trans. Compon., Packag., Manuf. Technol. A, vol. 17,
Mar. 2003, doi: 10.1109/TED.2003.810474. no. 3, pp. 477–484, Sep. 1994, doi: 10.1109/22.868993.

52870 VOLUME 8, 2020

M. San Miguel Montesdeoca et al.: Analytical Scalable Lumped-Element Model for GaN on Si Inductors

MARIO SAN MIGUEL MONTESDEOCA JAVIER DEL PINO (Member, IEEE) received the
received the B.S. degree in telecommunications B.S., M.S., and Ph.D. degrees in electronics and
technologies engineering and the M.Eng. degree communication engineering from the University of
in telecommunications engineering from the Uni- Las Palmas de Gran Canaria, Spain, in 1996, 1997,
versity of Las Palmas de Gran Canaria, Spain, and 2002, respectively.
in 2014 and 2016, respectively, where he is cur- Since 1994, he has been with the Micro-
rently pursuing the Ph.D. degree, with his thesis electronic Technologic Division, Institute for
focusing on MMIC design for Ku and Ka band Applied Microelectronics (IUMA), University of
applications for SATCOM. Las Palmas de Gran Canaria. In 1998, he joined as
From 2014 to 2017, he was an Intern with an Associate Professor with the University of Las
the RFIC Group, Institute for Applied Microelectronics (IUMA), where Palmas de Gran Canaria, from 1998 to 2005, where he has been a Professor
he designed RFICs (low noise amplifiers, power amplifiers, and passive since 2005. In 2000 and 2002, he was an Invited Researcher with the Centro
mixers) for Zigbee applications. Since 2017, he has been working as a de Estudios e Investigaciones Técnicas de Guipúzcoa (CEIT), Spain, and in
RFIC/MMIC Design Engineer with Wireless Innovative MMIC (WIMMIC). the Fraunhofer Institute for Integrated Circuits, Germany, respectively. His
He has authored or coauthored ten publications in international journals group has made relevant contributions in the design RFICs and MMICs for
and conferences and tutorized two B.S. and one M.Sc. theses. His research different wireless communications standards and technologies. His group
interests include MMIC design in III-V technologies like GaN on Si also has demonstrated extensive experience in the modeling and optimiza-
or GaAs, and CMOS and BiCMOS RFICs design for SATCOM and tion of passive components such as varactors and inductors. His group has
5G applications. also helped develop integrated circuits for commercial applications. He has
authored or coauthored more than 150 publications in international journals,
conferences, and authored the book Design of Low-Noise Amplifiers for
Ultra-Wideband Communications (McGraw-Hill, 2014). He has graduated
six Ph.D. students. He currently leads a group of nine Ph.D. students and
postdoctoral Fellows.

SERGIO MATEOS ANGULO received the B.S.

degree in telecommunications technologies engi-
neering and the M.Sc. degree in telecommuni- JAVIER A. GARCÍA Y GARCÍA (Member, IEEE)
cations technologies from the University of Las received the M.S. degree in physics (specialized
Palmas de Gran Canaria, Spain, in 2015 and 2016, in electronics) from the University of Santiago de
respectively, where he is currently pursuing the Compostela, Spain, in 1993, and the Ph.D. degree
Ph.D. degree, with his thesis focusing on the in electronic engineering from the University of
design of radiation hardened-by-design radiofre- Las Palmas de Gran Canaria (ULPGC), Spain,
quency integrated circuits and the analysis of the in 2001.
effects caused by radiation in these circuits. He was an Invited Researcher with the Centro
From 2015 to 2019, he was an Intern with the RFIC Group, Insti- de Estudios e Investigaciones Técnicas de Guipúz-
tute for Applied Microelectronics (IUMA), where he designed RFICs coa (CEIT), Spain, and the Engineering School
(low noise amplifiers, passive mixers, and variable gain amplifiers) for (TECNUN), University of Navarra. Since 2003, he has been an Asso-
wireless sensor network applications. Since 2019, he has been work- ciate Professor with the Department of Electronic Engineering and Control,
ing as a RFIC/MMIC Design Engineer with Wireless Innovative MMIC ULPGC. He is currently a Researcher with the Institute for Applied Micro-
(WIMMIC). He has authored or coauthored 13 publications in interna- electronics (IUMA) involved in the Microelectronics Technology Division
tional journals and conferences. His research interests include MMIC (TME), ULPGC. He has authored or coauthored more than 60 publications in
design in III-V technologies like GaN on Si or GaAs, and CMOS international journals and conferences. His research interests include timing
and BiCMOS RFICs design for several applications, such as SATCOM and power consumption modeling, high-frequency integrated circuits for
and 5G. telecommunications, design, characterization and modeling of integrated
inductors and varactors, characterization, and modeling of GaN transistors.

SUNIL L. KHEMCHANDANI (Member, IEEE)

received the M.S. and Ph.D. degrees in electron-
DANIEL MAYOR DUARTE received the B.S. ics and communication engineering from the Uni-
degree in telecommunications technologies engi- versity of Las Palmas de Gran Canaria, Spain,
neering and the M.Sc. degree in telecommuni- in 2000 and 2007, respectively.
cations technologies from the University of Las Since 1998, he has been with the Research Insti-
Palmas de Gran Canaria, Spain, in 2016 and 2017, tute for Applied Microelectronics, University of
respectively, where he is currently pursuing the Las Palmas de Gran Canaria, where he was work-
Ph.D. degree, with his thesis focusing on the ing in RFIC for wireless LAN and GaAs IC’s for
design of high power amplifier based on GaAs and video and image processing. From 2001 to 2003,
GaN technologies. he was working in INCIDE Canary S.L, where he was involved in the
From 2015 to 2018, he was an Intern with the modeling of inductors in CMOS technology, designing of low noise ampli-
RFIC Group, Institute for Applied Microelectronics (IUMA), where he fiers for GPS applications, transimpedance amplifiers for SONET/SDH,
designed RFICs (low noise amplifiers, passive mixers, variable gain ampli- and phase-locked loops for MMDS. Since 2005, he has been an Associate
fiers, and filters) for wireless sensor network applications. Since 2018, he has Professor with the University of Las Palmas de Gran Canaria. He has
been working as a RFIC/MMIC Design Engineer with Wireless Innova- authored or coauthored more than 90 publications in international journals
tive MMIC (WIMMIC). He has authored or coauthored ten publications and conferences and authored the book Design of Low-Noise Amplifiers
in international journals and conferences. His research interests include for Ultra-Wideband Communications (McGraw-Hill, 2014). His research
MMIC design in III-V technologies like GaN on Si or GaAs, and CMOS interests include RFIC and MMIC circuits for wireless communications and
and BiCMOS RFICs design for several applications, such as SATCOM SATCOM.
and 5G.

VOLUME 8, 2020 52871