HEATHKIT CONTINUING EDUCATION petal Individual Learning Program MICROPROCESSORS Unit 7 INTERFACING — PART 1 EE-3401 HEATH COMPANY Copyright © 1977 BENTON HARBOR, MICHIGAN 49022 a ath Coeany pontine een7-2 UNIT SEVEN CONTENTS Introduction . . Unit Objectives ...... See Unit Activity Guide... Interfacing Fundamentals .............60.s00eceeeeee 7-6 interfacing with Random Access Memory ..............0000004 7-20 Interfacing with Displays... - 7-38 Interfacing Experiments - 7-50 Unit Examination.......0...0000.664 fecteeeees 781 Examination Answers .........00000c0ceeeseeessseeeeeeeees 7-53INTRODUCTION ‘As mentioned earlier, there are two things you can do with a micro- processor. You can program it and you can interface it with other circuits, By now you should be able to write simple programs without too much troubie. You will continue to learn new programming techniques as you progress through the course. However, in the remaining portions of the course, the emphasis will shift to interfacing the MPU with other circuits. Units 7 and 8 will give you enough general information to understand the interfacing experiments providing that you have a general knowledge of digital electronics. That is, these units are written on the assumption that you have training equivalent to that provided in the Heathkit Continuing Education, Individual Learning Program in Digital Electronics.7-4| ur seven toe UNIT OBJECTIVES When you have completed this unit, you should be able to: 1. Define 3-state logic and explain the need for it. 2. Explain the purpose of each of the control lines on the 6800 MPU. Explain the timing relationships between the clock signals and the information on the address, data, and R/W lines. Identify several different arrangements used in static RAMS. 5. Draw the logic diagram of a simple address decoder. 6. Explain the operation of a static RAM storage cell. 7. Show four different methods by which an MPU can drive 7-segment displays.att | 7-5 UNIT ACTIVITY GUIDE Read Section on Interfacing Fundamentals. C Complete Self-Test Review Questions 1 through 14. 1D Play Cassette Tape Section “Semiconductor Memories.” CD Read Section on Interfacing with Random Access Memory. CG Complete Self-Test Review Questions 15 through 28, Read Section on Interfacing with Displays. CD Complete Self-Test Review Questions 29 through 40. C Perform Interfacing Experiments 1 through 4. CO Complete Unit Examination. © Check Examination Answers.7-6 UNIT SEVEN INTERFACING FUNDAMENTALS Before going into specific interfacing examples, we must first discuss some fundamental concepts that will be used. First, we will discuss the concept of a bus and the need for 3-state logic. Then we will examine the various control and bus lines of the 6800 MPU. Finally, we will consider the various timing relationships involved in the execution of instruc- tions. Buses in computer jargon, a bus is generally defined es a group of conductors over which information is transferred from one place to another. In many cases, the information can originate from any one of several sources and can be transferred to any one of several destinations. Moreover, on some buses, information can be transferred in either of two directions. These are called bi-directional buses. Of course fora given bus, only one transfer of information can occur at a time. Figure 7-1 shows the data bus arrangement in a typical microcomputer application. Generally in thistype of system, all data transfers involve the MPU. Thus, data can be transferred in either direction between RAM and the MPU. However, other data transfers are one way only. Data can be transferred from ROM or the input buffer to the MPU. Also, data can be transferred from the MPU to the output latches a wus Figure 7-1 ‘Typical Data Bus Arrangement.KIT ‘CONTINUING ‘ucanion Inan arrangement like this, two problems arise. First, wemust insure that only one data transfer is attempted at any given time. This is done by assigning each destination or source a different address. For example, the RAM, ROM, output latches, and input buffers all have one or more chip enable pins. The proper logic levels on these pins will select or activate the circuit, By assigning each circuit a different address, we insure that only one circuit at a time is enabled. Figure 7-2 shows the addressing capability added to the block diagram. ‘An address decoder is added for each circuit. The inputs to the address decoders come from the MPU via the address bus. The outputs go to the chip enable lines of the various circuits. Since only one address can appear on the address bus at any given instant, only one of the external circuits will be enabled at a time. impo Figure 7-2 ‘Adding the Address Capability The memories are assigned many addresses since each byte must have its own address. For example, if a 512,9-byte RAM is used, it would probably be assigned addresses 0000,, through 01FF ys, When any one of these addresses appear on the address bus, the RAM is selected via its chip enable line. Notice that a portion of the address bus connects directly to the RAM. This selects the individual byte within the RAM.7-8| unr seven "eater In the same way, the ROM is assigned arange of addresses. Ifa 1024, byte ROM is used, it may be assigned addresses FC00,. through FFFF ,.. The ROM must be enabled whenever any of these addresses appear on the address bus. The output latch and input buffers are also assigned unique addresses. Thus, the MPU can communicate with any one of the external circuits simply by placing the proper address on the address bus. The second problem is more fundamental. It arises because of the basic 2-state nature of digital logic circuits. Recall that the output of a standard logic gate will always be either logic 1 (high) or logic 0 (low). The problem is: Which state should the outputs of the circuits that are con- nected to the data bus assume when they are not selected? Regardless of which state they assume, they interfere with the output of the enabled circuit. For example, if the output of the disabled circuits assume a high state, they interfere with the low output of the enabled circuit. In other words, one circuit tries to pull the bus line high while the other is trying to force it low. In the past, this problem has been overcome by using gates with open collector outputs. While open collector devices could be used to solve this problem in microprocessors, an entirely different approach is most often used. To understand how this problem is overcome, we must discuss 3-state logic. 3-State Logic ‘*urrst As the name implies, 3-state logic devices have a unique third state in addition to the normal 1 and 0 output. Figure 7-3 compares a standard A, stanonzo san-iaventing sueFeR non-inverting buffer with a 3-state, non-inverting buffer. ae oa Recall that a non-inverting buffer increases the current drive of the input wn — cvtror signal without changing the logic levels in any way. Thus, the output Bee may be able to drive ten times as many gates as the input. The standard ue buffer has one input and one output. The output always assumes the same B. ate stare logic level as the input. Because the input must be either 1 or 0, the output sanarincourtes must be the same. Figure 7-3 Comparison of standard and 3-state By contrast, the 3-state buffer has two inputs. In addition to the normal buffers." data input, the buffer has an enable/disable input. This input may be either logic 1 or logic 0 depending upon whether we wish to enable or disable the butfer. The buffer shown in Figure 7-3B is enabled by apply- ing logic 1 to the enable/disable input.EATHKIT When enabled, the 3-state buffer acts exactly like the standard buffer. The output will assume the same logic level as the data input. The 3-state buffer is disabled by applying logic 0 to the enable/disable input. When disabled, the output assumes a very high impedance state that is neither logic 1 nor logic 0. While in this high impedance state, the output can be assumed to be disconnected from the rest of the circuit. That is, when the buffer is disabled, its output will not interfere with the circuits to which it is connected There are many different types of 3-state devices available. Figure 7-4 shows four different types of 3-state buffers. The buffer shown in Figure 7-4A is the sameas that described above. It does not invert and is enabled by logic 1. Notice that the buffer shown in Figure 7-4B hasa small circleat the enable/disable input. This means that the buffer is enabled by a logic 0 and disabled by a logic 1. Figures 7-4C and D show inverting buffers. The first is enabled by a logic 1; the second is enabled by a logic 0. Generally, four or more 3-state buffers are included in a single integrated circuit. Figure 7-5 shows the 74126 type TTL IC, It contains four 3-state buffers in a single 14-pin dual-in-line package Figure 7-6 shows eight 3-state buffers in a single 20-pin package. The four lower buffers are enabled by a logic 0 at pin 1 of the IC, The four upper buffers are enabled by a logic 1 at pin 19. The input buffer shown earlier in Figures 7-1 and 7-2 could use this type of IC. Buffers of this type are often called bus extenders, line drivers, line receivers, etc., depending on how they are used. Figure 7-6 ‘The 74L8241 contains eight 2-state non-inverting buffers. Interacing — Patt | 7-9 Figure 7-4 Four types of 3-state buffers. Figure 7-5 ‘The 74126 IC contains four -stote buf- fers in a single 14-pin package7-10 | unit seven im abo qj q q q ba Gyre Pa Ga opm ayn ob qe oo as ofa oy. ofa as cepa cone Oe) Bn asf ce auf Te eb Figure 7-7 The 6800 and 688 MPU pin assignments, Fr}ecas Hf euwey — 4.c, Fata va vee Ess) While many different forms of 3-state buffers are available, many micro- processor support circuits do not require separate 3-state buffers. Most RAMS and ROMS have their own 3-state buffers built in. Thus, any time the RAM or ROM is not selected, it automatically goes to its third state. In this state, the outputs are said to be off, disconnected, disabled, floating, or in their high impedance state. The 6800 and 6808 MPU Interface Lines Before you can interface any microprocessor to its support circuits or to the outside world, you must become familiar with its pin assignments, control lines, etc, Figure 7-7 shows the pin assignments of the 6800 and 6808 MPU. Notice that the MPU is in a single 40-pin dual-in-line pack- age. Most of the pin assignments, as shown in Figure 7-7, are common to both the 6800 and 6808 microprocessors. There are six pin assignments that are not common, pin 3 and 35 through 39. The functions in parenthesis, are for the 6808. The functions on these same pins that have no paren- thesis are for the 6800 microprocessor. In the following description of the MPU interface lines, those common to both the 6800 and 6808 will be described first. Then those that apply to the individual MPU will be discussed under a separate heading. Notice that pins 9 through 20 and 22 through 25 make up the 16-bit address bus. These pins connect to 16 three-state output drivers in the MPU. Each driver is capable of driving one standard TTL load. When disabled, the address lines act as open circuits. This capability is some- times used to allow another device to gain control of the address bus. In this way, some external device can address memory. This is referred toas, “direct memory access” {DMA). Pins 26 through 33 are used for the 8-bit data bus. This is a bi-directional bus that is used to transfer data to and from memory and the input-output circuitry. You arealready familiar with four of the control lines: the read/write line, the reset line, the non-maskable interrupt, and the interrupt request line. The read/write (R/W) line tells the peripheral devices and memory whether the MPU is in the read or write mode. A read operation is indicated by a logic 1 on this line. In this mode, the MPU reads data from memory or from an input device. A write operation is indicated by a logic 0 on the R/W line. In this mode, the MPU sends data out to memory or an output device. Since it works hand-in-hand with the address bus, the R/W line has a 3-state capability.tntertacing — Pant + | 7-11 ‘The reset line (pin 40) was discussed in the previous unit. Recall that it is used to Teset and start the MPU when power is initially applied or at anytime that we wish to initialize the system. When this line goes to logic level 1, the MPU starts the reset sequence. Recail that the reset vector is retrieved from addresses FFFE,, and FFFF,s. This vector is loaded into the program counter so that the first instruction is fetched from that address. This capability is used to direct the MPU to the start of the monitor or control program. Thenon-maskable interrupt (NMI) was mentioned when interrupts were discussed. A high-to-low transition on pin 6 (the NMI line) will initiate the non-maskable interrupt sequence. Recall that this forces the MPU to pick up the NMI vector at addresses FFFC and FFFD. This vector is the address of the NMI service routine. ‘The interrupt request line (IRQ) was also discussed earlier. While this is similar to the non-maskable interrupt, there are three fundamental differ- ences. First, the IRQ signal is maskable; it will be ignored if the interrupt mask bit is set. Second, the IRQ sequence picks up the IRQ vector from addresses FFF8,, and FFF9,,. Third, the IRQ line (pin 4) is level sensitive. That is, a logic 0 on this pin causes the interrupt sequence. Compare thi to the NMI line which requires a logic 1-to-0 transition. The valid memory address (VMA) line is an output. It indicates to peripheral devices that the address on the address bus isa valid one. This signal is necessary because occasionally # false address will appear on. the address bus. The VMA signal is used to disable peripheral devices when the address is not valid. A logic 1 at pin 5 indicates that the address is valid and that the peripheral devices may respond accordingly. A logic 0 indicates that the address is not valid and that the peripheral devices should ignore the address. As you will see later, the VMA line is used in any decoding scheme. ‘The HALT line (pin 2) provides a hardware method of halting the MPU. If this input is forced low, the MPU will finish its present instruction, then. it will halt. When halted, all 3-state lines go to their off state. This effectively disconnects the MPU from the address and data buses. This line is sometimes used to implement single instruction operation. By controlling the HALT line. the MPU can be forced to stop after each instruction is executed. This can be a valuable aid in troubleshooting hardware and debugging programs. In many applications, the halt capa- bility is simply not required. In this case, the HALT line is permanently connected to +5 volts.7-12 UNIT SEVEN The final control line that is common to both the 6800 and 6808 micro- processors in identity and function is the bus available (BA) line. This output (pin 7) indicates whether or not the MPU is executing instruc- tions. Recall that the MPU may stop executing instructions for either of two reasons. First, the WAI instruction will cause the MPU to stop until an interrupt is received. Or, the MPU can be stopped by forcing the HALT line low. A logic 0 on the bus available line indicates that the MPU is running. A logic 1 indicates that the MPU has stopped. When the MPU is stopped, all 3-state outputs go to their off state. Thus, the MPU is effec- tively disconnected from the buses. The BA signal indicates that this condition exists by going to the logic 1 state, During this period the buses are available for other purposes such as DMA operations. ‘THE 6800 MPU INTERFACE LINES While you are not yet familiar with the remaining 10 pins of the 6800 MPU. five of them are self-explanatory. For example, two of them (pins 35 and 38) are not connected. Also, three of the pins are used for power. Pin8 is labeled V.<. This is the +5-volt supply. Pins 1 and 21 are labeled Vay These are ground pins. Notice that the 6800 MPU requires a single +S-volt supply. ‘The remaining five lines require a brief explanation. First. there are two clock signals labeled 61 (pronounced “phi one") and 42. A 2-phase non-overlapping clock is required. This must be provided to the MPU from some external clock generator. The details of the clock signal willbe discussed later. The normal clock frequency is 1 MHz, although higher speed versions of the 6800 MPU are also available. ‘The TSC line (pin 39) is used to enable or disable the 3-state address bus and the R/W line. which also has a 3-state capability. This input to the MPU is used in applications in which some external device must periodi- cally take over the address bus. Normally, the MPU has complete control of the address bus and read/write line. However, an external device can effectively disconnect the MPU from the address bus by switching the TSC line to the high state. When TSC goes high, the address bus and read/write line of the MPU go to their off or high impedance state, This allows the external device direct access to memory without going through the MPU. This is called direct memory access or DMA. In many applications, DMA operations are not required and TSC is permanently connected to ground.‘The data bus enable (DBE) line (pin 36) is the 3-state control line for the data bus. If this input to the MPU is forced low, the data bus will switch to its off or high impedance state. As you will see later, all data transfers between the MPU and memory take place when the #2 clock is high. For this reason, the DBE line is often connected to the $2 clock, ‘THE 6808 MPU INTERFACE LINES ‘The 6808 microprocessor has a total of five pins for power. Pins 8 and 35 are labeled V,,. This is the +5-volt supply. Pins 1, 21, and 36 are labeled Vu. These are ground pins. ‘The 6808 has an internal oscillator that may be crystal controlled. The crystal is connected between pins 38 and 39. These are designated as. XLAL and EXTAL on Figure 7-7. A divide-by-four circuit has been fabricated within the 6808 so that a 4 MHz crystal connected to pins 38 and 39 result ina 1 MHz output. This output (pin 37) is designated a ‘The 1 MHz output is similar to the 42 signal on the 6800 microprocessor. The Enable (E output) supplies the clock for peripheral devices. The final control line of the 6808 that we will consider is the memory ready (MR). This input (pin 3) isa control signal which allows stretching of the 1 MHz E output. When MR is high, E will bea normal pulse width. When MR is low, E may be stretched multiples of half periods. This feature allows for interfacing to slow memories. Intertacing — pant | 712.1oo inetacng — Pan 1| 7-13 Instruction Timing Before going further, the timing relationship between the various control and bus signals will be discussed. The discussion will start with the most basic timing relationship: the timing for a single instruction. The follow- ing discussion applies to both the 6800 and 6808 microprocessors. The only significant difference is where the $1 and 2 clocks are generated: internal to the 6808, external to the 6800. You should also keep in mind that 42 in the following discussion is the E output of the 6808. Figure 7-8 shows the 2-phase clock signals required by the micro- processor. These two clock signals control every single action that takes place in the MPU and its peripheral devices. To illustrate this, the sig- nificant events that occur during the fetch and execution of the LDA immediate instruction will be discussed. Recall that this is a 2-byte instruction. The first byte is the opcode (86s). The second byte is the number that is to be loaded into accumulator A. This instruction requires two MPU cycles. During the first cycle, the opcode is fetched and de- coded. During the second cycle, the operand is retrieved from memory and is placed in accumulator A. er Poa 7 Figure 7-8. Timing for the LDAA immediate in struction. The significant events are illustrated. Notice that the events occur at the edges of the clock pulses. Assume that, prior to time 1, the program counter contains the address of the LDAA immediate instruction. At time 1, the address is transferred from the program counter to the address bus via the memory address register. Notice that this occurs at the positive-going edge of the $1 clock. if the VMA and RIW lines are not already at logic 1, they will be switched to logic 1. A logic 1 on VMA indicates to memory that this is a valid address. A logic 1 on R/W indicates to memory that the MPU wishes to read the byte at the indicated address. Time 2 is the falling edge of the #1 clock. At this time, the program counter will be incremented by one to the address of the next byte in memory. However, this will not change the address on the address bus. Remember that this address is latched into the memory address register Thus, the output address is still that of the first byte of the LDAA instruc- tion, The events which occur during the 1 clock are initiated from within the MPU itself. In fact, in most systems, the #1 clock is applied only to the MPU. The 42 clock, on the other hand, is applied to the peripheral circuits as well as the MPU. Thus. the RAMs, ROMS, etc., are controlled by the #2 clock.7-14 | unit seven Sourmiunes ‘Time 3 is the rising edge of the 62 clock. This positive-going edge forces memory to place the data from the indicated address onto the data bus. Recall that this is the opcode for the LDAA immediate instruction or 86,.. Notice that the address has had from time 1 to time 3 to stabilize. Time 4 is the falling edge of the #2 clock. At this time, the MPU accepts the byte from the data bus. Notice that the data bus has from time 3 totime 4 to stabilize. The MPU transfers this byte (865) to the instruction regis- ter. There, it is decoded and is interpreted as an LDAA immediate op- code. This tells the MPU that the next byte in memory is the operand that is to be loaded into accumulator A. This completes the first MPU cycle. During this cycle, the opcode was simply read from memory and decoded. This corresponds to the fetch phase discussed earlier for our hypothetical MPU. Notice that an MPU. cycle corresponds to one cycle of the clock. Now let's see what happens during the second cycle or execute phase of the instruction. At time 5, the address of the operand is transferred from the program counter to the address bus. At time 6, the program counter is incremented by one in anticipation of the next fetch phase. At time 7, the rising edge of the 42 clock causes the operand to be transferred from memory to the data bus. At time, the operand is latched into the MPU where it is transferred to accumulator A. This completes the second MPU cycle and the execution phase of the instruction. Time 9 represents the start of the fetch phase for the next instruction. The LDAA immediate instruction required two MPU cycles or two cycles of the clock. Assuming a 1 MHz clock, two microseconds are required for this instruction.HeaTHOT Timing of Program Segment Now that you are familiar with the timing of a single instruction, several instructions will be put together to form a sample program. You can then study the timing relationships between the bus signals, clock signals, the R/W line, etc. Our sample program segment is shown in Figure 7-9. Using the im- mediate addressing mode, it loads 07, into accumulator A and adds 21,5. The result is then stored in location 0001. Notice that the first instruc- tion resides at address 0010, WeX | HEX | MNEMONICL ‘COMMENTS, ADDRESS | CONTENTS| HEX CONTENTS| tore > sta [rome enat Figure 7-9 ‘Sample program segment Figure 7-10 illustrates the timing relationships. At the top the 1 and 62 clock signals are shown. The information that appears on the buses and control lines for each clock period is shown at the bottom. This program. segment requires eight clock or MPU cycles. These are numbered one through eight. Next, you will see what happens during each of these cycles. pant | 7-15‘ADORESS eee aT eee arian eee eset re a eho ore a o wo | oa ” ov | “ore [a _) ve + : 1" ' 1 1 ° 1 i Figure 7-10 ‘Timing of sample program segment. Cycle 1. During the first cycle, the address of the LDAA# instruction (0010;,) is placed on the address bus. As a result, the opcode 86y. is read from that address and is picked up by the MPU. Since this was a read operation from a valid address, the VMA and R/W lines are at logic 1. The MPU decodes the opcode and recognizes that this is an LDAA# instruc- tion. Consequently, it knows that the next byte in memory is the operand that is to be loaded into the accumulator. During this cycle, the program counter was incremented to 0011, so that it now points at the operand. Cycle 2. This is the execution phase of the LDAA# instruction. The address of the operand (0011,.) is placed on the address bus. The operand (07,,) is read out on the data bus and is placed in accumulator A. In the process, the program counter is incremented to 0012... This completes the execute phase of the first instruction. Cycle 3. This is the fetch phase of the next instruction. The address (0012,¢ is placed on the address bus. The opcode et that address is read out and placed on the data bus. The MPU picks up the opcode, decodes it, and discovers that it is an ADDA¥ instruction. In the process, the program counter is incremented to 0013,4. Cycle 4. Here, the address 0013, is transferred to the address bus and the selected memory location is read out. Therefore, the operand 215 is, placed on the data bus. The operand is picked up by the MPU and is added to the contents of the accumulator. The sum 26x. is retained in accumulator A. The program counter is incremented to 00141Cycle 5. This is the fetch phase for the third instruction. The address (0014, is placed on the address bus. The opcode for STAA is read out and decoded. The MPU recognizes that the direct address mode is used. Thus, it will interpret the next byte in memory as the address at which the sum is to be stored. The program counter is incremented to 0015,¢. Cycle 6. Address 0015,, is placed on the address bus. Notice that the contents of this location is the address at which the sum is to be stored. Thus, 01 is read out on the data bus where it is picked up by the MPU. Becatise the MPU recognized that direct addressing is indicated, it as- sumes that the address at which the sum is to be stored is 0001. This address is retained in the MPU. The program counter is incremented to 0016 Cycle 7. During this cycle, the MPU prepares ta store the sum. To do this, it must transfer the address 0001,, to the address register. Also, it must transfer the sum from the accumulator to the data register. While this is happening, the MPU must refrain from all external data transfers. To prevent unwanted data transfers, the MPU switches the VMA line low. This tells all peripheral devices that the address is not a valid one and that no data transfers should be initiated. Thus, the peripheral devices simply ignore the data and address buses for this cycle. Cycles. The MPU is now ready to store the sum in memory. The address at which the sum is to be stored (0001 ,) is placed on the address bus. The data to be stored (28) is placed on the data bus. The VMA line is switched high, indicating that this is a valid address. The R/W line is switched low, indicating that this is a store operation. Thus, the sum (28,.) is stored away in memory location 0001,5 Of course, the computer does not stop here. During the next cycle, the next instruction is fetched and decoded. However, the eight machine cycles illustrated above should give you the idea. As you will see later, the timing relationships shown here become important when we inter- face the MPU with memory or 1/O circuitry. The 6800 and 6808 Data Sheets The preceding section has given you some information on the control Jinesand timing relationships of both microprocessors, but you may have some questions that have not been answered here. For this reason, a detailed data sheet on these microprocessors is included in Appendix B of this course. It explains in more technical language the capabilities of the microprocessors. At this point in your study. you should have little trouble understanding these data sheets. You may want to refer to these data sheets if you have a question that is not answered in the text7-18 | uni seven pone Self-Test Review 1. What is a 3-state logic gate? 2. How is the non-inverting buffer shown in Figure 7-4 switched to its high impedance state? 3. Inthe6800 MPU, how can theaddress bus be forced to the off state? 4. How can the data bus be forced to its off state? 5. What does a logic 0 on the VMA. 1e indicate? 6. ‘What does a logic 1 on the BA line indicate? 7. How can the MPU be stopped by hardware? 8. _ Howdoes the MPU indicate that it wishes to store data in memory? List three ways in which an interrupt request differs from a non- maskable interrupt 10. The following isa list of the MPU's buses and control lines. Charac- terize each as either input, output, bidirectional, or internally gen- erated, Halt —____ RW =as ¢ 6800 6808 DBE a IRQ ———————— 2 —— VMA See te eee BA NM. Address Bus Reset ——___ Data Bus E Pepe SSeS ee 11. Inreference to the clock signals, when is a new address placed on the address bus? 12, When is the program counter incremented? 13, When does memory place data on the address bus? 14. When does the MPU pick up or latch in data that is on the data bus?HEATHKIT 7-19 ‘COMTI: ‘ucanion = Interfacing — Part 1 Answers A gate which has an off state in addition to the normal logic 1 and logic 0 states. By applying a logic 0 to the enable/disable input. By applying a logic 1 to the 3-state control (TSC) line. By applying a logic 0 to the data bus enable (DBE) line. That the address is not valid and should be ignored. That the MPU has halted. By applying a logic level 0 to the HALT input. By switching the R/W line to low. First, the interrupt request is maskable; NMI is not. Second, IRQ is level sensitive; NMI is edge sensitive. Third, IRQ uses the interrupt vector at address FFF8,, and FFF94¢, while NMI uses the vector at FFFC,, and FFFD ys. HALT — input RW — output 61 6800 input 6808 internal DBE — input IRQ — input 2 — input vMA — output TSC — input BA — output NMI — input Address Bus — output Reset — input Data Bus — bi-directional © — output, internal On the rising edge of the 61 clock. On the falling edge of the #1 clock. ‘On the rising edge of the 2 clock. On the falling edge of the 62 clock.7-20 | unr>r seven coun INTERFACING WITH RANDOM ACCESS MEMORY The Cassette tape segment entitled “Semiconductor Memories” is an excellent overview of the types of memories encountered in micro- processor applications. If you have not already done so, you should complete this audio-visual activity at this time. As shown in the audio-visual presentation, there are several different types of semiconductor memories. Today, the most popular type of mem- ory used with microprocessors is the static RAM. Recall that aRAM isa random access read/write memory. The static RAM uses bistable flip-flops to store data. Because the data is latched in these iE flip-flops. no refresh circuitry is required. That is, data can be maintained indefinitely without refreshing as long as power is applied. Many different types of static RAMs are available. The smaller static RAMs use the bipolar TTL technique. Most of the larger RAMs use either MOS or CMOS technology. One of the most popular sizes of static RAMs is 1024 bits. This size RAM is packaged ina single IC having from 16 to24 pins. Internally, the 1024 memory cells may be arranged as 128 8-bit words. Thus, a microprocessor system that requires 512 bytes of RAM would require four of these IC's. IC’s of this type require eight pins as data lines. For this reason, 24-pin packages are often used. Since price is related to package size, a RAM of this type is often more expensive than a a RAM that uses a smaller package. A more popular scheme is to arrange the 1024 memory cells into 256 - four-bit words. With this arrangement, only four data pins are required. Since the microprocessor works with 8-bit words, two of these RAMs must be used to form a 256 by 8-bit memory. As before, four packages are + required to form the 512-byte memory. However, the four packages tend to be smaller and probably less expensive. Another popular arrangement is the 1024 by 1-bit RAM. This scheme uses only one data line per package. Of course, eight of these packages must be used to form 8-bit bytes. Also, a problem arises if we wish to have ~ a memory smaller than 1024 by 8.The Static Ram Storage Cell The basic storage cell for an MOS type static RAM is shown in Figure 7-11. Keep in mind that this cell stores a single bit of data. There may be 1024 of these along with address decoders and bus drivers in a single IC. Lp aH see: Pete tT Figure 7-11 The static RAM storage cell The storage cell itself consists of the six MOS transistors. In keeping with current convention, the simplified symbol for the MOS transistor is used. Assume that these are N-channel enhancement type MOSFETs. Recall that an enhancement type MOSFET is normally off or non-conducting. However, since these are N-channel devices, they can bemadeto conduct by placing a positive voltage on the gate terminal. That is, when the gate is near ground potential, the transistor is off and represents a very high impedance. But, when the gate is high (near +V..), the transistor con- ducts and has a much lower impedance. If you keep these points in mind, the operation of the cell is easy to understand. Intertacing Par 1 7-217-22 UNIT SEVEN Transistors Q, and Q, are cross coupled so that they form a bistable latch or flip-flop. The bit of data is stored in this latch. Q, and Q, act as load resistors for Q, and Q, respectively. MOSFETs are used instead of phys- ical resistors because they take up less chip space. Qs and Q, act as switches which connect input data to the latch during write operations. Also, they connect the data in the latch to the output sense amplifier during read operations. The word select line is connected to the gates of Quand Q,.A logic 1 on the word select line will turn Q,and Q, on. A logic 0 will keep them turned off. Since this is a RAM storage cell, we must be able to write into it and to read from it. The following discussion will show how we write into it. Write Operation. Before writing a bit of data into the cell, the discus- sion will first define what constitutes a 1 and 0. Assume that the latch contains a binary 1 when Q, conducts and Q, is cut off. And, of course, contains a binary 0 when Q, conducts and Q, is cut off. When power is initially applied, the flip-flop will latch in one condition or the other but we can never be sure of which. We write data into the cell input, and word select lines. To store a binary 1, we place a logic 1 (a positive voltage) at the input line. The input line is always the opposite state of the input line, so it will go to logic 0 (~0 volts). The binary 1 is now stored by momentarily applying a logic 1 (positive pulse) to the word select line. A positive pulse on the word select line will turn switches Q, and Q, on. Thus, the positive voltage on the input line is applied through Q, to the gate of Q.. This forces Q. to conduct. When Q, conducts, its drain voltage falls toa low value. This reduced voltage is felt on the gate of Q,, cutting Q, off. When Q, cuts off, its drain voltage goes high. This increased voltage is felt on the gate of Qs, holding Q, in the on state.agatar imeracng—Pan : | 7-23 When the word select line returns to logic 0, Q, and Q, cut off. However, the conduction of Q, keeps Q, cut off and the high drain voltage of Q, keeps Q, conducting. Thus, the binary 1 is latched in the flip-flop. It will remain there until power is removed or until a binary 0 is deliberately written in. ‘We can later write in a 0 if we like by applying a logic 0 to the input, a logic 1 to input and then pulsing the word select line. When the ward select line goes high, Q, conducts, applying the logic 1 from Input to the gate of Q;. This tends to bring Q, out of cutoff. At the same time, Qs conducts, applying the logic from the input to the gate of Qs. This tends to cut off Q,. As you can see, the flip-flop latches in the opposite state. This represents a binary 0. The sense amplifier and output line (shown at the bottom) are disabled during this period by the read/write line (not shown), Read Operation. The input and input lines are 3-state lines that are enabled or disabled by the read/write line. When the read/write line (not shown) is high, the input and input lines are effectively disconnected. During this period, we can tead data from the storage cell by pulsing the word select line. Assume that the cell is presently storing a logic 1. This means that Q, is cut off and that Q, is conducting. Consequently Q,'s drain voltage is high (logic 1) while Q.'s drain voltage is low. When the word select line swings high, Q, conducts, connecting the high voltage at the drain of Q, to the left input of the sense amplifier. At the same time, Q conducts, connecting the low voltage at the drain of Q, to the right input of the sense amplifier. The sense amplifier interprets this as a logic 1 condition and sets the output line accordingly. If the flip-flop contains a logic 0 when the word select pulse occurs, the right input of the sense amplifier receives the higher voltage while the left input receives the lower. The sense amplifier interprets this as a logic 0.7-24 | unr seven cover A 128-Word by 8-Bit Ram Because a storage cell can store only one bit of information, large num- bers of these cells are required to form useful memory sizes. Figure 7-12 shows how 1024 cells can be erranged to form 128-word by 8-bit RAM. Each of the squares represents one of the 6-transistor cells just discussed. ‘The word select lines are shown entering on the left. While only four are shown, there would actually be 128 of these lines — one for each word. Notice that word select line 00 connects to each of eight storage cells across the top of the figure. In an actual system, these eight storage cells might make up the 8-bit byte we call memory location 00006. The input lines are shown at the top of the diagram. For simplicity, only four of the eight lines are shown. Notice that each input line is inverted so that complement inputs can be applied to each cell. Although the details are not shown, both the input and Tnput lines are 3-state lines so that they are effectively disconnected except during a write operation. The output lines are shown at the bottom of the diagram. These lines are disabled during a write operation but they are enabled during a read operation. One sense amplifier is required for each output line. Keep in mind that Figure 7-12 does not show the complete RAM. It merely shows the memory storage matrix and the sense amplifiers. Some additional circuits are required to turn this into a working RAM. One of these is an address decoder. The memory array is arranged as 128 bytes. An address decoder is required that can select any of these 128, 8-bit storage locations. Thus, a 1 of 128 decoder is required. The input to the decoder is the seven address lines from the MPU. Recall that seven bits can specify 128 different addresses.Ce Inetacing — Par 1 | 7-25 = 7 “o oof i yi A, i. 7 t T L T= EEE Poe eee <4 ~< nf ir [ Figure 7-12 Here 1024 storage cells are arranged to form 2 128-byte by 6-bit RAM.7-26 UNIT SEVEN HEATHKIT CONTINUING ‘The address decoder is made up of 128 7-input AND gates. A simplified gram is shown in Figure 7-13. Here, only three gates are shown — the first two and the last. Word select line 00 should go high when address lines A, through A, are all low. Notice that seven inverters are used to form A, through Ay. Notice also, that these complements are the inputs to the top AND gate. If A, through A, areail low, then N, through A; must be all high. Consequently, the output of the AND gate goes high. Thus, word select line 00 is selected when the low order address is 0000000. 3 = 7 i ae Figure 7-13, ‘The 1 of 128 address decoder. The 01 select line is sctivated when the address is 0000001., The next 125,» gates are not shown. Word select line i27,, is selected when Ay through A, are all high. Thus, it is activated when the address is 11111, Most RAMs do not have separate input and output ines. Instead they have data lines which can serve either as inputs or outputs. This is possible because the MPU cannot read and write data simultaneeusly.Figure 7-14 shows a simplified arrangement. The data lines are shown on the left. The 3-state input buffers are enabled by a high signal on the WRITE line. This line is controlled by the R/W signal and the chip enable (CE) signal. As you will see, the WRITE line is high when the MPU is writing data into memory. This enables the input buffers and allows data to be written into the selected address. The output buffers are disabled during this period by the low signal on the READ line. Pitt it wut ge we ee DDO ourrut aes Elo ee sais att | 7-27 Interfacing Ete Eee = When data is to be read from the RAM, the READ line is switched high and the WRITE line is switched low. This disables the input buffers and enables the output buffers. Thus, the data at the selected address is read out and placed on the data bus. As Figure 7-14 illustrates, the READ and WRITE signals are controlled by the chip enable (CE) signal and the R/W line. The CE input line is switched high when this particular memory chip is selected. If this line is. low, gates 1 and 2 are disabled. This causes both the READ and WRITE signals to go low, disabling both the input and output buffers. In effect, it disconnects this chip from the data bus. Figure 7-14 This RAM has bidirectional data lines.7-28 | unm seven ooo However, when CE is high, the R/W line controls the READ and WRITE signals. This R/W line is connected to the R/W line of the MPU. Recall that the R/W line is low when the MPU is writing data intoRAM, and high when the MPU is reading from RAM. When R/W is high, the output of gate 2 goes high, enabling the output buffers. The output of gate 1 is held low, disabling the input buffers. This places the RAM in the read mode. ‘When R/W goes low, the output of gate 1 goes high and the output of gate 2 goes low. This places the RAM in the write mode. Some RAMs have a single chip enable line. In many RAMs, the chip enable line is labeled CE, meaning that the chip is selected when the enable line is low. Some RAMs have several chip enable (CE) or chip select (CS) lines. Figure 7-15 shows a 128 by 6 RAM that is designed to be used with the 6800 MPU. As shown in the simplified block diagram, this RAM has six chip select lines. The large number of chip selects allows this RAM to be used with little or no external address decoding. As shown in the pin assignment diagram, a 24-pin package is tequired. This RAM is called the 6810. Data sheets on this device are included in Appendix B of this course. ae come eae Figure 7-15 ‘The 6810 is a 128-byte by @-bit RAM,Heer 7-29 Interfacing — Part + A 256 by 4-Bit Ram Figure 7-16 shows the block diagram of a popular 256 by 4-bit static RAM. In B-bit systems, two of these would be required to form a 256,. byte memory. Like the 128,.by 8 RAM, this circuit has 1024,,storage cells. To simplify theaddress decoders, the cells are arranged in 32 rows of 32 cells each. The 32 cells in each row are further divided into 8 columns of 4 bits each. Thus, the array consists of 32 rows by 8 columns by 4 bits (or 256 by 4 bits). ‘Two address decoders are used. The row select decoder is a 1-of-32 decoder which chooses the row. Five address lines (A, through A,) are used to specify the proper row. A 1-of-8 column decoder is used to select the proper column. Three address lines (A; through A;) are used to specify the proper column. The selected 4-bit word is at the point where the row and column lines intersect. woe eee] |_| Figure 7-16 Block Diagram of a 256 by 4 RAM.In this particular IC, the data lines are called I/O lines. The R/W line determines whether the IC is in the read or write mode. The CE line determines if this particular IC has been selected. If you count the pins shown and add one for Vee and another for ground, you will see thata = — 16-pin package is required, Figure 7-17 shows the pin assignments and logic diagram of the popular 2112 static RAM. It has the same general arrangement as that shown in the block diagram. ee dq“ ef ~@ —qe Figure 7~ Pin assignments and logic symbol for the 2122 static RAM. - Connecting Ram to the MPU Figure 7-18 is a partial schematic of a 6800 based microprocessor system. ‘Two 2112 IC's are used as a 256,y-by-8 RAM. Although not shown, the address and data buses from the MPU arealso connectedtoaROM, input _. and output circuits, and possibly additional RAMs. The MPU can com- municate with only one of these devices at any onetime. To communicate with the two 2112 ICs, the MPU must first select them by switching their CE lines low. Notice that the CE lines are connected to the output of the RAM address decoder. This decoder monitors the eight high-order ad- dress lines. When the address of the RAM appears on theselines,thetwo 2112 chips are enabled.Hea inertacing —ean | 7-31 a Figure 7-18 Partial schematic of 9 6800 based mi- croprocessor using two 2112 static = RAMs. ‘The two 2112 IC’s make up a 256 by &-bit RAM. IC1 connects to the four least significant bits of the data bus (D, through D;), while IC2 connects to the four most significant bits. Thus, when a byte of data is stored in the RAM, the four LSB’s go in [C1, while the four MSB's go in IC2. This is possible because the two IC’s are enabled at the same time. Notice that the address, CE, and R/W lines of the two {Cs are tied together. The address lines of the IC's monitor the A, through A, lines from the MPU, Once the chips are enabled, any one of the 256 memory locations can be selected by placing the proper address on the lower eight address lines.7-32 | un seven Sone : Address Decoding The 256,«-byte RAM must be assigned some starting address. In 6800- ee based systems, a common practice is to assign RAM the lowest addresses. Thus, a256,.-byte RAM would be given address 0000,, through OOF F,,.In binary, these are addresses 0000 0000 0000 0000; through 0000 0000 1111 11112, Notice that the eight LSB’s can specify any one of the 2564 memory locations. However, itis the upper eight bits that specify that the starting address is at the low end of memory. That is, the RAM must be — enabled when the upper eight bits of the address bus are 0000 0000. In Figure 7-18, the RAM address decoder monitors the upper eightbitsof = — the address bus. When this decoder finds that the upper eight bits are all zeros, it switches the CE line low, enabling the RAM. However, notice that VMA and the 2 clock signals are also applied to the decoder. Recall — that VMA is 1 when the address is valid. Thus, the decoder must also monitor the VMA line, since the RAM should not be enabled unless the address is valid. Recall also that the MPU must receive and transmit data. =~ only while the 92 clock is at logic 1. Thus, the decoder also monitors the 92 clock. If the high-order address lines are all zeros, the VMA line is high, and the 92 clock is high, the RAM will be enabled. — The address decoder can be any type of logic circuit that meets the above requirements. A typical circuit is shown in Figure 7-19. If you trace =~ through the various logic levels, you will see that CE is low only when Ay through A,, are low and VMA and 2 are high. NAND gate 1 produces a low at its output when VMA and 92 are high. The other inputs toNOR =~ gate 2 and the inputs to NOR gates 3 and 4 are low when the high-order address is 0000 00002. The three NOR gates produce high outputs. Thus, the inputs to NAND gate 5 are all high. This forces the output of gate5 — low. As you can see, this circuit fulfills the requirements of the address decoder. Figure 7-19 ne Address decoder using discrete logic gates.A memory location in the RAM shown in Figure 7-18 is selected by all 16 address lines. The low-order address lines connect directly to the RAM IC’s, while the high-order lines connect to the RAM address decoder. Thus, each memory location in RAM has only oneaddress. The addresses are said to be fully decoded. We can save some decoding logic by only partially decoding the address. Figure 7-20 shows an address decoder that monitors only two of the address lines (A,, and A,,). If you trace the logic levels through, you will see that CE is low any time that A,, and A,, are low and VMA and 92 are high. A,, and A,, will be low for any address at or below 3FFF,. Ifthe CE lineis used to enablea RAM that has fewer than 3FFF , bytes, some of the addresses will be duplicated. To illustrate this point, assume that we replace the address decoder shown in Figure 7-18 with the circuit shown. in Figure 7-20. Memory location 0000, can be selected by placing ad- dress 0000,, on the address bus. However, location 0000,, is also selected when 0900,« is placed on the address bus. The reason for this is that the RAM is enabled because A,, and A,, are low. And, the lowest address in the RAM is read out because A, through A, are low. Actually, there are dozens of addresses that will select any given location. For example, addresses 3F00;¢, 2700,2, 1C00;., and many others will all select memory location 0000,.. This is the price that must be paid for saving a few gates in the address decoder. igure 7-20 We can save gates by only partially decoding the address. In practice, this does not actually causemany problems. All we havedone is sacrifice the lower 16,384» addresses to 256» bytes of RAM. However, this still leaves three-fourths of the 65 K of addresses untouched. In most cases, this leaves more than enough addresses for I/O devices, ROMs, etc. The fact that a given byte of data appears at several addresses is also no problem as long as we remember this limitation in our programming. Partial decoding schemes are frequently used because they save decod- ing logic.[aT 7-34 | unr seven ‘eran Self-Test Review 15. 16. 17. 18. 19. 20. a1. 22, 23. 24, 25. 26. 27. 28. List three common arrangements for a 1024-bit static RAM. Using 256 by 4-bit static RAMs, what is the smallest 8-bit RAM possible? ‘What is the advantage of using two 256 by 4-bit RAMS to form 256 by 8-bit memory rather than using two 128 by 8-bit RAMs. How many bits of data can be stored in the circuit shown in Figure 7-al? Explain how data is written into this circuit. Explain how data is read from this circuit. Refer to Figure 7-13. Which address lines would connect to the input of the AND gate that drives word select line 02? Refer to Figure 7-14. What is the state of the input and output buffers if CE is low? ‘When CE is high and 8/Wis low, the circuit shown in Figure 7-14 is in the _____- state. Inaddition to some address lines, what other signals are connected to an address decoder in a 6800-based microcomputer system? How is the 2112 static RAM enabled? Refer to Figure 7- low? '9. What conditions must bemet beforeCE will go ‘What is the advantage and disadvantage of only partially decoding an address? When each byte of memory has one and only one address, the memory is said to be decoded.‘CONTINUING Intertacing — Pans | 7-35 Answers 15. 16, 17. 1B. 19. 20. 21. 22, 23, 24, 25. 26. 27. 28. The most common arrangements for a 1024-bit static RAM are: 1024 by 1-bit 256 by 4-bits 128 by 8. 256 by 8-bits. Because the 128 by 8-bit RAM requires 8 data lines, it uses a larger and usually more expensive package. Only one at a time. The input data bit sets the INPUT and INPUT lines to the proper complementary states, then the word select iine is pulsed high. ‘This turns Q, and Q, on connecting the inputs to the flip-flop. This sets or resets the flip-flop to the proper state. The two input lines are tri-stated. The word select line is pulsed high turning on Q, and Q,. This connects the outputs of the flip- flop to the sense amplifier. In turn, the sense amplifier sets the data line to the proper state. “Ro, Ass Bay Aa, Aa, As, and Ay, Both the input and output buffers are disabled. Write. ‘The VMA line and the 92 clock signal. The 2112 staticRAM is enabled by applying a logic 0 tothe CEline. VMA and g2 must be high. At the same time, address lines Ag through Ay, must be low. ‘The advantage is that generally fewer logic gates are required, The disadvantages are that it wastes addresses and that a given byte of data may be accessed at several different addresses, Fully.7-36 | unr seven INTERFACING WITH DISPLAYS One of the most popular output devices used with the microprocessor is the 7-segment LED display. It can be used to display the decimal digits 0 through 9 or the hexadecimal digits 0 through F. It can also display many special characters. Its low cost and flexibility make the 7-segment LED display ideal for low cost microprocessor based systems. The 7-Segment Display The 7-segment display consists of seven LED's arranged in the pattern shown in Figure 7-21A. An eighth LED is generally included to act as a decimal point. By lighting the LED's in different combinations, 256, patterns are possible. These range from a blank display (all segments off) tothe digit 8 with a decimal point (all segments on). Figure 7-21B shows some of the patterns that can be formed. B. igh bis kD la Figure 7-21 ‘The 7-segment display can be used to form many numerals, let rs, and sym- bolsEe Inertacing —Pan 1 | 7-37 ‘Two types of 7-segment displays are popular. One is called the common- anode type. As shown in Figure 7-22A, the anodes of the eight light- emitting diodes are tied together and connected to +V... A diode is forward biased (turned on) by applying a low logic level to its cathode. ‘An external series resistor is required to reduce the current to an accept- able level. The other type is called the common-cathode type. As Figure 7-228 illustrates, the cathodes are tied together and connected to ground. In this, case, a diode is forward biased (turned on) by applying a high logic level to its anode. Driving the 7-Segment Display A number of IC’s are especially designed to drive the 7-segment display. Atypical example is the 7447 shown in Figure 7-23A. This is a BCD-to-7- segment decoder-driver. It receives a 4-bit binary number at inputs A, B, C,and D. It provides the proper patterns at outputs through gto form the numerals 0 through 9 and six special characters as shown in Figure 7-238. FARM . , pots Seen ia ai ito oe a Figure 7-23 ‘The 7447 seven segment decoder- driver and its resultant displays. Aura Figure 7-22 ‘Two types of 7-sogment displays.7-38 | unrrseven ce When used with a microprocessor, the MPU does not drive the decoder- driver directly. Recall that the information on the data bus is there for a microsecond or less. Since the 7447 has no latch capability, a separate latch must be used to store the data at the right instant. Figure 7-24 shows a representative circuit vite ggg fie BS ee i Hae . EE, sf 0—| © Sect B © He, - aa tooo Figure 7-24 Using the decoder(driver. Here a 4-bit bistable latch is used between the data bus and the decoder- driver. The latch is enabled only at the instant that its address appears on the address bus. For example, assume that the latch has been given the = address 8000... An instruction such as STAA 8000, will activate the display. When this instruction is executed, the address 8000 is placed on the address bus. The address decoder recognizes this address and enables s the latch. Thus, the data on lines D, through D, are latched into the 4-bit latch. An instant later, the MPU places new information on the address and data buses. However, the display responds only to what has been preserved in the 4-bit latch. ‘The advantage of this circuit is that it requires only one instruction from a the MPU to display a given number indefinitely. Its disadvantage is its lack of flexibility. Of the 256,, displays possible, only the 164» provided by the decoder-driver can be used. Thus, this arrangement can display only those symbols shown in Figure 7-23B.A more versatile way of driving a 7-segment display is shown in Figure 7-25, Here, a low current display is used so that the latch can drive the display directly. Notice that the BCD-to-7-segment decoder is eliminated. The seven segments of the display (and the decimal point) are now controlled directly by the eight bits of data on the data bus. oti = a0nnessf gnoness [> Figure 7-25 FROm ae A more versatile way of driving a 7-segment display. The display shown is a common-cathode type. Thus, a segment is turned on by applying a logic high to its input. Figure 7-28 shows the 8-bit pattern that is required to display the digit 1. Since this 8-bit pattera comes from the MPU, the microprocessor must do the decoding. This requires more MPU time and instructions but it greatly increases the versatility of the display. We can now use any of the 256,» possible displays by providing the proper 8-bit pattern. Dpe be de tg ofo]i[iJofoloo. — f tok i 3 i Figure 7-26 Each bit controls one segment of the display.A display of this type is often used to display the hexadecimal digits 0 through F. The MPU must convert the binary numbers 0000 through 1111 into the proper 8-bit patterns to display the equivalent hexadecimal digit. The easiest way to do this is to use a “look-up” table. The 8-bit patterns are placed in 16, consecutive memory locations. Assume that the start. ing address of the table is FF96,, as shown in Figure 7-27. Wex_]_neX MNEMONICI [ADDRESS | CONTENTS ‘CONTENTS, COMMENTS, a 7 STAR Seba bnty nbn ‘ore ce ox Tenn raptor core s o Shee os & ot Congres ign oy 7 sna Siren raronen, ou = i ‘oa ta o.apeserg | nextmstmuction rs ® Orr 1110 | regen gatem 0 far 3 8011 9009 | FSopnen seren tort oe ® St 191809 | Peon perme? ese ° Sit 1001 | 7Seomen seren'ers rea 3 Gort oot1 | tSemengaumis reo 3 Stor tort | rsemocsaten os free + Grortstt | rsopmetpaem re Bo » S131 0000. | rSogmee pan tr? reve Ed Stisases | rsopmee panama Free % Soir tors | Pogue banen 8 Fox ™ Srry anes | Sopneasann tera Fear @ Soar titi | tSagmem saten 8 Fea a S100 1140 | tSapment autem ic fea ° oort 110% | tSemmnpumm io fm o Stag ti tt | FSkpen sammie ras o Siooortt | psagnonsanemiar® Figure 7-27 Program segment and table for con- verting binary to 7-segment display format.HEATH A program segment is required that will store the proper 7-segment pattern in the latches shown in Figure 7-25. Assume that the address of the latches is 8000;.. The program segment might look like that shown in Figure 7-27. ‘The program assumes that the binary number we wish to convert to its 7-segment hexadecimal equivalent is in accumulator A. The first instruc- tion stores the binary number at address 0016,.. Assume that the number is 0000 0110, or 06,.. Thus, this number is stored at address 0016,.. Notice that this number becomes the offset for the LDAA, X instruction at address 0015s The second instruction loads the starting address of the table (FF96,.) into the index register. Then, accumulator A is loaded using indexed addressing. The offset, which is now 06,¢, (by virtue of the first instruc- tion) is added to the contents of the index register (FF96,,) to form the address of the operand (FF9C;.). Thus, the number at address FF9C,s is loaded into accumulator A. This number is 5Fy., which is the proper 7-segment code to form the numeral 6. Finally, this number is stored at address 8000,g. This is the address of the latches that drive the display. Therefore, if 06,gis in accumulator A when this program segment is executed, the digit 6 will be displayed. Also, if 024s is initially in accumulator A, the program segment will cause a2 to be displayed. Using this arrangement, two 4-bit latches are required for each display. There are eight bit latches available in a single IC. However, most comein 20 to 24-pin packages, which are relatively expensive. There is one type of 8-bit latch that comes in a 16-pin package. This device will be dis- cussed next.7-42 | unit seven TDUCATION Using an Addressable Latch Figure 7-28 shows the pin outs and schematic for the 8-bit addressable latch. It can store an 8-bit byte and drive a low current display. Its most striking characteristic is that data is entered into the device in serial form. Thatiis, thasa single data input (pin 13). Thus, the eight bits of data must, be entered into the device one bit at a time. This explains how the IC can get by with only 16 pins. Figure 7-28 Pin outs and schematic diagram of the 7418289 latch. ‘The addressable latch has an enable pin that allows it tobe selected by an address decoder. A low at pin 14 will enable the latch and allow it to receive data. Actually, there are eight latches on the IC. They are num- bered 0 through 7. The particular latch to which the input data bit is routed is determined by the 3-bit address at pins Ay, A,, and A;. Figure 7-29 shows which latch is selected for each address. ‘ADORESS INPUTS Latcn a a «| selecreo Figure 7-29. Latch selection table.How can this latch be used by the microprocessor to drive a display? Figure 7-30 shows a representative circuit. The three address lines on the addressable latch are connected to their corresponding lines on the address bus. The remaining lines of the address bus are connected to the address decoder. Assume that the address decoder is arranged so that the addressable latch is enabled for addresses C160,, through C167». That is, the addressable latch is enabled for eight different addresses. Address C1604, selects latch 0 of the addressable latch; C1614, selects latch 1; and so forth. Figure 7-30. Using the addressable latch to drive @ 7-sogment display, The only data line connected to the addressable latch is D, from the microprocessor’s data bus. The outputs of the eight latches (Qy through Q,) drive the seven segments and the decimal point of the display, ant 7-43HEATHKIT UNIT SEVI EN Ee, me TTT 000 _[bsssabls SAI A A ay MATES _asthis TTT oie pooh TTT ont soidtidd ss TTT ce Figure 7-31 sasaaaan L Loading the addressable latch. a feel al‘CONTIAUING letertacing — Patt | 7-45 While this arrangement results in an inexpensive circuit, it places an extra burden on the MPU. As in the previous example, the microproces- sor must make the binary to 7-segment conversion. But in this case, it must also convert the parallel 7-segment code into a serial bit stream that is acceptable to the addressable latch. You are already familiar with the solution to the first problem. Now, the discussion will show how the MPU can convert parallel data to serial data. The procedure is illustrated in Figure 7-31. The register on the left represents one of the accumulators. It contains the proper 7-segment code for displaying the letter A. This code must be transferred a bit at a time into the addressable latch shown on the right. Remember that the ad- _ dressable latch actually contains eight latches and that the particular latch selected is determined by the 3-bit address at A, through A;. _ __Thefirst step is to store the contents of the accumulator at the basic latch address which is C160, If you convert this address to binary, you will find that address bits A,, A,, A; are all 0's. Since these lines connect to — pins As, A,,and A; on the addressable latch, latch 0 is selected as shown. Notice that the only data line used is D,. Thus, the 0 in bit 0 of the accumulator is stored in latch 0 Next, the contents of the accumulator are shifted to the right so that the next bit is available at Dy. The address of the latch is incremented by 1 and - a store instruction is executed. Thus, the second bit is stored in latch 1.z me 7-46 | unr seven ‘cours This procedure continues as shown until all eight bits have been shifted from the accumulator to the addressable latch. Of course, a short program segment is required to control this operation. A typical program is shown in Figure 7-32. Step through the program and verify that it works. Re- member that the 7-segment code must be in accumulator A before run- ning the program. ‘The ET-3400 Microprocessor Trainer uses a method similar to this for driving the displays. The program shown in Figure 7-32 will light the left-most display. However, in the ET-3400 Microprocessor Trainer, the Dp data lineis inverted. Therefore, a 1 must\be used in the accumulator for each segment that you wish to light. For example, the letter A is formed by placing 01110111, in accumulator A before you run the program. Hex WX] WNEMONICS! aooress | contents | "CONTENTS couments ovo ce ore |Loss none nme on & cr” — |sneuaraesoe wer oe ® o | os S 2704. | sires A he eh re Pa | os & Boma | corny nord not sow © Cte | Concwe mn tu ase Ee S er orn & he | tara don te, a sora * mr late Figure 7-32 ‘A simuple program for loading the ad dressable latch,HEATHKIT CONTINUING ‘ucanon =e Multiplexing Displays ‘The previous approaches required one or more latches for each display. There is a method by which we can drive up to eight displays using only two 8-bit latches. However, it requires some additional componentsand a lot of microprocessor time. Atypical circuit is shown in Figure 7-33. Eight common cathode displays are used in this example. The display cannot light unless its associated transistor is turned on. The transistors are controlled by the contents of. the digit select latch. In turn, this latch is loaded by the MPU. Q, is turned onby placing 1 in bit 7 of the digit latch: Q, is turned on by placing 1 in bit 6; etc. Generally, only one transistor at a time is turned on. A common procedure is to store 10000900 in the digit select latch and rotate the contents so that the 1 appears at each bit in turn. Figure 7-33 Multiplexing Displays. Interfacing — Patt | 7-477-48 | unr seven = The individual segments of each display are turned on by the segment latch. For example, toturn on the decimal point in theright-most display, the segment latch must contain a 1 at bit 7. At the same time, the digit select latch must turn on Q,. - To display an 8-digit message, the procedure looks like this: Load the digit select latch with 10000000;. Load the segment latch with the — 7-segment information for the right-most display. This causes the right- most display to show the first digit. After a brief delay, the contents of the digit display latch are changed to 01000000. This turns on the second = — display. Next the contents of the segment latch must be changed to the 7-segment code for the second display. This procedure continues until all eight displays are lit. Because no two displays are it simultaneously, the — displays must be refreshed many times each second to give the illusion of a constant steady display. The advantage of this technique is that a minimum amount of hardware is required. However, it requires more MPU time than the previous techniques since the displays must be constantly refreshed.erfacing — Patt | 7-49 Self-Test Review 29. How do we turn on a common-anode type 7-segment display? 30. What isa disadvantage of using a decoder-driver, such as the 7447, to drive a display? 31. Why isa latch required between the MPU and the display? 32. When the latch drives the display directly, what performs the decoding function? 33. List four instructions that could beused to output data toa display. 34, Using the arrangement shown in Figure 7-26, what 8-bit code is required to form the letter P? 35. Refer to the program shown in Figure 7-27. If the number in ac- cumulator A is 08,. when this program segment isrun, what binary number will be outputted to the display? 36. What is the purpose of the program shown in Figure 7-27? 37. Refer to Figure 7-30. What determines which of the latches the input data bit goes into? 38. The program shown in Figure 7-32 converts ______. data to ——_—- data, 39. Refer to Figure 7-33. What determines which character is dis- played? 40. Refer to Figure 7-33. What determines the display on which the character appears?7-50 UNIT SEVEN Answers 29, 30. 31. 32. 33. 34, 35. 36. 37. 38. 39. 40. A common-anode type display is turned on by applying logic 0 to the proper cathode. The pattern is limited to those provided by the decoder. Because the output data is stable for only an instant, a latch must be used to capture the data and hold it for the display. The microprocessor. Any of the store instructions could be used to output data to a display. These include: STAA, STAB, STX, and STS. 0110 0111, 0111 1111,, This is the 7-segment pattern for the numeral 8. ‘The program converts binary numbers between 0000 and 1111 toa 7-segment code to form the appropriate hexadecimal numeral. The 3-bit address at Ay through A;. parallel, serial ‘The number in the segment latch. The number in the digit select latch. INTERFACING EXPERIMENTS ‘The hardware experiments are included in Unit 10 of this course. Go to Unit 10 and perform experiments 1 through 4. Some of these experiments are quite involved and you should not attempt more than one experiment per sitting.ee interfacing — Pan's | 7-51 UNIT EXAMINATION 1. A B.state logic gate: A. Has an enable/disable input as well as the normal data inputs. B. Is effectively disconnected from the circuit when it is dis- abled. CC. Isgenerally used when two or more gates drive the same bus line. D. All the above. Which of the following lines or buses is bi-directional? A. The read/write line. B. The address bus. C. The data bus, D. Alll the above, Which of the following lines or buses is an input to the 6800 MPU? ‘The address bus. The 92 clock. Valid Memory Address (VMA). Bus available (BA). pope ‘The MPU can be stopped by external hardware by: Forcing the halt line low. Forcing the halt line high. Forcing the BA line low. Forcing the BA line high. gom> RAM places data on the data bus when: The positive-going edge of the $2 clock occurs. The negative-going edge of the g2 clock occurs. The positive-going edge of the $1 clock occurs. ‘The negative-going edge of the #1 clock occurs. cap> In 6800-based systems, two control lines are generally connected to the address decoder along with the address line. These are: A. BA and gi. B. VMA and 62. C. TSC and 92. D. NMI and 91.7-52 UNIT SEVEN 10. 11. 12. What is the minimum number of 256 by 4 RAM IC’s required to develop a memory of 8-bit words? A. One. B. Two. Cc. Four. D. Eight. ‘The output of the address decoder normally connects to: A. The R/W line on the RAM IC's. B. The CE line on the RAM IC's. C. The HALT line of the MPU. D. The NMI line of the MPU What type of circuit is required between the MPU data lines and the 7-segment display? A. Alatch. B. A decoder/driver. C. An address decoder. D. Alll of the above. Refer to the program shown in Figure 7-27. The number in ac- cumulator A when the program starts is used as: ‘A. The address of the corresponding 7-segment code. B. The 7-segment code. C. The offset address for the LDA, X instruction. D. The address of the 7-segment display. The program shown in Figure 7-32: ‘A. Converts the 7-segment code in accumulator A into a serial bit stream acceptable to the latch. B. Converts the 7-segment code in accumulator A into a parallel data byte acceptable to the addressable latch. C. Converts the binary number in accumulator A into the cor- responding 7-segment code. D. Loads eight addressable latches with the proper 7-segment codes to display an 8-character message. ‘An advantage of the circuit shown in Figure 7-33 is: ‘A. Itrequires fewer MPU instructiois than the other methods of driving the display. B. It requires less MPU time than the other methods of driving the displays. C. It requires less external circuitry than the other methods. D. All of the above.