Lecture 4 (part 2): Data Transfer
Instructions
CSE 30: Computer Organization and Systems Programming
Diba Mirza
Dept. of Computer Science and Engineering
University of California, San Diego
Assembly Operands: Memory
v Memory: Think of as single one-dimensional array where each cell
v Stores a byte size value
v Is referred to by a 32 bit address e.g. value at 0x4000 is 0x0a
0x0a 0x0b 0x0c 0x0d
0x4000 0x4001 0x4002 0x4003
v Data is stored in memory as: variables, arrays, structures
v But ARM arithmetic instructions only operate on registers,
never directly on memory.
v Data transfer instructions transfer data between registers and
memory:
v Memory to register or LOAD from memory to register
v Register to memory or STORE from register to memory
Load/Store Instructions
v The ARM is a Load/Store Architecture:
v Does not support memory to memory data processing
operations.
v Must move data values into registers before using them.
v This might sound inefficient, but in practice isn’t:
v Load data values from memory into registers.
v Process data in registers using a number of data processing
instructions which are not slowed down by memory access.
v Store results from registers out to memory.
Load/Store Instructions
v The
ARM has three sets of instructions which interact
with main memory. These are:
v Single register data transfer (LDR/STR)
v Block data transfer (LDM/STM)
v Single Data Swap (SWP)
v The basic load and store instructions are:
v Load and Store Word or Byte or Halfword
v LDR / STR / LDRB / STRB / LDRH / STRH
Single register data transfer
LDR STR Word
LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load
v Memory system must support all access sizes
v Syntax:
v LDR{<cond>}{<size>} Rd, <address>
v STR{<cond>}{<size>} Rd, <address>
e.g. LDREQB
Data Transfer: Memory to Register
v To
transfer a word of data, we need to
specify two things:
v Register:
r0-r15
v Memory address: more difficult
v How do we specify the memory address of data to
operate on?
v We will look at different ways of how this is done in
ARM
Remember: Load value/data FROM memory
Addressing Modes
v Thereare many ways in ARM to specify the
address; these are called addressing modes.
v Two basic classification
1. Base register Addressing
§ Register holds the 32 bit memory address
§ Also called the base address
2. Base Displacement Addressing mode
§ An effective address is calculated :
Effective address = < Base address +offset>
§ Base address in a register as before
§ Offset can be specified in different ways
Base Register Addressing Modes
v Specify
a register which contains the
memory address
v In case of the load instruction (LDR) this is the memory
address of the data that we want to retrieve from memory
v In case of the store instruction (STR), this is the memory
address where we want to write the value which is
currently in a register
v Example: [r0]
v specifiesthe memory address pointed to by the
value in r0
Data Transfer: Memory to Register
v Load Instruction Syntax:
1 2, [3]
v where
1) operation name
2) register that will receive value
3) register containing pointer to memory
v ARM Instruction Name:
v LDR(meaning Load Register, so 32 bits or one
word are loaded at a time)
Data Transfer: Memory to Register
v LDR r2,[r1]
This instruction will take the address in r1, and then load a 4
byte value from the memory pointed to by it into register r2
v Note: r1 is called the base register
Memory
r1 r2
0x200 0x200 0xaa 0xddccbbaa
0x201 0xbb
Base Register Destination Register
0x202 0xcc
0x203 0xdd for LDR
Data Transfer: Register to Memory
v STR r2,[r1]
This instruction will take the address in r1, and then store a 4
byte value from the register r2 to the memory pointed to by r1.
v Note: r1 is called the base register
Memory
r1 r2
0x200 0x200 0xaa 0xddccbbaa
0x201 0xbb
Base Register Source Register
0x202 0xcc
0x203 0xdd for STR
Base Displacement Addressing Mode
v To
specify a memory address to copy from,
specify two things:
v A register which contains a pointer to memory
v A numerical offset (in bytes)
v Theeffective memory address is the sum of
these two values.
v Example: [r0,#8]
v specifies
the memory address pointed to by the
value in r0, plus 8 bytes
Base Displacement Addressing Mode
1. Pre-indexed addressing syntax:
I. Base register is not updated
LDR/STR <dest_reg>[<base_reg>,offset]
Examples:
LDR/STR r1 [r2, #4]; offset: immediate 4
;The effective memory address is calculated as r2+4
LDR/STR r1 [r2, r3]; offset: value in register r3
;The effective memory address is calculated as r2+r3
LDR/STR r1 [r2, r3, LSL #3]; offset: register value *23
;The effective memory address is calculated as r2+r3*23
Base Displacement Addressing Mode
1. Pre-indexed addressing:
I. Base register is not updated:
LDR/STR <dest_reg>[<base_reg>,offset]
II. Base register is first updated, the updated address is used
LDR/STR <dest_reg>[<base_reg>,offset]!
Examples:
LDR/STR r1 [r2, #4]!; offset: immediate 4
;r2=r2+4
LDR/STR r1 [r2, r3]!; offset: value in register r3
;r2=r2+r3
LDR r1 [r2, r3, LSL #3]!; offset: register value *23
;r2=r2+r3*23
Base Displacement, Pre-Indexed
v Example: LDR r0,[r1,#12]
This instruction will take the pointer in r1, add 12 bytes to
it, and then load the value from the memory pointed to by
this calculated sum into register r0
v Example: STR r0,[r1,#-8]
This instruction will take the pointer in r0, subtract 8 bytes
from it, and then store the value from register r0 into the
memory address pointed to by the calculated sum
v Notes:
v r1 is called the base register
v #constant is called the offset
v offset is generally used in accessing elements of array or
structure: base reg points to beginning of array or structure
Pre indexed addressing
What is the value in r1 after the following instruction is executed?
A. 0x200
STR r2,[r1, #-4]! B. 0x1fc
C. 0x196
D. None of the above
Memory
r1 r2
0x200 0x20_ 0xaa 0xddccbbaa
0x20_ 0xbb
Base Register Destination Register
0x20_ 0xcc
0x20_ 0xdd for LDR
Base Displacement Addressing Mode
1. Post-indexed addressing:Base register is updated after load/
store
LDR/STR <dest_reg>[<base_reg>] ,offset
Examples:
LDR/STR r1 [r2], #4; offset: immediate 4
;Load/Store to/from memory address in r2, update r2=r2+4
LDR/STR r1 [r2], r3; offset: value in register r3
;Load/Store to/from memory address in r2, update r2=r2+r3
LDR r1 [r2] r3, LSL #3; offset: register value left shifted
;Load/Store to/from memory address in r2, update r2=r2+r3*23
Post-indexed Addressing Mode
Memory
* Example: STR r0, [r1], #12
r1 Offset r0
Updated Source
Base 0x20c 12 0x20c 0x5 Register
Register for STR
0x200 0x5
r1
Original
Base 0x200
Register
* If r2 contains 3, auto-increment base register to 0x20c by multiplying
this by 4:
• STR r0, [r1], r2, LSL #2
* To auto-increment the base register to location 0x1f4 instead use:
• STR r0, [r1], #-12
Using Addressing Modes Efficiently
* Imagine an array, the first element of which is pointed to by the contents
of r0.
Memory
* If we want to access a particular element, element Offset
then we can use pre-indexed addressing:
• r1 is element we want.
• LDR r2, [r0, r1, LSL #2] 3 12
Pointer to start 2 8
of array
* If we want to step through every 1 4
element of the array, for instance r0 0 0
to produce sum of elements in the
array, then we can use post-indexed addressing within a loop:
• r1 is address of current element (initially equal to r0).
• LDR r2, [r1], #4
Use a further register to store the address of final element,
so that the loop can be correctly terminated.
Pointers vs. Values
v Key Concept: A register can hold any 32-bit
value. That value can be a (signed) int, an
unsigned int, a pointer (memory
address), and so on
v If you write ADD r2,r1,r0
then r0 and r1 better contain values
v If you write LDR r2,[r0]
then [r0] better contain a pointer
v Don’t mix these up!
Compilation with Memory
v What offset in LDR to select A[8] in C?
v 4x8=32 to select A[8]: byte vs word
v Compile by hand using registers:
g = h + A[8];!
v g: r1, h: r2, r3:base address of A
v 1st
transfer from memory to register:
!LDR r0,[r3, #32] ; r0 gets A[8]
v Add 32 to r3 to select A[8], put into r0!
v Next
add it to h and place in g
ADD r1,r2,r0 ; r1 = h+A[8]
Notes about Memory
v Pitfall:
Forgetting that sequential word
addresses in machines with byte addressing
do not differ by 1.
v Many assembly language programmers have
toiled over errors made by assuming that the
address of the next word can be found by
incrementing the address in a register by 1
instead of by the word size in bytes.
v So remember that for both LDR and STR, the
sum of the base address and the offset must be a
multiple of 4 (to be word aligned)
More Notes about Memory: Alignment
v ARM typically requires that all words start at
byte addresses that are multiples of 4 bytes
0 1 2 3! Last hex digit
of address is:!
Aligned!
0, 4, 8, or Chex!
Not! 1, 5, 9, or Dhex!
Aligned! 2, 6, A, or Ehex!
3, 7, B, or Fhex!
v Called Alignment: objects must fall on address
that is multiple of their size.
Role of Registers vs. Memory
v What if more variables than registers?
v Compiler tries to keep most frequently used
variables in registers
v Why not keep all variables in memory?
v Smaller is faster:
registers are faster than memory
v Registers more versatile:
v ARM arithmetic instructions can read 2, operate on
them, and write 1 per instruction
v ARM data transfer only read or write 1 operand per
instruction, and no operation
Conclusion
v Memory is byte-addressable, but LDR and STR
access one word at a time.
v A pointer (used by LDR and STR) is just a
memory address, so we can add to it or subtract
from it (using offset).
Conclusion
v Instructions so far:
v Previously:
ADD, SUB, MUL, MULA, [U|S]MULL, [U|S]MLAL, RSB
AND, ORR, EOR, BIC
MOV, MVN
LSL, LSR, ASR, ROR
New:
LDR, LDR, STR, LDRB, STRB, LDRH, STRH
