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VHDL Decoder Design Methods

This document describes three different modeling approaches - dataflow, behavioral, and structural - for implementing a 2-input to 4-output decoder circuit in VHDL. The dataflow model describes the circuit using signal assignments. The behavioral model uses a process with an if-else statement to assign outputs conditionally based on inputs. The structural model breaks the circuit into components - inverters and 3-input AND gates - and connects them using a port map.

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72 views4 pages

VHDL Decoder Design Methods

This document describes three different modeling approaches - dataflow, behavioral, and structural - for implementing a 2-input to 4-output decoder circuit in VHDL. The dataflow model describes the circuit using signal assignments. The behavioral model uses a process with an if-else statement to assign outputs conditionally based on inputs. The structural model breaks the circuit into components - inverters and 3-input AND gates - and connects them using a port map.

Uploaded by

atul
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Dataflow modelling

library IEEE;
useIEEE.std-logic-ll64.all;
entity decoderZto4 is
end decoder2to4;
architecture DATAFLOW-DEC of decoder2to4 is
begin
port (xl, x0, E: in BIT; out BIT-VECTOR (0 to 3 ) ) ;
signal xll, x00: BIT;
xll <= not xl;
x00 <= not x0;
d(O)<=E and xll and x00;
d(l)<=E and xll and x0;
d(2)<=E and xl and x00;
d(3)<=E and xl and x0;
end DATAFLOW-DEC;
Behavioural Modelling
library IEEE;
useIEEE.std-logic-ll64.all;
entity decoder2to4 is
port (xl, x0, E: in BIT; d: out BIT-VECTOR ( 0 to 3));
end decoder2to4;
architecture BEHAVIOR-DEC of decoder2to4 is
begin
process (xl, x0, E)
variable xll, x0O:BIT;
xll:= not xl;
xOO:= not x0;
begin
if E = '1' then
d(O)<= xll and x00;
d(l)<= xll and x0;
d(2)<= xl and x00;
d(3)<= xl and x0;
d< = " 0 0 0 0 " ;
else
end if;
end process;
end BEHAVIOR-DEC;
Structural Modelling
library IEEE;
useIEEE.std-logic-ll64.all;
entity decoder2to4 is
port (xl,xO,E: in B1T;d: out BIT-VECTOR(0
end decoder2to4;
architecture STRUCTURAL-DEC of decoder2to4 is
port ( u : in BIT; v: out BIT);
component inv
end component;
--VHDL code for inv
library IEEE;
useIEEE.std-logic-ll64.all;
entity inv is
end inv;
architecture LOGIC1 of inv is
begin
end LOGIC1;
port (u: in BIT; v: out BIT);
v<=not u;
component and3
end component;
port (a, b, c: in BIT; f: out BIT);
--VHDL code for and3
library IEEE;
useIEEE.std-logic-ll64.all;
entity and3 is
end and3;
architecture LOGIC of and3 is
begin
end LOGIC;
begin
port (a, b, c: in BIT; f: out BIT);
f<= a and b and c;
signal xll, x00: BIT;
fO: inv port map (xl, xll);
to 3 ) ) ;
fl: inv port map (x0, x00);
f2: and3 port map (E, xll, x00, d(0));
f3: and3 port map (E, xll, x0, d ( 1 ) ) ;
f4: and3 port map (E, xl, x00, d ( 2 ) ) ;
f5: and3 port map (E, xl, x0, d(3));
end STRUCTURAL-DEC;

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