16VLB05 DIGITAL CMOS VLSI DESIGN LT P C

3 0 2 4
COURSE OBJECTIVES:

 To deal comprehensively with all aspects of transistor level design of all the digital building blocks
 To focus on the transistor level design
 To address all important issues related to size, speed and power consumption.
 To deal with the memory architectures
 To know the interconnect and clocking strategies.
 To understand the design of combinational and sequential CMOS circuits

COURSE OUTCOMES:

 Able to carry out transistor level hand calculation

 Able to design most important building blocks used in digital CMOS VLSI circuits.
 Able to develop strong understanding of the design methodology
 Able to develop tradeoffs of the various circuit choices for each of all the blocks discussed.
 Able to know the interconnect and clocking strategies.
 Able to design combinational and sequential CMOS circuits

UNIT I: MOS TRANSISTOR PRINCIPLES AND CMOS INVERTER 9

MOS(FET) Transistor Characteristic under Static and Dynamic Conditions, (Add)MOS device Design equation, MOS Transistor
Secondary Effects, Process Variations, Technology Scaling, CMOS Inverter - Static Characteristic, Dynamic Characteristic, Power,
Energy, and Energy Delay parameters,(Add) Tristate inverters.

UNIT II: COMBINATIONAL LOGIC CIRCUITS 9

Propagation Delays, Stick diagram, Layout diagrams, Examples of combinational logic design, Elmore’s constant, Dynamic Logic
Gates, Pass Transistor Logic, Power Dissipation, Low Power Design principles.

UNIT III: SEQUENTIAL LOGIC CIRCUITS 9

Static Latches and Registers, Dynamic Latches and Registers, Timing Issues, Pipelines, Pulse and sense amplifier based Registers,
Nonbistable Sequential Circuits.

UNIT IV: ARITHMETIC BUILDING BLOCKS AND MEMORY ARCHITECTURES 9

Data path circuits, Architectures for Adders, Accumulators, Multipliers, Barrel Shifters, Speed and Area Tradeoffs, Memory
Architectures, and Memory control circuits.

UNIT V:INTERCONNECT AND CLOCKING STRATEGIES 9

Interconnect Parameters – Capacitance, Resistance, and Inductance, Electrical Wire Models, Timing classification of Digital Systems,
Synchronous Design, Self-Timed Circuit Design.

TOTAL: 45 Hours

REFERENCE BOOKS:

Sl.No Author(s) Title of the Book Publisher Year of Publication

Jan Rabaey, Anantha

Digital Integrated Circuits: A
1. Chandrakasan, B Prentice Hall of India. 2003
Design Perspective
Nikolic
N.Weste, K. Principles of CMOS VLSI
2 Addision Wesley 1993
Eshraghian, Design
Application Specific Integrated
3. M J Smith Addisson Wesley 1997
Circuits
 David A. Hodges,
Analysis and Design of Digital
4. HoraceG. Jackson, and McGraw-Hill 2004
Integrated Circuits
Resve A. Saleh

5. Ken Martin Digital Integrated Circuit Design Oxford University Press 2000

WEB URLs :
1. nptel.ac.in/courses/117101105
2. nptel.ac.in/courses/117106093
3. nptel.ac.in/downloads/117101105/
4. www.nptelvideos.in/2012/12/vlsi-design.html
5. www.nptelvideos.in/2012/12/digital-vlsi-system-design.html

Mapping of COs and POs

POs
CO s
1 2 3 4 5 6 7 8 9 10 11
CO1 2 3 3 - - - - 3 - - -
CO2 3 3 3 2 3 3 2 - - -
CO3 3 3 2 - - - - - - -
CO4 2 3 3 3 - - 3 - - - -
CO5 3 3 2 - 3 - 3 - - - -
CO6 1 2 2 - - - 3 - - -
16VLB06 CAD FOR VLSI CIRCUITS L T P C
3 2 0 4
COURSE OBJECTIVES:

 To introduce the basic CAD algorithm

 To understand the Partitioning
 To study about Placement, Floor Planning
 To learn about Global, Detail routing
 To know the Modeling and synthesis in CAD flow.
 To understand the High level transformations

COURSE OUTCOMES:

 Learn the Fundamentals of basic algorithm in CAD.

 Study the different partitioning algorithm.
 Understand the floor planning and placement algorithm.
 Learn about different routing algorithms.
 Know about modeling and synthesis techniques of CAD.
 Able to analyze the local routing problems

UNIT I: VLSI DESIGN METHODOLOGIES 9

Introduction to VLSI Design methodologies - Review of Data structures and algorithms - Review of VLSI Design automation tools -
Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems – general purpose methods for
combinatorial optimization.

UNIT II:DESIGN RULES 9

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction - placement and partitioning -
Circuit representation – Placement algorithms – partitioning.

UNIT III:FLOOR PLANNING 9

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems - Area routing - channel routing -
global routing - algorithms for global routing.

UNIT IV:SIMULATION 9
Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation - Combinational Logic Synthesis - Binary
Decision Diagrams – Two Level Logic Synthesis.

UNIT V:MODELLING AND SYNTHESIS 9

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and scheduling - Simple scheduling
algorithm – Assignment problem - High level transformations.

TOTAL: 45 Hours

REFERENCE BOOKS:

Year of
Sl.No Author(s) Title of the Book Publisher
Publication
Algorithms for VLSI
1. S.H. Gerez John Wiley & Sons 2002
Design Automation
Algorithms for VLSI
Kluwer Academic
2. N.A. Sherwani Physical Design 2002
Publishers
Automation
3. Giovanni De Synthesis and Tata McGraw Hill 1994
 Optimization of Digital
Micheli
Circuits
M. Sarrafzadeh An Introduction to VLSI
4. McGraw Hill 1996
and C.K. Wong Physical Design
Sun Microsystems
5. Samir Palnitkar Verilog HDL Press A Prentice Hall 2001
Title

WEB URLs:
1. http:// nptel.ac.in/courses/106103016
2. http:// www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch01.pdf
3. http:// nptel.ac.in/courses/Webcourse-contents/IIT.../VLSI%20Design/TOC-l13.html
4. http:// textofvideo.nptel.iitm.ac.in/106105083/lec17.pdf
5. http:// textofvideo.nptel.iitm.ac.in/112102101/lec1.pdf

Mapping of COs and POs

POs
CO s
1 2 3 4 5 6 7 8 9 10 11
CO1 2 3 3 - - 3 - 3 1 1 1
CO2 3 3 3 2 3 3 3 2 1 - 1
CO3 3 3 2 - - 3 - 1 1 -
CO4 2 3 3 3 - 3 3 - 1 - 1
CO5 3 3 2 - 3 3 3 - 1 1 -
CO6 1 2 2 - - 3 3 - - -
16VLB07 LOW POWER VLSI DESIGN L T P C
3 0 0 3
COURSE OBJECTIVES:

 To understand different sources of power dissipation in CMOS & MIS structure.

 To understand the different types of low power adders and multipliers
 To focus on synthesis of different level low power transforms.
 To gain knowledge on low power static RAM architecture & the source of power dissipation in SRAM
 To understand the various energy recovery techniques used in low power design
 To understand the Special techniques of low power VLSI design

COURSE OUTCOMES:

 An ability to analyze different source of power dissipation and the factors involved in.
 Able to understand the different techniques involved in low power adders and multipliers
 Understandings of the impact of various low power transform
 An ability to identify and analyze the different techniques involved in low power SRAM.
 Able to understand various energy recovery techniques.
 Able to analyze the adders and multipliers

UNIT I: POWER DISSIPATION 9

Hierarchy of limits of power – Sources of power consumption – Physics of power dissipation in CMOS FET devices – Basic principle
of low power design. (Add) Power dissipation in Domino CMOS- Low power VLSI design limits.

UNIT II:POWER OPTIMIZATION 9

Logic level power optimization – Circuit level low power design – circuit techniques for reducing power consumption in adders and
multipliers.

UNIT III:DESIGN OF LOW POWER CIRCUITS 9

Computer arithmetic techniques for low power system – reducing power consumption in memories – low power clock, Inter connect
and layout design – Advanced techniques –Special techniques.

UNIT IV:POWER ESTIMATION 9

Power Estimation technique – logic power estimation – Simulation power analysis –Probabilistic power analysis, (Add) Modeling of
signals- Signal probability calculation.

UNIT V: SYNTHESIS AND SOFTWARE DESIGN 9

Synthesis for low power – Behavioral level transform – software design for low power overlap and digital correction.

TOTAL: 45 Hours

REFERENCE BOOKS:

Year of
Sl.No Author(s) Title of the Book Publisher
Publication

Kaushik Roy and Low power CMOS

1. Wiley 2000
S.C.Prasad VLSI circuit design
Dimitrios Soudris,
Designing CMOS
2. Christians Pignet, Kluwer 2002
Circuits for Low Power
Costas Goutis

3. J.B.Kulo and J.H Lou J.B.Kulo and J.H Lou Wiley 1999
 A.P.Chandrasekaran Low power digital
4. Kluwer 1995
and R.W.Broadersen CMOS design
Practical low power
5. Gary Yeap Kluwer 1998
digital VLSI design

WEB URLs:
1. nptel.ac.in/courses/111108066/
2. nptel.ac.in/courses/106105034/36
3. nptel.ac.in/syllabus/106105034/
4. www.nptelvideos.in/2012/11/low-power-vlsi-circuits-systems.html
5. textofvideo.nptel.iitm.ac.in/106105034/lec1.pdf

Mapping of COs and POs

POs
CO s
1 2 3 4 5 6 7 8 9 10 11
CO1 2 3 3 - - 2 - 3 1 - 1
CO2 3 3 3 2 3 1 3 2 - - -
CO3 3 3 2 - - 2 - 1 1 -
CO4 2 3 3 3 - - 3 - - - 1
CO5 3 3 2 - 3 1 3 - - 1 -
CO6 1 2 2 - - 2 3 2 - -
 16VLC02 ADVANCED DIGITAL SYSTEM DESIGN L T P C
3 0 0 3
COURSE OBJECTIVES:

 To understand the concepts of advanced Boolean algebra

 To understand the concepts of threshold logic
 To understand the concepts of symmetric functions
 To understand the concepts of sequential logic circuits.
 To study the concepts of Fault Diagnosis and Testability Algorithms.
 To understand the concept of test generation.

COURSE OUTCOMES:

 To apply knowledge of Boolean algebra to the analysis and design of digital logic circuits.
 To acquire the knowledge of threshold logic
 To acquire the knowledge of symmetric functions.
 To view advanced digital design from a hierarchical viewpoint.
 To acquire the knowledge of testability concepts.
 To analyze the Built-in Self Test.

UNIT I: ADVANCED TOPICS IN BOOLEAN ALGEBRA 9

Shannon's expansion theorem, Consensus theorem, Octal designation, Run measure, INHIBIT / INCLUSION / AOI / Driver / Buffer
gates, Gate expander, Reed Muller expansion, Synthesis of multiple output combinational logic circuits by product map method,
Design of static hazard free and dynamic hazard free logic circuits.

UNIT II: THRESHOLD LOGIC 9

Linear seperability, Unateness, Physical implementation, Dual comparability, Reduced functions, Various theorems in threshold logic,
Synthesis of single gate and multigate threshold Network.

UNIT III: SYMMETRIC FUNCTIONS 9

Elementary symmetric functions, Partially symmetric and total ly symmetric functions, McCluskey decomposition method, Unity ratio
symmetric ratio functions, Synthesis of symmetric function by contact networks.

UNIT IV: SEQUENTIAL LOGIC CIRCUITS 9

Mealy machine, Moore machine, Trivial / Reversible / Isomorphic sequential machines, State diagrams, State table minimization,
Incompletely specified sequential machines, State assignments, Design of synchronous and asynchronous sequential logic circuits
working in the fundamental mode and pulse mode, Essential hazards Unger's theorem.

UNIT V: FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS 9

Fault Table Method –Path Sensitization Method –Boolean Difference Method –Kohavi Algorithm –Tolerance Techniques –The
Compact Algorithm –Fault in PLA –Test Generation –Masking Cycle –Built-in Self Test.

TOTAL: 45 Hours

REFERENCE BOOKS:

Year of
Sl.No Author(s) Title of the Book Publisher
Publication
1. Charles
Fundamentals of Logic Design Thomson Learning 2004
H.Roth Jr
 2 Nripendra N
Logic Design Theory Prentice Hall of India 2001
Biswas
3 Parag Digital system Design using
B S Publications 2003
K.Lala PLD
Advanced Digital Systems
4 Lucien Design with Rapid
Springer 2012
Ngalamou Prototyping on FPGAs Using
VHDL
5 Kuruvilla Digital System Design with
Prentice Hall 2007
Varghese PLDs and FPGAs

WEB URLs

1. nptel.ac.in/courses/117108040/downloads/Digital%20System%20Design.pdf
2. nptel.ac.in/video.php?subjectId=117105080
3. nptelvideos.in/2012/12/digital-systems-design.html
4. extofvideo.nptel.iitm.ac.in/117106092/lec1.pdf
5. youtube.com/watch?v=CL3ups78jrs

Mapping of COs and POs

POs
CO s
1 2 3 4 5 6 7 8 9 10 11
CO1 2 - 1 - - - - - 1 - 1
CO2 2 1 - 2 1 1 - 1 - 1
CO3 2 - 2 2 1 1 - 1 1 1 1
CO4 - 1 2 - 1 1 1 1 1 - 1
CO5 3 1 2 2 2 - - - - 2 -
CO6 3 - 1 2 1 - - 1 - - -
16VLC04 VLSI TECHNOLOGY L P T C
3 0 0 3

COURSE OBJECTIVES:

 To understand the Fabrication of ICs and purification of Silicon in different technologies.

 To impart in-depth knowledge about Etching and deposition of different layers.
 To understand the different packaging techniques of VLSI devices.
 To understand the fabrication technologies.
 To understand the integration techniques.
 To understand the MOS Memory IC technology
COURSE OUTCOMES:

 The ability to use metallization techniques to create three-dimensional device structures devices.
 The ability to know methodology to fabricate an IC’s.
 The ability to observe the implementation techniques in chip designing.
 The ability to learn the application areas of VLSI technologies
 Able to understand the integration techniques.
 Able to analyze the MOS Memory IC technology

UNIT I: CRYSTAL GROWTH, WAFER PREPARATION, EPITAXY ANDOXIDATION 9

Electronic Grade Silicon, Czochralski crystal growing, Silicon Shaping, processing consideration,Vapor phase Epitaxy, Molecular
Beam Epitaxy, Epitaxial Evaluation, Growth Mechanism andkinetics, Thin Oxides, Oxidation Techniques and Systems, Oxide
properties, Redistribution ofDopants at interface, Oxidation of Poly Silicon, Oxidation induced Defects.

UNIT II:LITHOGRAPHY AND REACTIVE PLASMA ETCHING 9

Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography, Nano imprint Lithography, Plasma properties,
Feature Size control and Anisotropic Etch mechanism, reactive Plasma Etching techniques and Equipments.

UNIT III:DEPOSITION, DIFFUSION AND ION IMPLANTATION 9

Deposition process, Polysilicon, plasma assisted Deposition, Models of Diffusion in Solids, Fick’sone dimensional Diffusion Equation
- Measurement techniques - Range theory- Implant equipment –Annealing- Shallow junction, High - energy implantation.

UNIT IV : METALLIZATION AND VLSI PROCESS INTEGRATION 9

Physical Vapour Deposition (PVD) –Patterning- NMOS IC Technology – CMOS IC Technology –BICMOS IC Technology- MOS
Memory IC technology - Bipolar IC Technology –Silicon on Insulator Technology–Noise in VLSI Technologies

UNIT V:ANALYTICAL, ASSEMBLY TECHNIQUES AND PACKAGING OF VLSI DEVICES 9

Analytical Beams – Beams Specimen interactions - Chemical methods – Package types – packaging design consideration – VLSI
assembly technology – Package fabrication technology. Scanning Probe Techniques-Analysis by diffraction and fluorescence methods

TOTAL: 45 Hours

REFERENCE BOOKS:

Sl.No Author(s) Title of the Book Publisher Year of Publication

1. S.M .Sze VLSI Technology McGraw Hill 2003

 2. Introduction to N MOS and CMOS
Amar Mukherjee PHI 2000
VLSI System Design
James D Plummer, Silicon VLSI Technology:
3. Michael D. Deal and Fundamentals Practice and PHI 2000
Peter B. Griffin Modeling

4. Wai Kai Chen VLSI Technology CRC press 2003

Nano Electronics and Information

5. Rainer Waser Wiley-IEEE Press 2004
Technolgy

WEB URLs :
1. www.google.co.in/search?site=&source=hp&q=S.M+.Sze%2C+VLSI+Technology
2. www.scribd.com/doc/124363987/VLSI-DESIGN-pdf
3. nptel.ac.in/courses/IIT-MADRAS/ Silicon VLSI Technology. pdf
4. nptel.ac.in/courses/111104027/
5. nptel.ac.in/courses/111106087/
Mapping of COs and POs

POs
CO s
1 2 3 4 5 6 7 8 9 10 11
CO1 2 - - - - 2 2 2 2 - 2
CO2 - 2 - 2 1 2 2 - 2 2 2
CO3 3 - 3 - 1 2 2 1 2 - 2
CO4 2 - 2 - - 2 2 - 2 - 2
CO5 1 3 2 2 2 - - - 2 2 -
CO6 1 3 - 3 - - 1 - 2 - -
16VLC05 DSP INTEGRATED CIRCUITS L P T C
3 0 0 3
COURSE OBJECTIVES:

 To study the procedural flow of system design in DSP and Integrated circuit.
 To design FIR and IIR filters for the given specifications.
 To study the architectures for DSP system.
 To learn the design layout for VLSI circuits.
 To understand the concept of DSP Processor Architecture and code optimization.
 To learn the applications of DSP Integrated circuits.

COURSE OUTCOMES:

 To design filter and analysis the concept of finite word length effects.
 To synthesis DSP Architecture and design integrated circuits.
 To learn DSP Processor Architecture.
 The ability to learn the optimization techniques.
 To understand the concept of DSP Processor Architecture and code optimization.
 To learn the applications of DSP Integrated circuits.

UNIT I: DSP SYSTEMS AND MOS TECHNOLOGIES 9

Standard digital signal processors –Application specific IC’s for DSP –DSP systems –DSP system design –Integrated circuit design –
MOS transistors- MOS logic - VLSI process technologies – Trends in CMOS technologies.

UNIT II:DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS 9

FIR filters: FIR filter structures, FIR chips - IIR filters structures- Real time filtering – Circular buffering- Adaptive filtering: LMS
and RLS Algorithm –Multi-rate filters: Interpolation with an integer factor L, Sampling rate change with a ratio L/M Finite Word
Length Effects: Parasitic oscillations - Scaling of signal levels - Round-off noise –Measuring round-off noise.

UNIT III:DSP ARCHITECTURES AND ITS SYNTHESIS 9

DSP system architectures - Standard DSP architecture - Ideal DSP architectures - Multiprocessors and multicomputer - Systolic and
Wave front arrays - Shared memory architectures - Mapping of DSP algorithms onto hardware - Implementation based on complex
PEs - Shared memory architecture with Bi-serial PEs.

UNITIV:ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN 9

Conventional number system - Redundant Number system - Residue Number System - Bit-parallel and Bit-Serial arithmetic - Basic
shift accumulator - Reducing the memory size - Complex multipliers - Improved shift-accumulator - Layout of VLSI circuits - FFT
processor - DCT processor and Interpolator as case studies - Cordic algorithm.

UNIT V: TMS320C6X, DSP56XXX PROCESSORS ARCHITECTURE AND CODE OPTIMIZATION 9

CPU Operation – Pipelined CPU- Velocity TI – C64XDSP- Software tools: EVM – DSK Target C6x board – Assembly file –
Memory management- Compiler utility- Code initialization – Code composer studio – Interrupt data processing, Code Optimization:
Word- wide optimization – Mixing C and assembly- Software pipelining – C64X improvements - Overview on Free scale
DSP56XXX Core Architecture. Design of modulo multipliers using RNS-complex multipliers-accumulator.
TOTAL: 45 Hours
REFERENCE BOOKS:

Year of
Sl.No Author(s) Title of the Book Publisher
Publication

1. Lars DSP Integrated Circuits Academic press, New 1999

 Wanhammer York

Nasser
2 Wiley Prentice Hall 2001
Kehtarnavaz DSP System Design Using the
TMS320C6000
Richard G. Understanding Digital Signal
Prentice Hall 2010
Lyons Processing 2004.

John G. Digital Signal Processing:

Proakis, Principles, Algorithms, and Kluwer Acedamic
Applications. 2006.
Dimitris K. Publishers
Manolakis

Mohammed Digital Signal Processing

El- Applications with Motorola's Prentice Hall 2006
Sharkawy DSP56002Processor,

WEB URLs
1. www.annauniv.edu/academic_courses/WSA/.../07.%20VLSI%20Design.pdf
2. www.scribd.com/doc/310875222/1-Digital-Signal-Processing-Introduction
3. www.computer.org/csdl/trans/tc/1985/05/01676588-abs.html
4. www.bitsathy.ac.in/academics/pdf/syllabus/VLSI%20-%202015.pdf
5. nptel.ac.in/courses/IIT-MADRAS/ DSP Integrated Circuits /Pdfs/1_5.pdf

Mapping of COs and POs

POs
CO s
1 2 3 4 5 6 7 8 9 10 11
CO1 2 3 3 - - - - 3 - - -
CO2 3 3 3 2 3 3 2 - - -
CO3 3 3 2 - - - - - - -
CO4 2 3 3 3 - - 3 - - - -
CO5 3 3 2 - 3 - 3 - - - -
CO6 1 2 2 - - - 3 - - -