DS3231

Extremely Accurate I2C-Integrated

RTC/TCXO/Crystal
General Description Features
The DS3231 is a low-cost, extremely accurate I2C real- o Accuracy ±2ppm from 0°C to +40°C
time clock (RTC) with an integrated temperature- o Accuracy ±3.5ppm from -40°C to +85°C
compensated crystal oscillator (TCXO) and crystal. The o Battery Backup Input for Continuous
device incorporates a battery input, and maintains accu- Timekeeping
rate timekeeping when main power to the device is inter- o Operating Temperature Ranges
rupted. The integration of the crystal resonator enhances Commercial: 0°C to +70°C
the long-term accuracy of the device as well as reduces Industrial: -40°C to +85°C
the piece-part count in a manufacturing line. The DS3231 o Low-Power Consumption
is available in commercial and industrial temperature o Real-Time Clock Counts Seconds, Minutes,
ranges, and is offered in a 16-pin, 300-mil SO package. Hours, Day, Date, Month, and Year with Leap Year
Compensation Valid Up to 2100
The RTC maintains seconds, minutes, hours, day, date, o Two Time-of-Day Alarms
month, and year information. The date at the end of the
o Programmable Square-Wave Output
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The o Fast (400kHz) I2C Interface
clock operates in either the 24-hour or 12-hour format o 3.3V Operation
with an AM/PM indicator. Two programmable time-of- o Digital Temp Sensor Output: ±3°C Accuracy
day alarms and a programmable square-wave output o Register for Aging Trim
are provided. Address and data are transferred serially o RST Output/Pushbutton Reset Debounce Input
through an I2C bidirectional bus. o Underwriters Laboratories (UL) Recognized
A precision temperature-compensated voltage refer-
ence and comparator circuit monitors the status of VCC Ordering Information
to detect power failures, to provide a reset output, and
to automatically switch to the backup supply when nec- PART TEMP RANGE PIN-PACKAGE
essary. Additionally, the RST pin is monitored as a DS3231S# 0°C to +70°C 16 SO
pushbutton input for generating a µP reset. DS3231SN# -40°C to +85°C 16 SO

Applications #Denotes an RoHS-compliant device that may include lead

(Pb) that is exempt under RoHS requirements. The lead finish
Servers Utility Power Meters is JESD97 category e3, and is compatible with both lead-
based and lead-free soldering processes. A "#" anywhere on
Telematics GPS the top mark denotes an RoHS-compliant device.

Pin Configuration appears at end of data sheet.

Typical Operating Circuit
VCC VCC
RPU = tR/CB
VCC

RPU RPU
VCC
SCL SCL INT/SQW
SDA SDA 32kHz
µP
RST RST VBAT
DS3231
PUSHBUTTON N.C. N.C.
RESET
N.C. N.C.
N.C. N.C.
N.C. GND N.C.

For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. 19-5170; Rev 9; 1/13
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground......-0.3V to +6.0V Junction Temperature ......................................................+125°C
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)....73°C/W Storage Temperature Range ...............................-40°C to +85°C
Junction-to-Case Thermal Resistance (θJC) (Note 1) ......23°C/W Lead Temperature (soldering, 10s) .................................+260°C
Operating Temperature Range Soldering Temperature (reflow, 2 times max)..................+260°C
DS3231S ..............................................................0°C to +70°C (See the Handling, PC Board Layout, and Assembly section.)
DS3231SN ........................................................-40°C to +85°C

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

(TA = TMIN to TMAX, unless otherwise noted.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC 2.3 3.3 5.5 V
Supply Voltage
VBAT 2.3 3.0 5.5 V
0.7 x VCC +
Logic 1 Input SDA, SCL VIH V
VCC 0.3
0.3 x
Logic 0 Input SDA, SCL VIL -0.3 V
VCC

ELECTRICAL CHARACTERISTICS
(VCC = 2.3V to 5.5V, VCC = Active Supply (see Table 1), TA = TMIN to TMAX, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC = 3.63V 200
Active Supply Current ICCA (Notes 4, 5) μA
VCC = 5.5V 300
I2C bus inactive, 32kHz VCC = 3.63V 110
Standby Supply Current ICCS output on, SQW output off μA
(Note 5) VCC = 5.5V 170

I2C bus inactive, 32kHz VCC = 3.63V 575

Temperature Conversion Current ICCSCONV μA
output on, SQW output off VCC = 5.5V 650
Power-Fail Voltage VPF 2.45 2.575 2.70 V
Logic 0 Output, 32kHz,
VOL I OL = 3mA 0.4 V
INT/SQW, SDA
Logic 0 Output, RST VOL I OL = 1mA 0.4 V
Output Leakage Current 32kHz,
ILO Output high impedance -1 0 +1 μA
INT/SQW, SDA
Input Leakage SCL ILI -1 +1 μA
RST Pin I/O Leakage I OL RST high impedance (Note 6) -200 +10 μA
VBAT Leakage Current
IBATLKG 25 100 nA
(VCC Active)

2 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.3V to 5.5V, VCC = Active Supply (see Table 1), TA = TMIN to TMAX, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency f OUT VCC = 3.3V or VBAT = 3.3V 32.768 kHz
VCC = 3.3V or 0°C to +40°C ±2
Frequency Stability vs.

f/f OUT VBAT = 3.3V, ppm
Temperature (Commercial)
aging offset = 00h >40°C to +70°C ±3.5

VCC = 3.3V or -40°C to <0°C ±3.5

Frequency Stability vs.

f/f OUT VBAT = 3.3V, 0°C to +40°C ±2 ppm
Temperature (Industrial)
aging offset = 00h >40°C to +85°C ±3.5
Frequency Stability vs. Voltage
f/V 1 ppm/V
-40°C 0.7
Trim Register Frequency +25°C 0.1

f/LSB Specified at: ppm
Sensitivity per LSB +70°C 0.4
+85°C 0.8
Temperature Accuracy Temp VCC = 3.3V or VBAT = 3.3V -3 +3 °C
After reflow, First year ±1.0
Crystal Aging
f/f O ppm
not production tested 0–10 years ±5.0

ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBAT = 2.3V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EOSC = 0, BBSQW = 0, VBAT = 3.63V 70
Active Battery Current IBATA μA
SCL = 400kHz (Note 5) VBAT = 5.5V 150
EOSC = 0, BBSQW = 0, VBAT = 3.63V 0.84 3.0
EN32kHz = 1,
Timekeeping Battery Current IBATT μA
SCL = SDA = 0V or
SCL = SDA = VBAT (Note 5) VBAT = 5.5V 1.0 3.5

EOSC = 0, BBSQW = 0, VBAT = 3.63V 575

Temperature Conversion Current IBATTC SCL = SDA = 0V or μA
SCL = SDA = VBAT VBAT = 5.5V 650

Data-Retention Current IBATTDR EOSC = 1, SCL = SDA = 0V, +25°C 100 nA

Maxim Integrated 3
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX) or VBAT = VBAT(MIN) to VBAT(MAX), VBAT > VCC, TA = TMIN to TMAX, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Fast mode 100 400
SCL Clock Frequency f SCL kHz
Standard mode 0 100
Bus Free Time Between STOP Fast mode 1.3
tBUF μs
and START Conditions Standard mode 4.7
Hold Time (Repeated) START Fast mode 0.6
tHD:STA μs
Condition (Note 7) Standard mode 4.0
Fast mode 1.3
Low Period of SCL Clock tLOW μs
Standard mode 4.7
Fast mode 0.6
High Period of SCL Clock tHIGH μs
Standard mode 4.0
Fast mode 0 0.9
Data Hold Time (Notes 8, 9) tHD:DAT μs
Standard mode 0 0.9
Fast mode 100
Data Setup Time (Note 10) t SU:DAT ns
Standard mode 250
Fast mode 0.6
START Setup Time t SU:STA μs
Standard mode 4.7
Rise Time of Both SDA and SCL Fast mode 20 + 300
tR ns
Signals (Note 11) Standard mode 0.1CB 1000
Fall Time of Both SDA and SCL Fast mode 20 + 300
tF ns
Signals (Note 11) Standard mode 0.1CB 300
Fast mode 0.6
Setup Time for STOP Condition t SU:STO μs
Standard mode 4.7
Capacitive Load for Each Bus
CB (Note 11) 400 pF
Line
Capacitance for SDA, SCL CI/O 10 pF
Pulse Width of Spikes That Must
t SP 30 ns
Be Suppressed by the Input Filter
Pushbutton Debounce PBDB 250 ms
Reset Active Time tRST 250 ms
Oscillator Stop Flag (OSF) Delay t OSF (Note 12) 100 ms
Temperature Conversion Time tCONV 125 200 ms

POWER-SWITCH CHARACTERISTICS
(TA = TMIN to TMAX)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC Fall Time; VPF(MAX) to
t VCCF 300 μs
VPF(MIN)
VCC Rise Time; V PF(MIN) to
t VCCR 0 μs
VPF(MAX)
Recovery at Power-Up tREC (Note 13) 250 300 ms

4 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Pushbutton Reset Timing

RST

PBDB tRST

Power-Switch Timing

VCC
VPF(MAX)
VPF VPF
VPF(MIN)

tVCCF tVCCR

tREC

RST

Maxim Integrated 5
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Data Transfer on I2C Serial Bus

SDA

tBUF tSP
tHD:STA
tLOW tR tF

SCL

tHD:STA tHIGH tSU:STA

tSU:STO
STOP START tSU:DAT REPEATED
START
tHD:DAT

WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: ICCA—SCL clocking at max frequency = 400kHz.
Note 5: Current is the averaged input current, which includes the temperature conversion current.
Note 6: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC.
Note 7: After this period, the first clock pulse is generated.
Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 9: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 11: CB—total capacitance of one bus line in pF.
Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ 3.4V.
Note 13: This delay applies only if the oscillator is enabled and running. If the EOSC bit is a 1, tREC is bypassed and RST immedi-
ately goes high. The state of RST does not affect the I2C interface, RTC, or TCXO.

6 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)

STANDBY SUPPLY CURRENT SUPPLY CURRENT

vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
150 1.2

DS3231 toc01

DS3231 toc02
BSY = 0, SCL = SDA = VCC VCC = 0V, BSY = 0,
SDA = SCL = VBAT OR VCC
125 1.1
RST ACTIVE

100 1.0
EN32kHz = 1
ICCS (μA)

IBAT (μA)
75 0.9
EN32kHz = 0
50 0.8

25 0.7

0 0.6
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.3 3.3 4.3 5.3
VCC (V) VBAT (V)

SUPPLY CURRENT FREQUENCY DEVIATION

vs. TEMPERATURE vs. TEMPERATURE vs. AGING VALUE
1.0
DS3231 toc03

DS3231 toc04
VCC = 0, EN32kHz = 1, BSY = 0, 60
SDA = SCL = VBAT OR GND
50 -128
FREQUENCY DEVIATION (ppm)

0.9 40 -33
30
IBAT (μA)

20 0
0.8 10
0
-10
0.7
-20 32
127
-30
0.6 -40
-40 -15 10 35 60 85 -40 -15 10 35 60 85
TEMPERATURE (°C) TEMPERATURE (°C)

DELTA TIME AND FREQUENCY

vs. TEMPERATURE
DS3231 toc05
20
0 0
-20 CRYSTAL
+20ppm
DELTA FREQUENCY (ppm)

DELTA TIME (MIN/YEAR)

-40 -20
-60 TYPICAL CRYSTAL,
UNCOMPENSATED
-80 -40
-100 DS3231
CRYSTAL ACCURACY
-120 -60
-20ppm BAND
-140
-160 -80
-180
-200 -100
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)

Maxim Integrated 7
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Block Diagram

32kHz
OSCILLATOR AND
X1
CAPACITOR ARRAY N

CONTROL LOGIC/ SQUARE-WAVE BUFFER;

DIVIDER INT/SQW CONTROL INT/SQW
X2
1Hz
N

VCC
VBAT TEMPERATURE ALARM, STATUS, AND
POWER CONTROL
SENSOR CONTROL REGISTERS
GND

1Hz
CLOCK AND CALENDAR
REGISTERS
SCL
I2C INTERFACE AND
ADDRESS REGISTER
DECODE
SDA USER BUFFER
(7 BYTES)
VCC

VOLTAGE REFERENCE; RST

DEBOUNCE CIRCUIT;
DS3231 PUSHBUTTON RESET N

8 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Pin Description
PIN NAME FUNCTION
32kHz Output. This open-drain pin requires an external pullup resistor. When enabled, the output operates
1 32kHz
on either power supply. It may be left open if not used.
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1μF to 1.0μF capacitor.
2 VCC
If not used, connect to ground.
Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor
connected to a supply at 5.5V or less. This multifunction pin is determined by the state of the INTCN bit in
the Control Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency
is determined by RS2 and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping
3 INT/SQW
registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the
INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms
disabled. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC. If not used, this pin can
be left unconnected.
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the
VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the RST
pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with a
4 RST
debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an
internal 50k
nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the
oscillator is disabled, tREC is bypassed and RST immediately goes high.
5–12 N.C. No Connection. Must be connected to ground.
13 GND Ground
Backup Power-Supply Input. When using the device with the VBAT input as the primary power source, this
pin should be decoupled using a 0.1μF to 1.0μF low-leakage capacitor. When using the device with the
14 VBAT VBAT input as the backup power source, the capacitor is not required. If VBAT is not used, connect to ground.
The device is UL recognized to ensure against reverse charging when used with a primary lithium battery.
Go to www.maximintegrated.com/qa/info/ul.
Serial Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin
15 SDA
requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC.
Serial Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data
16 SCL
movement on the serial interface. Up to 5.5V can be used for this pin, regardless of the voltage on VCC.

Detailed Description clock operates in either the 24-hour or 12-hour format

with an AM/PM indicator. The internal registers are
The DS3231 is a serial RTC driven by a temperature-
accessible though an I2C bus interface.
compensated 32kHz crystal oscillator. The TCXO pro-
vides a stable and accurate reference clock, and A temperature-compensated voltage reference and
maintains the RTC to within ±2 minutes per year accu- comparator circuit monitors the level of VCC to detect
racy from -40°C to +85°C. The TCXO frequency output power failures and to automatically switch to the back-
is available at the 32kHz pin. The RTC is a low-power up supply when necessary. The RST pin provides an
clock/calendar with two programmable time-of-day external pushbutton function and acts as an indicator
alarms and a programmable square-wave output. The of a power-fail event.
INT/SQW provides either an interrupt signal due to
alarm conditions or a square-wave output. The clock/cal-
Operation
endar provides seconds, minutes, hours, day, date, The block diagram shows the main elements of the
month, and year information. The date at the end of the DS3231. The eight blocks can be grouped into four
month is automatically adjusted for months with fewer functional groups: TCXO, power control, pushbutton
than 31 days, including corrections for leap year. The function, and RTC. Their operations are described sep-
arately in the following sections.

Maxim Integrated 9
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
32kHz TCXO active battery current, IBATA, is drawn. When the serial
The temperature sensor, oscillator, and control logic interface is inactive, timekeeping current (IBATT), which
form the TCXO. The controller reads the output of the includes the averaged temperature conversion current,
on-chip temperature sensor and uses a lookup table to IBATTC, is used (refer to Application Note 3644: Power
determine the capacitance required, adds the aging Considerations for Accurate Real-Time Clocks for
correction in AGE register, and then sets the capaci- details). Temperature conversion current, IBATTC, is
tance selection registers. New values, including specified since the system must be able to support the
changes to the AGE register, are loaded only when a periodic higher current pulse and still maintain a valid
change in the temperature value occurs, or when a voltage level. Data retention current, IBATTDR, is the
user-initiated temperature conversion is completed. current drawn by the part when the oscillator is
Temperature conversion occurs on initial application of stopped (EOSC = 1). This mode can be used to mini-
VCC and once every 64 seconds afterwards. mize battery requirements for times when maintaining
time and date information is not necessary, e.g., while
Power Control the end system is waiting to be shipped to a customer.
This function is provided by a temperature-compensat-
ed voltage reference and a comparator circuit that Pushbutton Reset Function
monitors the VCC level. When VCC is greater than VPF, The DS3231 provides for a pushbutton switch to be
the part is powered by VCC. When VCC is less than VPF connected to the RST output pin. When the DS3231 is
but greater than VBAT, the DS3231 is powered by VCC. not in a reset cycle, it continuously monitors the RST
If V CC is less than V PF and is less than V BAT , the signal for a low going edge. If an edge transition is
device is powered by VBAT. See Table 1. detected, the DS3231 debounces the switch by pulling
the RST low. After the internal timer has expired
Table 1. Power Control (PBDB), the DS3231 continues to monitor the RST line.
If the line is still low, the DS3231 continuously monitors
SUPPLY CONDITION ACTIVE SUPPLY the line looking for a rising edge. Upon detecting
VCC < V PF, VCC < VBAT VBAT release, the DS3231 forces the RST pin low and holds it
low for tRST.
VCC < V PF, VCC > VBAT VCC
VCC > V PF, VCC < VBAT VCC RST is also used to indicate a power-fail condition.
When VCC is lower than VPF, an internal power-fail sig-
VCC > V PF, VCC > VBAT VCC
nal is generated, which forces the RST pin low. When
VCC returns to a level above VPF, the RST pin is held
To preserve the battery, the first time VBAT is applied to low for approximately 250ms (tREC) to allow the power
the device, the oscillator will not start up until V CC supply to stabilize. If the oscillator is not running (see
exceeds VPF, or until a valid I2C address is written to the Power Control section) when VCC is applied, tREC is
the part. Typical oscillator startup time is less than one bypassed and RST immediately goes high. Assertion of
second. Approximately 2 seconds after VCC is applied, the RST output, whether by pushbutton or power-fail
or a valid I2C address is written, the device makes a detection, does not affect the internal operation of the
temperature measurement and applies the calculated DS3231.
correction to the oscillator. Once the oscillator is run-
ning, it continues to run as long as a valid power Real-Time Clock
source is available (VCC or VBAT), and the device con- With the clock source from the TCXO, the RTC provides
tinues to measure the temperature and correct the seconds, minutes, hours, day, date, month, and year
oscillator frequency every 64 seconds. information. The date at the end of the month is auto-
matically adjusted for months with fewer than 31 days,
On the first application of power (VCC) or when a valid including corrections for leap year. The clock operates
I2C address is written to the part (VBAT), the time and in either the 24-hour or 12-hour format with an AM/PM
date registers are reset to 01/01/00 01 00:00:00 indicator.
(DD/MM/YY DOW HH:MM:SS).
The clock provides two programmable time-of-day
VBAT Operation alarms and a programmable square-wave output. The
There are several modes of operation that affect the INT/SQW pin either generates an interrupt due to alarm
amount of VBAT current that is drawn. While the device condition or outputs a square-wave signal and the
is powered by VBAT and the serial interface is active, selection is controlled by the bit INTCN.

10 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Figure 1. Timekeeping Registers
BIT 7 BIT 0
ADDRESS BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 FUNCTION RANGE
MSB LSB
00h 0 10 Seconds Seconds Seconds 00–59
01h 0 10 Minutes Minutes Minutes 00–59
AM/PM 1–12 + AM/PM
02h 0 12/24 10 Hour Hour Hours
20 Hour 00–23
03h 0 0 0 0 0 Day Day 1–7
04h 0 0 10 Date Date Date 01–31
Month/ 01–12 +
05h Century 0 0 10 Month Month
Century Century
06h 10 Year Year Year 00–99
07h A1M1 10 Seconds Seconds Alarm 1 Seconds 00–59
08h A1M2 10 Minutes Minutes Alarm 1 Minutes 00–59
AM/PM 1–12 + AM/PM
09h A1M3 12/24 10 Hour Hour Alarm 1 Hours
20 Hour 00–23
Day Alarm 1 Day 1–7
0Ah A1M4 DY/DT 10 Date
Date Alarm 1 Date 1–31
0Bh A2M2 10 Minutes Minutes Alarm 2 Minutes 00–59
AM/PM 1–12 + AM/PM
0Ch A2M3 12/24 10 Hour Hour Alarm 2 Hours
20 Hour 00–23
Day Alarm 2 Day 1–7
0Dh A2M4 DY/DT 10 Date
Date Alarm 2 Date 1–31
0Eh EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE Control —
0Fh OSF 0 0 0 EN32kHz BSY A2F A1F Control/Status —
10h SIGN DATA DATA DATA DATA DATA DATA DATA Aging Offset —
11h SIGN DATA DATA DATA DATA DATA DATA DATA MSB of Temp —
12h DATA DATA 0 0 0 0 0 0 LSB of Temp —
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.

Address Map event, it is possible that the microcontroller and

DS3231 I 2C communications could become unsyn-
Figure 1 shows the address map for the DS3231 time-
chronized, e.g., the microcontroller resets while read-
keeping registers. During a multibyte access, when the
ing data from the DS3231. When the microcontroller
address pointer reaches the end of the register space
resets, the DS3231 I2C interface may be placed into a
(12h), it wraps around to location 00h. On an I 2 C
known state by toggling SCL until SDA is observed to
START or address pointer incrementing to location 00h,
be at a high level. At that point the microcontroller
the current time is transferred to a second set of regis-
should pull SDA low while SCL is high, generating a
ters. The time information is read from these secondary
START condition.
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the Clock and Calendar
main registers update during a read.
The time and calendar information is obtained by read-
I2C Interface ing the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
The I2C interface is accessible whenever either VCC or
or initialized by writing the appropriate register bytes.
VBAT is at a valid level. If a microcontroller connected
The contents of the time and calendar registers are in
to the DS3231 resets because of a loss of VCC or other

Maxim Integrated 11
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
the binary-coded decimal (BCD) format. The DS3231 Alarms
can be run in either 12-hour or 24-hour mode. Bit 6 of
The DS3231 contains two time-of-day/date alarms.
the hours register is defined as the 12- or 24-hour
Alarm 1 can be set by writing to registers 07h to 0Ah.
mode select bit. When high, the 12-hour mode is
Alarm 2 can be set by writing to registers 0Bh to 0Dh.
selected. In the 12-hour mode, bit 5 is the AM/PM bit
The alarms can be programmed (by the alarm enable
with logic-high being PM. In the 24-hour mode, bit 5 is
and INTCN bits of the control register) to activate the
the 20-hour bit (20–23 hours). The century bit (bit 7 of
INT/SQW output on an alarm match condition. Bit 7 of
the month register) is toggled when the years register
each of the time-of-day/date alarm registers are mask
overflows from 99 to 00.
bits (Table 2). When all the mask bits for each alarm
The day-of-week register increments at midnight. are logic 0, an alarm only occurs when the values in the
Values that correspond to the day of week are user- timekeeping registers match the corresponding values
defined but must be sequential (i.e., if 1 equals stored in the time-of-day/date alarm registers. The
Sunday, then 2 equals Monday, and so on). Illogical alarms can also be programmed to repeat every sec-
time and date entries result in undefined operation. ond, minute, hour, day, or date. Table 2 shows the pos-
When reading or writing the time and date registers, sec- sible settings. Configurations not listed in the table will
ondary (user) buffers are used to prevent errors when result in illogical operation.
the internal registers update. When reading the time and The DY/DT bits (bit 6 of the alarm day/date registers)
date registers, the user buffers are synchronized to the control whether the alarm value stored in bits 0 to 5 of
internal registers on any START and when the register that register reflects the day of the week or the date of
pointer rolls over to zero. The time information is read the month. If DY/DT is written to logic 0, the alarm will
from these secondary registers, while the clock contin- be the result of a match with date of the month. If
ues to run. This eliminates the need to reread the regis- DY/DT is written to logic 1, the alarm will be the result of
ters in case the main registers update during a read. a match with day of the week.
The countdown chain is reset whenever the seconds regis- When the RTC register values match alarm register set-
ter is written. Write transfers occur on the acknowledge tings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
from the DS3231. Once the countdown chain is reset, to set to logic 1. If the corresponding Alarm Interrupt
avoid rollover issues the remaining time and date registers Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the
must be written within 1 second. The 1Hz square-wave out- INTCN bit is set to logic 1, the alarm condition will acti-
put, if enabled, transitions high 500ms after the seconds vate the INT/SQW signal. The match is tested on the
data transfer, provided the oscillator is already running. once-per-second update of the time and date registers.

Table 2. Alarm Mask Bits

ALARM 1 REGISTER MASK BITS (BIT 7)
DY/DT ALARM RATE
A1M4 A1M3 A1M2 A1M1
X 1 1 1 1 Alarm once per second
X 1 1 1 0 Alarm when seconds match
X 1 1 0 0 Alarm when minutes and seconds match
X 1 0 0 0 Alarm when hours, minutes, and seconds match
0 0 0 0 0 Alarm when date, hours, minutes, and seconds match
1 0 0 0 0 Alarm when day, hours, minutes, and seconds match

ALARM 2 REGISTER MASK BITS (BIT 7)

DY/DT ALARM RATE
A2M4 A2M3 A2M2
X 1 1 1 Alarm once per minute (00 seconds of every minute)
X 1 1 0 Alarm when minutes match
X 1 0 0 Alarm when hours and minutes match
0 0 0 0 Alarm when date, hours, and minutes match
1 0 0 0 Alarm when day, hours, and minutes match

12 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Control Register (0Eh)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE
POR: 0 0 0 1 1 1 0 0

Special-Purpose Registers shows the square-wave frequencies that can be select-

ed with the RS bits. These bits are both set to logic 1
The DS3231 has two additional registers (control and
(8.192kHz) when power is first applied.
status) that control the real-time clock, alarms, and
square-wave output. SQUARE-WAVE OUTPUT FREQUENCY
Control Register (0Eh) SQUARE-WAVE OUTPUT
Bit 7: Enable Oscillator (EOSC). When set to logic 0, RS2 RS1
FREQUENCY
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped when the DS3231 switches to VBAT. This 0 0 1Hz
bit is clear (logic 0) when power is first applied. When 0 1 1.024kHz
the DS3231 is powered by VCC, the oscillator is always 1 0 4.096kHz
on regardless of the status of the EOSC bit. When
1 1 8.192kHz
EOSC is disabled, all register data is static.
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). When set to logic 1 with INTCN = 0 and VCC Bit 2: Interrupt Control (INTCN). This bit controls the
< VPF, this bit enables the square wave. When BBSQW INT/SQW signal. When the INTCN bit is set to logic 0, a
is logic 0, the INT/SQW pin goes high impedance when square wave is output on the INT/SQW pin. When the
VCC < VPF. This bit is disabled (logic 0) when power is INTCN bit is set to logic 1, then a match between the
first applied. timekeeping registers and either of the alarm registers
activates the INT/SQW output (if the alarm is also
Bit 5: Convert Temperature (CONV). Setting this bit to enabled). The corresponding alarm flag is always set
1 forces the temperature sensor to convert the temper- regardless of the state of the INTCN bit. The INTCN bit
ature into digital code and execute the TCXO algorithm is set to logic 1 when power is first applied.
to update the capacitance array to the oscillator. This
can only happen when a conversion is not already in Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
progress. The user should check the status bit BSY logic 1, this bit permits the alarm 2 flag (A2F) bit in the
before forcing the controller to start a new TCXO exe- status register to assert INT/SQW (when INTCN = 1).
cution. A user-initiated temperature conversion does When the A2IE bit is set to logic 0 or INTCN is set to
not affect the internal 64-second update cycle. logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
A user-initiated temperature conversion does not affect applied.
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conver- Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
sion is finished, at which time both CONV and BSY go logic 1, this bit permits the alarm 1 flag (A1F) bit in the
to 0. The CONV bit should be used when monitoring status register to assert INT/SQW (when INTCN = 1).
the status of a user-initiated conversion. When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the INT/SQW sig-
Bits 4 and 3: Rate Select (RS2 and RS1). These bits nal. The A1IE bit is disabled (logic 0) when power is
control the frequency of the square-wave output when first applied.
the square wave has been enabled. The following table

Maxim Integrated 13
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Status Register (0Fh)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: OSF 0 0 0 EN32kHz BSY A2F A1F
POR: 1 0 0 0 1 X X X

Status Register (0Fh) ters. If the A1IE bit is logic 1 and the INTCN bit is set to
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit logic 1, the INT/SQW pin is also asserted. A1F is
indicates that the oscillator either is stopped or was cleared when written to logic 0. This bit can only be
stopped for some period and may be used to judge the written to logic 0. Attempting to write to logic 1 leaves
validity of the timekeeping data. This bit is set to logic 1 the value unchanged.
any time that the oscillator stops. The following are exam-
ples of conditions that can cause the OSF bit to be set: Aging Offset
1) The first time power is applied. The aging offset register takes a user-provided value to
add to or subtract from the codes in the capacitance
2) The voltages present on both VCC and VBAT are array registers. The code is encoded in two’s comple-
insufficient to support oscillation. ment, with bit 7 representing the sign bit. One LSB rep-
3) The EOSC bit is turned off in battery-backed mode. resents one small capacitor to be switched in or out of
4) External influences on the crystal (i.e., noise, leak- the capacitance array at the crystal pins. The aging off-
age, etc.). set register capacitance value is added or subtracted
from the capacitance value that the device calculates
This bit remains at logic 1 until written to logic 0. for each temperature compensation. The offset register
Bit 3: Enable 32kHz Output (EN32kHz). This bit con- is added to the capacitance array during a normal tem-
trols the status of the 32kHz pin. When set to logic 1, the perature conversion, if the temperature changes from
32kHz pin is enabled and outputs a 32.768kHz square- the previous conversion, or during a manual user con-
wave signal. When set to logic 0, the 32kHz pin goes to version (setting the CONV bit). To see the effects of the
a high-impedance state. The initial power-up state of aging register on the 32kHz output frequency immedi-
this bit is logic 1, and a 32.768kHz square-wave signal ately, a manual conversion should be started after each
appears at the 32kHz pin after a power source is aging register change.
applied to the DS3231 (if the oscillator is running). Positive aging values add capacitance to the array,
Bit 2: Busy (BSY). This bit indicates the device is busy slowing the oscillator frequency. Negative values
executing TCXO functions. It goes to logic 1 when the remove capacitance from the array, increasing the
conversion signal to the temperature sensor is asserted oscillator frequency.
and then is cleared when the device is in the 1-minute The change in ppm per LSB is different at different
idle state. temperatures. The frequency vs. temperature curve is
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag shifted by the values used in this register. At +25°C,
bit indicates that the time matched the alarm 2 regis- one LSB typically provides about 0.1ppm change in
ters. If the A2IE bit is logic 1 and the INTCN bit is set to frequency.
logic 1, the INT/SQW pin is also asserted. A2F is Use of the aging register is not needed to achieve the
cleared when written to logic 0. This bit can only be accuracy as defined in the EC tables, but could be
written to logic 0. Attempting to write to logic 1 leaves used to help compensate for aging at a given tempera-
the value unchanged. ture. See the Typical Operating Characteristics section
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag for a graph showing the effect of the register on accu-
bit indicates that the time matched the alarm 1 regis- racy over temperature.

Aging Offset (10h)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: Sign Data Data Data Data Data Data Data
POR: 0 0 0 0 0 0 0 0

14 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Temperature Register (Upper Byte) (11h)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: Sign Data Data Data Data Data Data Data
POR: 0 0 0 0 0 0 0 0

Temperature Register (Lower Byte) (12h)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: Data Data 0 0 0 0 0 0
POR: 0 0 0 0 0 0 0 0

Temperature Registers (11h–12h) line while the clock line is high are interpreted as
control signals.
Temperature is represented as a 10-bit code with a res-
olution of 0.25°C and is accessible at location 11h and Accordingly, the following bus conditions have been
12h. The temperature is encoded in two’s complement defined:
format. The upper 8 bits, the integer portion, are at Bus not busy: Both data and clock lines remain
location 11h and the lower 2 bits, the fractional portion, high.
are in the upper nibble at location 12h. For example,
START data transfer: A change in the state of the
00011001 01b = +25.25°C. Upon power reset, the reg-
data line from high to low, while the clock line is high,
isters are set to a default temperature of 0°C and the
defines a START condition.
controller starts a temperature conversion. The temper-
ature is read on initial application of VCC or I2C access STOP data transfer: A change in the state of the
on VBAT and once every 64 seconds afterwards. The data line from low to high, while the clock line is high,
temperature registers are updated after each user-initi- defines a STOP condition.
ated conversion and on every 64-second conversion. Data valid: The state of the data line represents
The temperature registers are read-only. valid data when, after a START condition, the data
line is stable for the duration of the high period of the
I2C Serial Data Bus clock signal. The data on the line must be changed
The DS3231 supports a bidirectional I2C bus and data during the low period of the clock signal. There is
transmission protocol. A device that sends data onto one clock pulse per bit of data.
the bus is defined as a transmitter and a device receiv-
Each data transfer is initiated with a START condition
ing data is defined as a receiver. The device that con-
and terminated with a STOP condition. The number
trols the message is called a master. The devices that
of data bytes transferred between the START and
are controlled by the master are slaves. The bus must
the STOP conditions is not limited, and is determined
be controlled by a master device that generates the
by the master device. The information is transferred
serial clock (SCL), controls the bus access, and gener-
byte-wise and each receiver acknowledges with a
ates the START and STOP conditions. The DS3231
ninth bit.
operates as a slave on the I2C bus. Connections to the
bus are made through the SCL input and open-drain Acknowledge: Each receiving device, when
SDA I/O lines. Within the bus specifications, a standard addressed, is obliged to generate an acknowledge
mode (100kHz maximum clock rate) and a fast mode after the reception of each byte. The master device
(400kHz maximum clock rate) are defined. The DS3231 must generate an extra clock pulse, which is associ-
works in both modes. ated with this acknowledge bit.
The following bus protocol has been defined (Figure 2): A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
• Data transfer may be initiated only when the bus is
way that the SDA line is stable low during the high
not busy.
period of the acknowledge-related clock pulse. Of
• During data transfer, the data line must remain stable course, setup and hold times must be taken into
whenever the clock line is high. Changes in the data account. A master must signal an end of data to the

Maxim Integrated 15
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

SDA

MSB

SLAVE ADDRESS R/W ACKNOWLEDGEMENT

DIRECTION SIGNAL FROM RECEIVER
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER

SCL
1 2 6 7 8 9 1 2 3–7 8 9

ACK ACK
Figure 2. I2C Data Transfer Overview

slave by not generating an acknowledge bit on the the slave address. Next follows a number of data
last byte that has been clocked out of the slave. In bytes. The slave returns an acknowledge bit after
this case, the slave must leave the data line high to each received byte. Data is transferred with the most
enable the master to generate the STOP condition. significant bit (MSB) first.
Figures 3 and 4 detail how data transfer is accom- Data transfer from a slave transmitter to a master
plished on the I2C bus. Depending upon the state of receiver. The first byte (the slave address) is trans-
the R/W bit, two types of data transfer are possible: mitted by the master. The slave then returns an
Data transfer from a master transmitter to a slave acknowledge bit. Next follows a number of data
receiver. The first byte transmitted by the master is bytes transmitted by the slave to the master. The

<SLAVE
ADDRESS> <R/W> <WORD ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)

S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P

S - START
SLAVE TO MASTER MASTER TO SLAVE
A - ACKNOWLEDGE (ACK)
P - STOP DATA TRANSFERRED
R/W - READ/WRITE OR DIRECTION BIT ADDRESS (X + 1 BYTES + ACKNOWLEDGE)

Figure 3. Data Write—Slave Receiver Mode

<SLAVE
ADDRESS> <R/W> <DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>

S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P

S - START MASTER TO SLAVE SLAVE TO MASTER

A - ACKNOWLEDGE (ACK) DATA TRANSFERRED
P - STOP (X + 1 BYTES + ACKNOWLEDGE)
A - NOT ACKNOWLEDGE (NACK) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
R/W - READ/WRITE OR DIRECTION BIT ADDRESS

Figure 4. Data Read—Slave Transmitter Mode

16 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

<SLAVE
ADDRESS> <R/W> <WORD ADDRESS (n)> <SLAVE ADDRESS (n)> <R/W>

S 1101000 0 A XXXXXXXX A Sr 1101000 1 A

<DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>

XXXXXXXX A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P

S - START MASTER TO SLAVE SLAVE TO MASTER

Sr - REPEATED START
A - ACKNOWLEDGE (ACK) DATA TRANSFERRED
P - STOP (X + 1 BYTES + ACKNOWLEDGE)
A - NOT ACKNOWLEDGE (NACK) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
R/W - READ/WRITE OR DIRECTION BIT ADDRESS

Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit

master returns an acknowledge bit after all received acknowledging the transfer. The master may then
bytes other than the last byte. At the end of the last transmit zero or more bytes of data, with the DS3231
received byte, a not acknowledge is returned. acknowledging each byte received. The register
The master device generates all the serial clock puls- pointer increments after each data byte is trans-
es and the START and STOP conditions. A transfer is ferred. The master generates a STOP condition to
ended with a STOP condition or with a repeated terminate the data write.
START condition. Since a repeated START condition Slave transmitter mode (DS3231 read mode): The
is also the beginning of the next serial transfer, the first byte is received and handled as in the slave
bus will not be released. Data is transferred with the receiver mode. However, in this mode, the direction
most significant bit (MSB) first. bit indicates that the transfer direction is reversed.
The DS3231 can operate in the following two modes: Serial data is transmitted on SDA by the DS3231
while the serial clock is input on SCL. START and
Slave receiver mode (DS3231 write mode): Serial STOP conditions are recognized as the beginning
data and clock are received through SDA and SCL. and end of a serial transfer. Address recognition is
After each byte is received, an acknowledge bit is performed by hardware after reception of the slave
transmitted. START and STOP conditions are recog- address and direction bit. The slave address byte is
nized as the beginning and end of a serial transfer. the first byte received after the master generates a
Address recognition is performed by hardware after START condition. The slave address byte contains
reception of the slave address and direction bit. The the 7-bit DS3231 address, which is 1101000, fol-
slave address byte is the first byte received after the lowed by the direction bit (R/W), which is 1 for a
master generates the START condition. The slave read. After receiving and decoding the slave
address byte contains the 7-bit DS3231 address, address byte, the DS3231 outputs an acknowledge
which is 1101000, followed by the direction bit (R/W), on SDA. The DS3231 then begins to transmit data
which is 0 for a write. After receiving and decoding starting with the register address pointed to by the
the slave address byte, the DS3231 outputs an register pointer. If the register pointer is not written to
acknowledge on SDA. After the DS3231 acknowl- before the initiation of a read mode, the first address
edges the slave address + write bit, the master that is read is the last one stored in the register point-
transmits a word address to the DS3231. This sets er. The DS3231 must receive a not acknowledge to
the register pointer on the DS3231, with the DS3231 end a read.

Maxim Integrated 17
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Handling, PC Board Layout, signal line. All N.C. (no connect) pins must be connect-
ed to ground.
and Assembly
Moisture-sensitive packages are shipped from the fac-
The DS3231 package contains a quartz tuning-fork tory dry packed. Handling instructions listed on the
crystal. Pick-and-place equipment can be used, but package label must be followed to prevent damage
precautions should be taken to ensure that excessive during reflow. Refer to the IPC/JEDEC J-STD-020 stan-
shocks are avoided. Ultrasonic cleaning should be dard for moisture-sensitive device (MSD) classifications
avoided to prevent damage to the crystal. and reflow profiles. Exposure to reflow is limited to 2
Avoid running signal traces under the package, unless times maximum.
a ground plane is placed between the package and the

Pin Configuration Chip Information

SUBSTRATE CONNECTED TO GROUND
TOP VIEW PROCESS: CMOS
Package Information
32kHz 1 16 SCL For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
VCC 2 15 SDA
“+”, “#”, or “-” in the package code indicates RoHS status only.
INT/SQW 3 14 VBAT Package drawings may show a different suffix character, but the
RST 4 DS3231 13 GND
drawing pertains to the package regardless of RoHS status.

N.C. 5 12 N.C. PACKAGE PACKAGE OUTLINE LAND

TYPE CODE NO. PATTERN NO.
N.C. 6 11 N.C.
16 SO W16#H2 21-0042 90-0107
N.C. 7 10 N.C.

N.C. 8 9 N.C.

SO

18 Maxim Integrated
 DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 1/05 Initial release. —
Changed Digital Temp Sensor Output from ±2°C to ±3°C. 1, 3
Updated Typical Operating Circuit. 1
1 2/05
Changed TA = -40°C to +85°C to TA = TMIN to TMAX. 2, 3, 4
Updated Block Diagram. 8
Added “UL Recognized” to Features; added lead-free packages and removed S from
top mark info in Ordering Information table; added ground connections to the N.C. pin 1
in the Typical Operating Circuit.
Added “noncondensing” to operating temperature range; changed VPF MIN from 2.35V
2
to 2.45V.
Added aging offset specification. 3
Relabeled TOC4. 7
Added arrow showing input on X1 in the Block Diagram. 8
Updated pin descriptions for VCC and VBAT. 9
2 6/05
Added the I2C Interface section. 10
Figure 1: Added sign bit to aging and temperature registers; added MSB and LSB. 11
Corrected title for rate select bits frequency table. 13
Added note that frequency stability over temperature spec is with aging offset register
14
= 00h; changed bit 7 from Data to Sign (Crystal Aging Offset Register).
Changed bit 7 from Data to Sign (Temperature Register); correct pin definitions in I2C
15
Serial Data Bus section.
Modified the Handing, PC Board Layout, and Assembly section to refer to
17
J-STD-020 for reflow profiles for lead-free and leaded packages.
3 11/05 Changed lead-free packages to RoHS-compliant packages. 1
Changed RST and UL bullets in Features. 1
Changed EC condition “VCC > VBAT” to “VCC = Active Supply (see Table 1).” 2, 3
Modified Note 12 to correct tREC operation. 6
Added various conditions text to TOCs 1, 2, and 3. 7
Added text to pin descriptions for 32kHz, VCC, and RST. 9
4 10/06
Table 1: Changed column heading “Powered By” to “Active Supply”; changed
10
“applied” to “exceeds VPF” in the Power Control section.
Indicated BBSQW applies to both SQW and interrupts; simplified temp convert
13
description (bit 5); added “output” to INT/SQW (bit 2).
Changed the Crystal Aging section to the Aging Offset section; changed “this bit
14
indicates” to “this bit controls” for the enable 32kHz output bit.
Added Warning note to EC table notes; updated Note 12. 6
Updated the Typical Operating Characteristics graphs. 7

5 4/08 In the Power Control section, added information about the POR state of the time and
date registers; in the Real-Time Clock section, added to the description of the RST 10
function.
In Figure 1, corrected the months date range for 04h from 00–31 to 01–31. 11

Maxim Integrated 19
DS1086L
3.3V Spread-Spectrum EconOscillator

Revision History (continued)

REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
Updated the Typical Operating Circuit. 1
Removed the V PU parameter from the Recommended DC Operating Conditions table
and added verbiage about the pullup to the Pin Description table for INT/SQW, SDA, 2, 9
and SCL.
Added the Delta Time and Frequency vs. Temperature graph in the Typical Operating
7
Characteristics section.
6 10/08 Updated the Block Diagram. 8
Added the VBAT Operation section, improved some sections of text for the 32kHz
10
TCXO and Pushbutton Reset Function sections.
Added the register bit POR values to the register tables. 13, 14, 15
Updated the Aging Offset and Temperature Registers (11h–12h) sections. 14, 15
Updated the I2C timing diagrams (Figures 3, 4, and 5). 16, 17
Removed the “S” from the top mark in the Ordering Information table and the Pin
7 3/10 1, 18
Configuration to match the packaging engineering marking specification.
Updated the Typical Operating Circuit; removed the “Top Mark” column from the
Ordering Information; in the Absolute Maximum Ratings section, added the theta-JA
and theta-JC thermal resistances and Note 1, and changed the soldering temperature 1, 2, 3, 4, 6,
8 7/10 to +260°C (lead(Pb)-free) and +240°C (leaded); updated the functional description of 9, 11, 12, 13,
the VBAT pin in the Pin Description; changed the timekeeping registers 02h, 09h, and 18
0Ch to “20 Hour” in Bit 5 of Figure 1; updated the BBSQW bit description in the Control
Register (0Eh) section; added the land pattern no. to the Package Information table.
9 1/13 Updated Absolute Maximum Ratings, and last paragraph in Power Control section 2, 10

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

20 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.