Research Statement

Patrick Chiang ([email protected])

Over the past 20 years, Moore’s law scaling of transistor line width has enabled significant improvements in
microchip power dissipation, performance, and cost/computation. However, unknown challenges in future process
scaling will force us to reconsider conventional CMOS analog/digital designs. Having been fortunate to have
worked on over seven fabricated testchips through various research/industrial experiences, I believe I have good
insight on these challenges. Therefore, my research vision is to create new mixed-signal architectures which will
take advantage of the continued advantages of CMOS scaling, like improved transistor speed, while compensating
for the growing disadvantages, such as larger process variations.

Past and Current Research

After obtaining my bachelor’s degree in electrical engineering from Berkeley, I worked as a design engineer at
Datapath Systems, now LSI Logic, designing a DSL analog front-end. Working for Dr. Samuel Sheng, I became
interested in the complexity and innovation involved in circuit design while developing a self-checking standard
cell library, a digital backend for a pipelined A/D, and a switch-capacitor tone acquisition filter in 0.5um
CMOS[1]. Designing the switch-capacitor filter, I observed first-hand the non-idealities in analog circuits, in
which the design required implementation of chopper stabilization to compensate for differential pair offset.

At Stanford, my first research project under Professor Dally was for a multi-university research initiative on
the interdisciplinary application of nonlinear systems towards communications. Working with researchers from
UCLA(Professor Jia Ming-Liu) and UCSD(Professor Larry Larson), the goals were to build a chaotically
modulated, ultrawideband transceiver and to understand how CMOS process variation affects the stability, bit
error rate, and overall effectiveness of non-linear communications systems. A prototype chip was built in 0.25um
CMOS[2], illustrating one of the first and only successful attempts at integration of a complete nonlinear
communications system on a single silicon die. In addition, I also had the experience of presenting research
findings at multiple DOD reviews in San Diego and Washington D.C. and preparing project reviews/summaries.
The process of participating in the entire research process and interacting with other academics, both in other
fields as well as other universities, was extremely rewarding.

My graduate work at Stanford has continued in the area of high speed serial links for chip-to-chip
interconnection. The design of interconnects has been fundamental towards the improvement in computer system
performance, as these links mitigate the disparity between on-chip and off-chip bandwidth. The performance of
these links will continue to be essential in the future, as the need for greater data bandwidth continues to increase
rapidly. At Stanford, in Professor Dally’s and Professor Horowitz’s groups, we have worked on a number of such
links. In particular, I helped my colleague Dr. Edward Lee with two test chips [3,4,5], which achieved low
jitter/power/area 4 Gb/s signaling. These chips compensated for comparator offset voltage by utilizing on-die
switch capacitor calibration.

While these links achieve near optimal performance/power/area at the 1-4Gb/s data rates, conventional
approaches become harder to design and less effective as serial data rates approach 20Gb/s and beyond, where the
necessity for timing accuracy is paramount. With process scaling, multi-phase architectures suffer from clock
phase timing skew (process variation) and supply-induced jitter (supply reduction). My solution to this problem is
to combine the design of the oscillator directly into the transmitter/receiver front-end multiplexers [6]. We used a
10GHz, inductor-based voltage-controlled oscillator and subsumed the capacitance of the interconnect and
multiplexer directly into the resonator, eliminating clock buffers, thereby reducing power and timing uncertainty.

My doctoral work has been in the design and implementation of this technique for a 20Gb/s CMOS
transceiver. Supervising a team of three graduate students, I built two prototype chips in 0.13um CMOS. This
included independently setting up the CAD design environments, inductor characterization, circuit
design/simulation/extraction, test board design, and experimental measurements. The first chip demonstrated a
20Gb/s transmitter with direct resonator/oscillator modulation of the front-end output multiplexer, in 0.43mm2,
consuming 165mW[7,8]. This testchip illustrated a power/area/data rate figure of merit more than 4x of current
architectures. The 2nd generation chip demonstrated a revised 20Gb/s transmitter, with 2-tap transmit pre-
emphasis, along with a new 20Gb/s receiver architecture, using clock down-conversion sampling to achieve data
demultiplexing[9]. By addressing the associated problems of process variability and power supply susceptibility,
this research exhibits new methods to achieve data rates, power, and area unachievable with conventional
techniques. Further, this doctoral research has also exposed me to many of the non-technical aspects of research
which I have enjoyed, such as fostering relationships with fabrication managers, giving invited technical talks at
companies, talking with grant sponsors, and winning a technical design competition award.

Future Research

My research vision is to design new circuit architectures that can achieve greater performance in future CMOS
technologies, leveraging the benefits of scaling’s advantages(improved transistor fT, decreased digital circuit
area/power/cost) against its own disadvantages(power supply reduction, process variability).

One particular area of interest is in scaling analog design performance with the improvements in digital
circuits. Typically, analog circuits have not improved in area, power, or complexity in relation to digital circuits,
because engineers are exceedingly cautious to over-provision designs to meet absolute performance requirements.
Analog designs consume more area and additional power than necessary in order to ensure adequate margins
across process corners. However, guaranteeing absolutes in an uncertain process scaling environment is
increasingly difficult—from the inaccuracy of the process models and various process options to the process
instabilities, mismatches, and design rule nuances. The problem is even more pronounced when we consider the
growing number of analog blocks in system-on-a-chip implementations, where chip yield is highly dependent
upon robustness of each individual analog circuit. Making and completing chips with reasonable design
complexity and fast time to market is becoming both essential and unfortunately, intractable.

One possible solution is for analog circuits to be made adaptable and programmable. As transistors are
essentially free, calibration redundancy can be added virtually everywhere, allowing for design knobs and tweaks
even after the chip has been fabricated. For example, along the front-end of a high speed serial link, on-die sub-
sampling oscilloscopes macros can be placed all along the analog datapath, such as in the front-end samplers,
amplifiers, phase-locked loops, and slicers. These calibration macros can compensate for the capacitance variation
of tighter wiring interconnects and threshold mismatch of smaller, lower power transistors. At a higher level, the
power dissipation of various blocks can be measured and optimized by using bit error rate measurements and other
performance metrics. Such circuit modifications would require new research areas, such as control algorithms for
calibration feedback control and CAD development for optimizing calibration weights/redundancy/layout. With
this research thrust, we can improve future analog design in performance, power, area, design complexity/time,
and yield, and bridge the gap between digital and analog circuits in deep submicron CMOS.

Another example research area is the design of extremely high data rate (20-40GS/s), low-precision analog-to-
digital converters. These converters have a wide number of applications: software-defined radio, ultrawideband
radio front-ends, and high-speed wireline communications. Such converters have typically been reserved for the
domain of exotic materials like SiGe or InP, but there is much interest in CMOS design because of the benefits of
system-on-a-chip integration. Using a technique similar to my doctoral work with a 20GS/s serial link receiver, I
believe it is possible to achieve such a converter with at least one order magnitude less power and area than the
conventional techniques. Such a method would create precision clocks at the receiver front-end, and then use
clock down-conversion to move the flash A/D slicers downstream, as opposed to the conventional approach of
using time-interleaved front-end sampling. Calibration structures, like switch capacitor banks, would be essential
towards achieving optimal sampling edges and minimal voltage offset. Such work would have many implications
in improving performance towards higher sampling rates in A/D’s or high speed serial links(40GS/s, OC-768).

While my interests and expertise in high frequency mixed-signal circuit design are many, I am in general a
passionate learner, and always looking to apply circuit design and microfabrication into many interdisciplinary
areas. Besides my previous work on nonlinear communications systems, I have collaborated with Mechanical
Engineering(Professor Beth Pruitt) on an Agilent sponsored, electrically addressable, liquid release well array[10].
Through this work, I have witnessed firsthand the process variability involved with MEMs processing and the
possible application of circuit calibration. I have also helped a colleague(Sam Palermo) on the design of his thesis
chip, a 90nm CMOS 16Gb/s transceiver for parallel VCSEL optical interconnects. Through these interactions, I
recognize the importance of interdisciplinary collaboration, and feel that there are many fields that can experience
enormous benefits from the application of mixed-signal chip design and fabrication to their specific problems.
Publications and References

[1] Cormac Conroy, Samuel Sheng, Arnold Feldman, Greg Uehara, Albert Yeung, Chih-Jen Hung, Vivek
Subramanian, Patrick Chiang, Paul Lai, Xiaomin Si, Jerry Fan, David Flynn, Meiqing He. A CMOS Analog Front-
End IC for DMT ADSL. International Solid State Circuits Conference, San Francisco, February 1999, pp. 240-
241.

[2] Patrick Chiang, William J. Dally, Ming-Ju E. Lee. Monolithic Chaotic Communications System. 2001 IEEE
International Conference on Circuits and Systems, Sydney, Australia, May 6-9, 2001.

[3] Ming-Ju E. Lee, William Dally, Patrick Chiang. A 90mW 4Gb/s Equalized I/O Circuit with Input Offset
Cancellation. International Solid State Circuits Conference, San Francisco, February 2000, TP 15.3, pp. 252-253.

[4] Ming-Ju E. Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit
Techniques. IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599.

[5] Ming-Ju E. Lee, William J. Dally, John W. Poulton, Patrick Chiang, Stephen F. Greenwood. An 84-mW 4Gb/s
Clock and Data Recovery Circuit for Serial Link Applications. VLSI Circuits Symposium, Kyoto, Japan, June
2001, pp. 149-152.

[6] Patrick Chiang, William J. Dally, Ming-Ju E. Lee. A 20Gb/s 0.13um CMOS Serial Link 2002 Hotchips 2002,
Stanford, CA, Aug. 18-20, 2002.

[7] Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark
Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output
Multiplexer. 2004 Symposium on VLSI Circuits, June 15-19, 2004, pp. 272-275.

[8] Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark
Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output
Multiplexer. IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, April 2005, pp. 1004-1011.

[9] Patrick Chiang. Doctoral Dissertation. 2005.

[10] T. Lamers, P. Chiang, R. Flynn, Y.R. Rau, K. Ioakeimidi, S. Devasenathipathy, B. Chui, B.L. Pruitt. An
Electrically Addressable, Liquid Release Well Array for a Hand-held Scented Material Dispense System. In
preparation for Hilton Head Workshop, 2006.