Principles and Applications of

Electrical Engineering 14.1 Latches and Flip-Flops

Sixth Edition
• Flip-flop
Chapter 14 – Elementary sequential logic gate
– Remains in one of two stable states until
conditions cause it to change state
Digital Systems – Has two outputs
• One is the complement of the other
• Common to depict flip-flops by their block
diagram
– Output given a name, such as Q
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RS Flip-Flop RS Flip-Flop Rules

• Two inputs: S and R • Rules that govern flip-flop state

ഥ
• Two outputs: Q and Q – When R = S = 0, state remains unchanged
from present state
– When S = 1 and R = 0, output is set such that
Q=1
– When S = 0 and R = 1, output is reset such
that Q = 0
– R and S are not permitted to be 1
simultaneously

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 Timing Diagram RS Flip-Flop (cont’d.)

• Describes transitions in flip-flop output due • RS flip-flop is level sensitive

to changes in the inputs – Set and reset operations are completed only
after the R and S inputs have reached the
appropriate levels
– Transitions in Q output occur with a small
delay
• RS flip-flop can be constructed in different
ways
– Two examples shown on next slide

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RS Flip-Flop (cont’d.) Additional Features of the RS Flip-Flop

• Preset, P
• Clear, C

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 Data Latch (Delay) D Flip-Flop

• Q is latched when E is set low and • Extension of the data latch

unlatched when E is set high • Utilizes two RS flip-flops
– Delays the impact of D on Q until the next • Clock signal drives the enable inputs
time E is set high
• Changes state only on a positive clock
transition (low to high)
– Positive-edge (leading-edge) triggered

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JK Flip-Flop

• Negative (trailing-edge) triggered

– Indicated by bubble at the clock input

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 JK Flip-Flop Rules JK Flip-Flop (cont’d.)

• If J and K are both low: • Known as universal flip-flop

– No change occurs in the state of the flip-flop – Can be configured to behave as RS or D
• If J = 0 and K = 1, the flip-flop is reset to 0
• If J = 1 and K = 0, the flip-flop is set to 1
• If both J and K are high:
– The flip-flop toggles between states at every
negative transition of the clock input, denoted
by the symbol ↓

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14.2 Digital Counters and Registers 3-Bit Binary Up Counter

• Counter • 23 = 8 possible
– Sequential logic device states
– Takes one of N possible states • Reset input can
• Steps through the states sequentially force the counter
– Resets to zero after reaching the last state outputs low
• Decade counter
– Counts from zero to nine and then resets
– Can be cascaded to represent any series of
decimal digits
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 3-Bit Binary Ripple Counter Divide-By-8 Circuit

• Ripple counter shown can be used to

make a divide-by-8 counter
– Result: one output pulse for every 8 clock
pulses

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Synchronous Counter Other Counters

• Input clock drives all the flip-flops • Ring counter

simultaneously • Up-down counter
– Additional select input determines whether the
counter counts up or down

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 Parallel-Input Parallel-Output Register
Registers
(cont’d.)
• Cascade of flip-flops each storing one bit • Load input pulse causes the parallel inputs
of binary data b0b1b2b3 to be transferred to the respective
• Parallel input-parallel output register flip-flops
– Load input pulse acts on all clocks • Binary word b3b2b1b0 is stored
simultaneously – Each bit represented by flip-flop state
• Register preserves stored word until new
load input appears

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Shift Register 14.3 Sequential Logic Design

• Can accommodate a binary word that • Design of sequential circuits uses a

arrives serially (one bit at a time) systematic procedure
• Provides both serial and parallel outputs – Tools: state diagram and state transition table
• Describe logic states and their interrelationships
• State diagram
– Graphical representation of sequence of
states (outputs)

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 State Diagram Example State Transition Table Example

• Each state denoted by a circle (node) • Current state represented by q

• Transitions indicated by arrow (directed – Next state represented by Q
edge)

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Truth Table and Excitation Table for an RS

Design Process
Flip-Flop
• State transition table or state diagram
communicates design requirements
• No single, unique implementation for a set
of output specifications
• Select a flip-flop and use its truth table to
define its excitation table

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 Example: Design of a Modulo-4 Binary Up- Example: Design of a Modulo-4 Binary Up-
Down Counter Down Counter (cont’d.)
• Specification given in the state diagram • Choose two RS flip-flops
shown • Create the state transition table shown
– Counter output limited to integers 0 to 3 – First five columns match information in state
– Counter can increment or decrement diagram

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Example: Design of a Modulo-4 Binary Up-

Programmable Logic Controllers (PLCs)
Down Counter (cont’d.)
• Find the RS input pair (S1,R1) and (S2,R2) • Specialized computers
that will produce the desired relationship – Very effective at executing series of complex
– Match the values of each output pair (Qt,Qt+1) logical decisions
found in the RS flip-flop excitation table to • Used in industrial applications to
each of the two pairs of counter outputs implement logic functions
(q1,Q1) and (q2,Q2)
– Example industries: machining, packaging,
– d represents don’t-care condition material handling, and automated assembly
• Use combinational logic tools (Karnaugh
maps) to determine the logic circuit

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 14.4 Computer System Architecture Computer System Architecture (cont’d.)

• Central processing unit (CPU) • General types of memory

– Receives data over the CPU bus – Volatile
• Examples: SRAM and DRAM
– Non-volatile
• Examples: EEPROM and Flash memory
• Clock
– Typically implemented by a crystal oscillator

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Computer System Architecture (cont’d.) 14.5 The ATmega328P Microcontroller

• Computer programs • Reduced instruction set computing (RISC)

– Programming done in high-level language microcontroller used in automobiles and
• Translated into machine language by a compiler the Arduino Uno prototyping platform
• CPU registers • External pins
– Retrieve data and store results of – Two 8-bit and one 7-bit bi-directional I/O ports
computations – Analog voltage reference
• Interrupts – Reset
– Allow the CPU to interrupt its normal flow of – Connections for ground and power supplies
operations to respond to an external event
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 The ATmega328P Microcontroller (cont’d.) 14.6 The ArduinoTM Project

• Ports designed to provide specialized • Open-source prototyping hardware and

functions software resources
– A/D conversion – Audience: casual users and professionals
– Pulse-width modulation – Hides many complex details of working with a
– Timer/counters microprocessor
– Communication interface – Built-in USB interface and serial output
• Provides low-power modes to conserve – Does not require firmware be burned onto the
chip
battery life
• Large library of high-level functions
available
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