Quad SPI Flash:
Benefits and Uses
in General Purpose
Microcontrollers
NXP Semiconductors
BL Microcontrollers
San Jose CA
October 2010
LPC4300: SPI Flash Interface
MPU GPDMA Audio PLL Flash
Up to 1 MB
Dual Bank
ARM
ARM CORTEX-M4 NVIC
Brownout
Up to 150MHz Detector
USB PLL CORTEX-M0
Up to 150MHz
SRAM
Power-On Up to 264 KB
WIC Reset
CPU PLL
Debug Watchdog ROM
Floating Point Unit IRC IPC NVIC
Trace Timer ROM/OTP
CORE SYSTEM MEMORY SUBSYSTEM
BUS SYSTEM
2 x HS SPI Flash Motor Ctrl State Config
4 x UART Serial GPIO
USB 2.0 Interface PWM Timer
CONFIGURABLE INTERFACES
Ethernet External 4 x 32 bit
3 x SSP/SPI
MAC Mem Ctrl Timers
OTP Key AES
Storage Decryption
LCD
SD/MMC 2 x I 2C RTC
Controller SECURITY
Quad Enc 2 x 8 Ch 10-Bit
CAN 2.0B 2 x I 2S Alarm Timer
Interface 10-Bit ADC DAC
INTERFACES TIMERS ANALOG
2
SPIFI – Overview
SPI Flash Interface
Serial Internal
Flash
SPIFI Memory
Cortex-M4
Memory Up to
40MB/s
LPCMicrocontroller
Unique NXP feature that maps low-cost serial flash
memories into the internal memory system.
3
SPIFI – Quad SPI Flash Interface
What is Quad SPI?
− A couple of years ago, PCs started using Quad-SPI Flash for loading
BIOS. The high PC volumes forced prices down to low levels
− Advantages: High speeds, small packages/few pins, low cost
− Disadvantages: Not supported by standard MCUs – UNTIL NOW!
/CS VCC
Serial
DO(IO1) /HOLD(IO3)
Flash
WP(IO2) CLK
Memory
GND DI (IO0)
SPI Flash Interface uses either 4 or 6 lines
− Standard SPI flash uses CLK, CS, MISO and MOSI
− Quad SPI flash uses CLK, CS IO0, IO1, IO2 and IO3 4
External Flash Performance
Comparison
Traditional View
SPIFI View
Full serial flash memory
Serial is visible to the CPU.
Flash CPU can read any
location randomly.
Bus Matrix
8
Pin Level Interface
Most of the 157 serial flashes noted above are SPI-only:
CS
SCK
MOSI
MISO
Read Status (opcode 05), input data 02, SPI mode
Most Basic SPI Read command:
CS
SCK
MOSI
MISO
opcode 24-bit address data
Read Command (opcode 0x03), SPI mode, first byte read = 0x38
9
Pin Level Interface 3
Next faster mode is for slave to send read data in dual format
opcode 24-bit address dummy byte data
slave drives
Fast Read Dual Out command (opcode 0x3B), first byte read = 0x38 IO3:0
Next faster mode: master sends the address & mode in dual format
mode
opcode 24-bit address byte data
slave drives
IO3:0
10
Pin Level Interface 2
Note that Read command requires the serial flash to provide data
in the clock period after it samples the last bit of the address.
This is a difficult requirement, and constrains the serial clock rate
at which the Read command can be used.
− Most devices limit Read to 20–50 MHz.
Fast Read command adds dummy byte between address and data.
− Allows time for device to get its data pipeline filled and ready.
− Can be used up to max serial clock frequency of device
(50–133 MHz).
CS
SCK
MOSI
MISO
opcode 24-bit address dummy byte data
Fast Read command (opcode 0x0B), SPI mode, first byte read = 0x31 11
Pin Level Interface 4
Quad mode adds signals IO3:2; here slave sends data in quad format
opcode 24-bit address Dummy byte data
slave drives
Fast Read Quad Out Command (opcode 0x6B), first byte read = 0x87 IO3:0
Here master sends
the address, mode,
2 dummy bytes in
quad format
opcode 24-bit addr mode
byte
dummy
byte
dummy
byte data
slave drives IO3:0
12
Fast Read Quad Out Command (opcode 0xEB), first byte read = 0x38
Mode Byte and No Opcode Mode
If the mode byte in the Read Dual/Quad I/O command is 0xA5, most
serial flashes will not expect the next command to have an opcode.
mode
opcode 24-bit addr byte 24-bit addr
Fast Read Quad I/O command (opcode 0xEB), mode byte 0xAF sets No Opcode mode for next command
Next mode byte(s) can be 0xA5, or 0xFF to end No Opcode mode.
Driver automatically uses no-opcode mode for devices that can do it.
“No opcode mode” is our term, flash vendors use “continuous read
mode”, “XIP mode” 13
ROM-based Drivers
Boot from Quad SPI Flash using SPIFI
− Faster than single lane serial flash
− Boot source selected by pin or NV location
Initialization API
− Checks what kind of device
− Writes to control registers for optimal read performance
Write API
− Block writes
− Erase
− Write protection.
14
SPIFI – Supported Devices
All NXP’s devices with the unique
SPI Flash Interface (SPIFI) support
all major suppliers of QSPI flash
15
Supported / Unsupported Devices
Three requirements for serial flash include most existing devices:
− Read JEDEC ID command
− Page programming command (byte programming not supported)
− At least one erase command that is uniform across the whole device
Most (all?) of the 17 unsupported devices lack page
programming:
− Elite F25L004, F25L008, F25L016
− Eon 25B64
− SST 25[VW]F512, 25[VW]F010, 25[LVW]F020, 25[VW]F040,
25[VW]F080, 25VF016, 25VF032.
157 serial flash devices from 11 vendors meet these
requirements.
95 have been successfully tested with the SPIFI driver API.
Most of the untested 62 are old, small, more or less obsolete. 16
Thank You
Santa Clara, CA
August 2011 17
