ARM

Advanced RISC Machines

 Features
• 32-bit microcontroller
• 32 bit data bus and 32 bit ALU
• 32 bit address bus
• RISC processor
• All instructions are 32-bit long ( data bus = 32bit ➔ time
to fetch is 1 cycle for all instructions)
*Except Thumb instructions
• All instructions perform 32-bit operations ( ALU=32bit
➔ execution time for all data processing instruction will
be 1 cycle)
• 37 registers, all 32 bits (16 available at a time)
• 7 different operating modes that can be entered invoked by various
interrupts/exceptions
• It has a “Load-Store” instruction set, typical of RISC processors This
means data from memory can only be taken (Load) into a register or stored
back (Store) into memory. All data processing will only happen on registers
on not directly on memory operands. This drastically reduces the number
of instructions needed in the instructions set (RISC).
• 3 stage pipelining
• 3 data formats (8, 16, 32 bits)
• Von Neumann model as well as Harvard Architecture
 ARM Registers Data Size

• 8bits - byte (universal)

• 16bits - half word
• 32its - word
CPSR (Current Program Status Register)

• V: Overflow Flag  Z: Zero Flag

V = 1 means signed overflow occurred Z = 1 means result is zero.
V = 0 means signed overflow hasn’t occurred
Z = 0 means result is non-zero

• C: Carry Flag  N: Negative Flag

C = 1 means carry after MSB If N = 1, result is negative
C = 0 means no carry after MSB If N = 0, result is positive.

• Extension- bits 8-15 ( Reserved for future use)

• Status- bits 16-23 (Reserved for future use)
• T: Thumb State
If T = 1, then processor is in Thumb state
If T = 0, then processor is in normal ARM7 state.
• F: Fast interrupt Mask
If F = 1, then Fast Interrupts are disabled (masked).
If F = 0, then Fast Interrupts are enabled (un-masked).
• I: Interrupt Request Mask
If I = 1, then normal Interrupts are disabled (masked).
If I = 0, then normal Interrupts are enabled (un-masked).
• Mode Bits
ARM7 can operate in 7 different operating modes.
These bits indicate the current operating mode of the
processor.
 Processor modes
• The ARM has seven basic operating modes:
1.User (USR): unprivileged mode under which most tasks run
2.Fast Interrupt request (FIQ) : entered when a high priority
(fast) interrupt is raised
3.Interrupt Request (IRQ): entered when a low priority
(normal) interrupt is raised
4.Supervisor (SVC): entered on reset and when a Software
Interrupt instruction is executed
5.Abort (ABT) : used to handle memory access violations
6.Undefined (UND): used to handle undefined instructions
7.System (SYS) : privileged mode using the same registers as
user mode
 Current Visible Registers
r0
User Mode r1
r2
r3 Banked out Registers
r4
r5
r6 FIQ IRQ SVC Undef Abort
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr
 Current Visible Registers
r0
IRQ Mode r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ SVC Undef Abort
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr
 Current Visible Registers
r0
FIQ Mode r1
r2
r3 Banked out Registers
r4
r5
r6 User IRQ SVC Undef Abort
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr
 Current Visible Registers
r0
SVC Mode
r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ Undef Abort
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr
 Current Visible Registers
r0
Abort Mode
r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr
Basic instructions

 MOV Rn, Op2

Load Rn with register with Op2 (operand2)
*immediate value can only be 8bit (00-FF or 0 to 255)
 MOV R5, R7
 MOV R2, #25
# is put before an immediate value.
 MOV R1, #0x87
0x for indicating hexadecimal
 ADD Rd, Rn, Op2
Add Op2 to Rn and store the result in Rd
Op2 can be a register or immediate value

MOV R1, #0x25

MOV R7, #0x35
ADD R5, R1, R7

MOV R1, #0x25

ADD R5, R1, #0x34

 SUB Rd, Rn, Op2 ➔ Rd = Rn – Op2

 Load store instructions

LDR Rd, [Rx]

Load Rd with the contents of location pointed to by Rx register.
 STR Rx, [Rd]
Store RX into locations pointed to by Rd
Signed numbers

 LDRSH
 LDRSB

Figure 5-1: Sign Extending a Byte

Figure 5- 2: Sign Extending a Half-word

Directives

 AREA section_name, attribute, attribute,……..

 AREA MY_PRG, CODE, READONLY

 AREA MY_VARIABLES, DATA, READWRITE
 AREA MY_CONSTANTS, DATA, READONLY
example

To Add Some Data and Store the SUM in R3.

AREA ADDITION, CODE, READONLY

Entry
MOV R1, #0x25 ;R1 = 0x25
MOV R2, #0x34 ;R2 = 0x34
ADD R3, R2,R1 ;R3 = R2 + R1

HERE B HERE ;stay here forever

END
 EQU (EQUATE) - used to define constant

VAR1 EQU 0x39

VAR2 EQU 2_00110101 (35 in hex)
VAR3 EQU 39 (27 in hex)
VAR4 EQU ‘2’
example

SUM EQU 0x40000120

MOV R2, #5
MOV R1, #2
ADD R2, R2, R1
LDR R3, =SUM
STRB R2, [R3]
Program Using RN Directive : Add Some Data and store the SUM in R3.

VAL1 RN R1
VAL2 RN R2
SUM RN R3

AREA PROG_2_2, CODE, READONLY

MOV VAL1, #0x25

MOV VAL2, #0x34
ADD SUM, VAL1, VAL2
HERE B HERE
END
Prg for storing data in program memory.

AREA LOOKUP_EXAMPLE, READONLY, CODE

LDR R2, =OUR_FIXED_DATA ;point to OUR_FIXED_DATA

LDRB R0, [R2]
ADD R1, R1, R0
HERE B HERE
Define Constant
OUR_FIXED_DATA DCB BYTE
DCB 0x55,0x33,1,2,3,4,5,6
DCW HALF WORD
DCD 0x23222120,0x30
DCD WORD
DCW 0x4540,0x50
END

Note: load address to register : ADR R2, OUR_FIXED_DATA ;point to OUR_FIXED_DATA ---------- (Pseudo Instruction)
DCB 0x55,0x33,1,2,3,4,5,6
DCD 0x23222120,0x30
DCW0x4540,0x50
 Space directive: allocates memory without initial value

 Following slide gives example

 ;R1 = A
AREA OUR_DATA, DATA, READWRITE
; Allocates the followings in SRAM memory LDR R0,=A
A SPACE 4
LDR R1,[R0]
B SPACE 4
C SPACE 4
END

;R2 = B
AREA OUR_PROG,CODE,READONLY
LDR R0,=B
;A = 5
LDR R2,[R0]
LDR R0,=A ;R0 = Addr. of A
MOV R1,#5
;C = R1 + R2 , (C = A + B)
STR R1,[R0]
ADD R3,R1,R2
LDR R0,=C
;B = 4
STR R3,[R0]
LDR R0,=B
loop B loop
MOV R1,#4
STR R1,[R0] ;
Align directive

 Used to make sure data is aligned on the 32bit word or 16 bit half
word address boundary.

The following uses to make the data 32 bit word aligned:

ALIGN 4 ; the next instruction is word (4bytes) aligned

…….
ALIGN 2 ; ; the next instruction is half-word (2bytes) aligned
…..
NO ALIGN
ALIGN 2
ALIGN 4
Arithmetic Instructions and Flag Bits for Unsigned Data
LDR R0,=0xF62562FA ;R0 = 0xF62562FA
LDR R1,=0xF412963B ;R1 = 0xF412963B
MOV R2,#0x35 ;R2 = 0x35
MOV R3,#0x21 ;R3 = 0x21
ADDS R5,R1,R0 ;R5 = 0xF62562FA + 0xF412963B
;now C = 1
ADC R6,R2,R3 ;R6 = R2 + R3 + C
; = 0x35 + 21 + 1 = 0x57
LDR R0,=0xF62562FA ;R0 = 0xF62562FA
LDR R1,=0xF412963B ;R1 = 0xF412963B
MOV R2,#0x21 ;R2 = 0x21
MOV R3,#0x35 ;R3 = 0x35
SUBS R5,R1,R0 ;R5 = R1-R0
=0xF412963B - 0xF62562FA
;now C = 1
SBC R6,R2,R3 ;R6 = R3-R2-1+C
; = 0x35 -0x21-1+0 = 0x13
 No increment or decrement instructions in ARM instead ADD or SUB are used.
ADD R4, R4, #1
SUB R4, R4, #1

 RSB – reverse subtract

RSB R5, R1, #0 ------ R5 = 0-R1

 2’Complement of a 64bit number

LDR R0, =0xF62562FA ; R0= 0xF62562FA (LOWER 32 BITS)
LDR R1, =0xF812963B ; R1= 0xF812963B
RSB R5, R0, #0 ; R5= 0-R0
RSC R6, R1, #0 ; R6= 0-R1-1+C
 Multiplication division circuits are complex so all processors does not
have this facility

 All arm processor have multiplications but not all have division

 Cortex M3 and cortex M4 has both

LDR R1, =100000 ; R0= 100000
LDR R2, =150000 ; R1=150000
MULL R3, R2, R1 ; R3 = R2 X R1
; BUT R3 is not 15000000000 because it is more than 32 bits
 UMULL R3, R4, R2, R1
R2 x R1
R3 = LOWER 32 BITS
R4 = HIGHER 32 BITS
 MLA Rd, Rm, Rs, Rn ; Rd = Rm x Rs + Rn

 UMLAL RdLo, RdHi, Rn, Op2 ; RdHi:RdLo = Rn x Op2 + RdHi:RdLo

Eg. UMLAL R4, R3, R2, R1

 SMULL – SIGNED MULTIPLY LONG

Signed Multiplication (SMULL RdLo, RdHi, Rm, Rs) Summary

 Logic Instructions and Flag Bits

 BIC Rd, Rn, Op2 ; clear certain bits of Rn specified by the Op2 and
place the result in Rd

 MVN Rd, Rn ; move 1’s complement of Rn to Rd

Logic Shift operations for unsigned numbers in ARM

Rotate operations for unsigned numbers in ARM

Flag Settings for Compare (CMP Rn, Op2) of Unsigned Data
 CMP FOR SIGNED

 OP2>RN V=N
 OP2=RN Z=1
 OP2<RN V != N