Narasinga Rao Miniskar, Ph.D.
Mobile: +1+865-232-9954
Email: [email protected]
Summary:
Strong exploration skills combined with technical expertise helps me to understand the
challenges in HPC and embedded systems and adapt to the environment to make significant
contributions in the these domains.
Work Experience:
Research Software Engineer (ORNL) from July 2019. Research work includes RISC-V architecture
exploration, hardware scheduling algorithms, and applying Machine Learning approaches for
system architecture problems such as design space exploration, scheduling, IRIS run-time
framework.
Associate Architect at Samsung R&D Institute India Bangalore (SRIB) from Nov-2011 to July
2019. Research work includes compiler for deep learning architectures, inference framework
and models to enable AI for mobile devices, and also DNN accelerator platform cycle
accurate simulators. Past experience on reconfigurable processor (CGRA) architectures and
development tool chain such as compiler, cycle accurate simulators, and profilers.
Developed an industry best high performance, low memory and light weight DNN fixed point
framework for ARM Big.Little architectures.
Research Scholar at IMEC R&D, Belgium from Oct-2006 to Oct-2011. Proposed a system
scenario based methodology for energy efficient multiprocessor resource management for
embedded systems.
Senior Software Engineer at Agere Systems India Pvt. Ltd, Bangalore from July-2002 to Oct-
2006. Worked on the customizable software traffic generator for wide range of Agere
network processors.
EDUCATION:
Doctor in Engineering (Ph.D.) from IMEC & K.U.Leuven on Dec-2012 (Oct 2006 – Oct 2011)
Master of Technology (M.Tech) in Computer Science & Engineering
Indian Institute of Technology Delhi, India. (July 2002 – May 2004) CGPA: 8.32
Bachelor of Technology (B.Tech.) in Computer Science & Engineering
J.N.T.University, Hyderabad, A.P., India. (Sep 1998 – May 2002) Score: 82.11%
Diploma in Computer Science & Engineering
Govt S.V.Polytechnic College, Tirupati, A.P., India. (Sep 1995 – May 1998) Score: 79.45%
PATENTS:
[Patent] Method and apparatus for determining memory requirement in a network,
US20200257972A1
[Provisional Patent by ORNL] Memory Efficient Lock-Free Circular Queue - Split Indexing with
Odd-Even Increment
PUBLICATIONS:
Article: Deffe: a data-efficient framework for performance characterization in domain-specific
computing. Frank Liu, Narasinga Rao Miniskar, Dwaipayan Chakraborty, and Jeffrey S.
Vetter. 2020. In Proceedings of the 17th ACM International Conference on Computing
Frontiers (CF ’20). Association for Computing Machinery, New York, NY, USA, 182–191. doi:
https://doi.org/10.1145/3387902.3392633
Patent: Method and apparatus for determining memory requirement in a network,
US20200257972A1. doi: https://patents.google.com/patent/US20200257972A1/en
Article: Light Weight and Fast Simulation Methodology in SystemC for TLM based Behavior
Modeling of Programmable Processors. Shashidhar SK, Miniskar NR, Batchu SK, Kim K. In
2019 IEEE International Conference on Electronics, Computing and Communication
Technologies (CONECCT) 2019 Jul 26 (pp. 1-7). IEEE. doi:
https://doi.org/10.1109/CONECCT47791.2019.9012935
Article: Low Complex & High Accuracy Computation Approximations to Enable On-Device
RNN Applications. Pasupuleti SK, Gadde RN, Rajagopal V, Vishnoi A, Sekhar NC, Kumar
RC, Miniskar NR. In 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
2019 May 26 (pp. 1-5). IEEE. doi:https://doi.org/10.1109/ISCAS.2019.8702528
Article: Optimal SDRAM buffer allocator for efficient reuse of layer IO in CNNs inference
framework. Miniskar NR, Pasupuleti SK, Rajagopal V, Vishnoi A, Ramasamy CK, Gadde RN.
In 2018 IEEE International Symposium on Circuits and Systems (ISCAS) 2018 May 27 (pp.
1-5). IEEE. doi: https://doi.org/10.1109/ISCAS.2018.8351294
Article: An Intelligent Bandwidth Manager for CNN Applications on Embedded Devices.
Pasupuleti SK, Rajaram A, Miniskar NR, Gadde RN, Yadvandu D, Rajagopal V, Vishnoi A,
Ramasamy CK. In 2018 25th IEEE International Conference on Image Processing (ICIP)
2018 Oct 7 (pp. 4173-4177). IEEE. doi: https://doi.org/10.1109/ICIP.2018.8451706
Article: Accurate and efficient fixed point inference for deep neural networks. Rajagopal V,
Ramasamy CK, Vishnoi A, Gadde RN, Miniskar NR, Pasupuleti SK. In 2018 25th IEEE
International Conference on Image Processing (ICIP) 2018 Oct 7 (pp. 1847-1851). IEEE. doi:
https://doi.org/10.1109/ICIP.2018.8451268
Article: Fast cycle-accurate compile based simulator for reconfigurable processor. Miniskar
NR, Gadde RN, Cho YC, Kim S. In 2017 IEEE International Symposium on Circuits and
Systems (ISCAS) 2017 May 28 (pp. 1-4). IEEE. doi:
https://doi.org/10.1109/ISCAS.2017.8050318
Article: A novel method to regenerate an optimal CNN by exploiting redundancy patterns in
the network. Pasupuleti SK, Miniskar NR, Rajagopal V, Gadde RN. In 2017 IEEE
International Conference on Image Processing (ICIP) 2017 Sep 17 (pp. 4407-4411). IEEE.
doi: https://doi.org/10.1109/ICIP.2017.8297115
Article: Intra mode power saving methodology for cgra-based reconfigurable processor
architectures. Miniskar NR, Patil RR, Gadde RN, Cho YC, Kim S, Lee SH. In 2016 IEEE
International Symposium on Circuits and Systems (ISCAS) 2016 May 22 (pp. 714-717).
IEEE. doi: https://doi.org/10.1109/ISCAS.2016.7527340
Article: Retargetable automatic generation of compound instructions for CGRA based
reconfigurable processor applications. Miniskar NR, Kohli S, Park H, Yoo D. In Proceedings
of the 2014 International Conference on Compilers, Architecture and Synthesis for
Embedded Systems 2014 Oct 12 (p. 4). ACM. (pp. 1-9). doi:
https://doi.org/10.1145/2656106.2656125
Article: Function inlining and loop unrolling for loop acceleration in reconfigurable processors.
Miniskar NR, Gode PS, Kohli S, Yoo D. In Proceedings of the 2012 international conference
on Compilers, architectures and synthesis for embedded systems 2012 Oct 7 (pp. 101-110).
ACM. doi: https://doi.org/10.1145/2380403.2380426
Article: Memory and communication driven spatio-temporal scheduling on MPSoCs. Bhatti
ZW, Miniskar NR, Preuveneers D, Wuyts R, Berbers Y, Catthoor F. In 2012 25th Symposium
on Integrated Circuits and Systems Design (SBCCI) 2012 (pp. 1-6). IEEE. doi:
https://doi.org/10.1109/SBCCI.2012.6344423
Article: SAMOSA: Scratchpad aware mapping of streaming applications. Bhatti ZW,
Preuveneers D, Berbers Y, Miniskar NR, Wuyts R. In 2011 International Symposium on
System on Chip (SoC) 2011 (pp. 48-55). IEEE. doi:
https://doi.org/10.1109/ISSOC.2011.6089687
Article: PinComm: Characterizing intra-application communication for the many-core era.
Heirman W, Stroobandt D, Miniskar NR, Wuyts R, Catthoor F. In 2010 IEEE 16th
International Conference on Parallel and Distributed Systems 2010 Dec 8 (pp. 500-507).
IEEE. doi: https://doi.org/10.1109/ICPADS.2010.56
Article: Scenario based mapping of dynamic applications on mpsoc: A 3d graphics case
study. Miniskar NR, Hammari E, Munaga S, Mamagkakis S, Kjeldsberg PG, Catthoor F. In
International Workshop on Embedded Computer Systems 2009 Jul 20 (pp. 48-57). Springer,
Berlin, Heidelberg. doi: https://doi.org/10.1007/978-3-642-03138-0_6
HONORS:
Two times winner of worldwide Samsung Best Paper Bronze award in (SBPA-2013, 2017)
All India 72nd rank in CS stream of Graduate Aptitude Test of Engineering (GATE-2002), an
entrance test for engineering post-graduation in Indian universities
Second prize in IEEE-2002 annual technical symposium and software contest, IIT-Roorkee
REFERENCES:
Dr. Jeffrey Vetter, Dr. Frank Liu,
Section Head, Group Leader,
Advanced Computing Systems Research, Architectures and Performance Group,
Oak Ridge National Laboratory, Oak Ridge National Laboratory,
Oak Ridge, 37830, USA Oak Ridge, 37830, USA
[email protected] [email protected]
Prof. Francky Catthoor, Dr. Balvinder Singh, Ph.D.
Professor at KU.Leuven Senior Director,
IMEC R&D, Leuven-3001, Belgium Head of Visual Intelligence Group,
[email protected] Samsung R&D Institute India Bangalore, India
[email protected]
