Machine Model CSTATT
Static Condenser (STATCON) Model CSTATT
𝐿𝐿𝐿𝐿𝐿 𝑀𝑀𝑀 = 𝑉𝑇 + 𝑋𝑇 𝐼𝐶𝐶𝐶𝐶0
States:
1 – Regulator 1 where
2 – Regulator 2 𝑖𝑖 (𝑉𝑇 ≥ 𝑉𝑐𝑐𝑐𝑐𝑐𝑐 ) 𝑡ℎ𝑒𝑒 𝐼𝐶𝐶𝐶𝐶0 = 𝐼𝐶𝐶𝐶𝐶
3 – Thyristor 𝐼𝐶𝐶𝐶𝐶 𝑉𝑇
𝑒𝑒𝑒𝑒 𝐼𝐶𝐶𝐶𝐶0 =
𝑉𝑐𝑐𝑐𝑐𝑐𝑐
Also, 𝐿𝐿𝐿𝐿𝐿 𝑀𝑀𝑀 ≤ 𝐸𝑙𝑙𝑙𝑙𝑙
Other Signals
VOTHSG 𝑉𝑚𝑚𝑚 𝐿𝐿𝐿𝐿𝐿 𝑀𝑀𝑀 𝐸𝑇
− −
− (1 + 𝑠𝑇1 )(1 + 𝑠𝑇2 ) 𝐾 + 1 𝑀𝑀𝑀𝑀𝑀
|𝑉| ∑ ∑ 𝐼𝑆𝑆
− (1 + 𝑠𝑇3 )(1 + 𝑠𝑇4 ) 𝑠 𝑋𝑡 𝑆𝑆𝑆𝑆𝑆
+ 3
1 2
𝑉𝑅𝑅𝑅 𝑉𝑚𝑚𝑚 𝐿𝐿𝐿𝐿𝐿 𝑀𝑀𝑀
𝐷𝐷𝐷𝐷𝐷
𝐿𝐿𝐿𝐿𝐿 𝑀𝑀𝑀 = 𝑉𝑇 − 𝑋𝑇 𝐼𝐿𝐿𝐿𝐿0
V is on the high-side of the generator step-up if integrated where
transformer step-up is included.
𝑖𝑖 (𝑉𝑇 ≥ 𝑉𝑐𝑐𝑐𝑐𝑐𝑐 ) 𝑡ℎ𝑒𝑒 𝐼𝐿𝐿𝐿𝐿0 = 𝐼𝐿𝐿𝐿𝐿
𝐼𝐿𝐿𝐿𝐿 𝑉𝑇
𝑒𝑒𝑒𝑒 𝐼𝐿𝐿𝐿𝐿0 =
𝑉𝑐𝑐𝑐𝑐𝑐𝑐
Model supported by PSSE