Intel Assembler 80186 and higher CodeTable 1/2
TRANSFER Flags
Name Comment Code Operation O D I T S Z A P C
MOV Move (copy) MOV Dest,Source Dest:=Source
XCHG Exchange XCHG Op1,Op2 Op1:=Op2 , Op2:=Op1
STC Set Carry STC CF:=1 1
CLC Clear Carry CLC CF:=0 0
CMC Complement Carry CMC CF:= ¬ CF ±
STD Set Direction STD DF:=1 (string op's downwards) 1
CLD Clear Direction CLD DF:=0 (string op's upwards) 0
STI Set Interrupt STI IF:=1 1
CLI Clear Interrupt CLI IF:=0 0
PUSH Push onto stack PUSH Source DEC SP, [SP]:=Source
PUSHF Push flags PUSHF O, D, I, T, S, Z, A, P, C 286+: also NT, IOPL
PUSHA Push all general registers PUSHA AX, CX, DX, BX, SP, BP, SI, DI
POP Pop from stack POP Dest Dest:=[SP], INC SP
POPF Pop flags POPF O, D, I, T, S, Z, A, P, C 286+: also NT, IOPL ± ± ± ± ± ± ± ± ±
POPA Pop all general registers POPA DI, SI, BP, SP, BX, DX, CX, AX
CBW Convert byte to word CBW AX:=AL (signed)
CWD Convert word to double CWD DX:AX:=AX (signed) ± ± ± ± ± ±
CWDE Conv word extended double CWDE 386 EAX:=AX (signed)
IN i Input IN Dest, Port AL/AX/EAX := byte/word/double of specified port
OUT i Output OUT Port, Source Byte/word/double of specified port := AL/AX/EAX
i for more information see instruction specifications Flags: ±=affected by this instruction ?=undefined after this instruction
ARITHMETIC Flags
Name Comment Code Operation O D I T S Z A P C
ADD Add ADD Dest,Source Dest:=Dest+Source ± ± ± ± ± ±
ADC Add with Carry ADC Dest,Source Dest:=Dest+Source+CF ± ± ± ± ± ±
SUB Subtract SUB Dest,Source Dest:=Dest-Source ± ± ± ± ± ±
SBB Subtract with borrow SBB Dest,Source Dest:=Dest-(Source+CF) ± ± ± ± ± ±
DIV Divide (unsigned) DIV Op Op=byte: AL:=AX / Op AH:=Rest ? ? ? ? ? ?
DIV Divide (unsigned) DIV Op Op=word: AX:=DX:AX / Op DX:=Rest ? ? ? ? ? ?
DIV 386 Divide (unsigned) DIV Op Op=doublew.: EAX:=EDX:EAX / Op EDX:=Rest ? ? ? ? ? ?
IDIV Signed Integer Divide IDIV Op Op=byte: AL:=AX / Op AH:=Rest ? ? ? ? ? ?
IDIV Signed Integer Divide IDIV Op Op=word: AX:=DX:AX / Op DX:=Rest ? ? ? ? ? ?
IDIV 386 Signed Integer Divide IDIV Op Op=doublew.: EAX:=EDX:EAX / Op EDX:=Rest ? ? ? ? ? ?
MUL Multiply (unsigned) MUL Op Op=byte: AX:=AL*Op if AH=0 ♦ ± ? ? ? ? ±
MUL Multiply (unsigned) MUL Op Op=word: DX:AX:=AX*Op if DX=0 ♦ ± ? ? ? ? ±
MUL 386 Multiply (unsigned) MUL Op Op=double: EDX:EAX:=EAX*Op if EDX=0 ♦ ± ? ? ? ? ±
IMUL i Signed Integer Multiply IMUL Op Op=byte: AX:=AL*Op if AL sufficient ♦ ± ? ? ? ? ±
IMUL Signed Integer Multiply IMUL Op Op=word: DX:AX:=AX*Op if AX sufficient ♦ ± ? ? ? ? ±
IMUL 386 Signed Integer Multiply IMUL Op Op=double: EDX:EAX:=EAX*Op if EAX sufficient ♦ ± ? ? ? ? ±
INC Increment INC Op Op:=Op+1 (Carry not affected !) ± ± ± ± ±
DEC Decrement DEC Op Op:=Op-1 (Carry not affected !) ± ± ± ± ±
CMP Compare CMP Op1,Op2 Op1-Op2 ± ± ± ± ± ±
SAL Shift arithmetic left (≡ SHL) SAL Op,Quantity i ± ± ? ± ±
SAR Shift arithmetic right SAR Op,Quantity i ± ± ? ± ±
RCL Rotate left through Carry RCL Op,Quantity i ±
RCR Rotate right through Carry RCR Op,Quantity i ±
ROL Rotate left ROL Op,Quantity i ±
ROR Rotate right ROR Op,Quantity i ±
i for more information see instruction specifications ♦ then CF:=0, OF:=0 else CF:=1, OF:=1
LOGIC Flags
Name Comment Code Operation O D I T S Z A P C
NEG Negate (two-complement) NEG Op Op:=0-Op if Op=0 then CF:=0 else CF:=1 ± ± ± ± ± ±
NOT Invert each bit NOT Op Op:=¬ Op (invert each bit)
AND Logical and AND Dest,Source Dest:=Dest∧ Source 0 ± ± ? ± 0
OR Logical or OR Dest,Source Dest:=Dest∨Source 0 ± ± ? ± 0
XOR Logical exclusive or XOR Dest,Source Dest:=Dest (exor) Source 0 ± ± ? ± 0
SHL Shift logical left (≡ SAL) SHL Op,Quantity i ± ± ? ± ±
SHR Shift logical right SHR Op,Quantity i ± ± ? ± ±
Intel Assembler 80186 and higher CodeTable 2/2
MISC Flags
Name Comment Code Operation O D I T S Z A P C
NOP No operation NOP No operation
LEA Load effective address LEA Dest,Source Dest := address of Source
INT Interrupt INT Nr interrupts current program, runs spec. int-program 0 0
JUMPS (flags remain unchanged)
Name Comment Code Operation Name Comment Code Operation
CALL Call subroutine CALL Proc RET Return from subroutine RET
JMP Jump JMP Dest
JE Jump if Equal JE Dest (≡ JZ) JNE Jump if not Equal JNE Dest (≡ JNZ)
JZ Jump if Zero JZ Dest (≡ JE) JNZ Jump if not Zero JNZ Dest (≡ JNE)
JCXZ Jump if CX Zero JCXZ Dest JECXZ Jump if ECX Zero JECXZ Dest 386
JP Jump if Parity (Parity Even) JP Dest (≡ JPE) JNP Jump if no Parity (Parity Odd) JNP Dest (≡ JPO)
JPE Jump if Parity Even JPE Dest (≡ JP) JPO Jump if Parity Odd JPO Dest (≡ JNP)
JUMPS Unsigned (Cardinal) JUMPS Signed (Integer)
JA Jump if Above JA Dest (≡ JNBE) JG Jump if Greater JG Dest (≡ JNLE)
JAE Jump if Above or Equal JAE Dest (≡ JNB ≡ JNC) JGE Jump if Greater or Equal JGE Dest (≡ JNL)
JB Jump if Below JB Dest (≡ JNAE ≡ JC) JL Jump if Less JL Dest (≡ JNGE)
JBE Jump if Below or Equal JBE Dest (≡ JNA) JLE Jump if Less or Equal JLE Dest (≡ JNG)
JNA Jump if not Above JNA Dest (≡ JBE) JNG Jump if not Greater JNG Dest (≡ JLE)
JNAE Jump if not Above or Equal JNAE Dest (≡ JB ≡ JC) JNGE Jump if not Greater or Equal JNGE Dest (≡ JL)
JNB Jump if not Below JNB Dest (≡ JAE ≡ JNC) JNL Jump if not Less JNL Dest (≡ JGE)
JNBE Jump if not Below or Equal JNBE Dest (≡ JA) JNLE Jump if not Less or Equal JNLE Dest (≡ JG)
JC Jump if Carry JC Dest JO Jump if Overflow JO Dest
JNC Jump if no Carry JNC Dest JNO Jump if no Overflow JNO Dest
JS Jump if Sign (= negative) JS Dest
General Registers: JNS Jump if no Sign (= positive) JNS Dest
8086
Table 2. Instruction Set Summary
Mnemonic and
Instruction Code
Description
DATA TRANSFER
MOV e Move: 76543210 76543210 76543210 76543210
Register/Memory to/from Register 100010dw mod reg r/m
Immediate to Register/Memory 1100011w mod 0 0 0 r/m data data if w e 1
Immediate to Register 1 0 1 1 w reg data data if w e 1
Memory to Accumulator 1010000w addr-low addr-high
Accumulator to Memory 1010001w addr-low addr-high
Register/Memory to Segment Register 10001110 mod 0 reg r/m
Segment Register to Register/Memory 10001100 mod 0 reg r/m
PUSH e Push:
Register/Memory 11111111 mod 1 1 0 r/m
Register 0 1 0 1 0 reg
Segment Register 0 0 0 reg 1 1 0
POP e Pop:
Register/Memory 10001111 mod 0 0 0 r/m
Register 0 1 0 1 1 reg
Segment Register 0 0 0 reg 1 1 1
XCHG e Exchange:
Register/Memory with Register 1000011w mod reg r/m
Register with Accumulator 1 0 0 1 0 reg
IN e Input from:
Fixed Port 1110010w port
Variable Port 1110110w
OUT e Output to:
Fixed Port 1110011w port
Variable Port 1110111w
XLAT e Translate Byte to AL 11010111
LEA e Load EA to Register 10001101 mod reg r/m
LDS e Load Pointer to DS 11000101 mod reg r/m
LES e Load Pointer to ES 11000100 mod reg r/m
LAHF e Load AH with Flags 10011111
SAHF e Store AH into Flags 10011110
PUSHF e Push Flags 10011100
POPF e Pop Flags 10011101
Mnemonics © Intel, 1978
26
8086
Table 2. Instruction Set Summary (Continued)
Mnemonic and
Instruction Code
Description
ARITHMETIC 76543210 76543210 76543210 76543210
ADD e Add:
Reg./Memory with Register to Either 000000dw mod reg r/m
Immediate to Register/Memory 100000sw mod 0 0 0 r/m data data if s: w e 01
Immediate to Accumulator 0000010w data data if w e 1
ADC e Add with Carry:
Reg./Memory with Register to Either 000100dw mod reg r/m
Immediate to Register/Memory 100000sw mod 0 1 0 r/m data data if s: w e 01
Immediate to Accumulator 0001010w data data if w e 1
INC e Increment:
Register/Memory 1111111w mod 0 0 0 r/m
Register 0 1 0 0 0 reg
AAA e ASCII Adjust for Add 00110111
BAA e Decimal Adjust for Add 00100111
SUB e Subtract:
Reg./Memory and Register to Either 001010dw mod reg r/m
Immediate from Register/Memory 100000sw mod 1 0 1 r/m data data if s w e 01
Immediate from Accumulator 0010110w data data if w e 1
SSB e Subtract with Borrow
Reg./Memory and Register to Either 000110dw mod reg r/m
Immediate from Register/Memory 100000sw mod 0 1 1 r/m data data if s w e 01
Immediate from Accumulator 000111w data data if w e 1
DEC e Decrement:
Register/memory 1111111w mod 0 0 1 r/m
Register 0 1 0 0 1 reg
NEG e Change sign 1111011w mod 0 1 1 r/m
CMP e Compare:
Register/Memory and Register 001110dw mod reg r/m
Immediate with Register/Memory 100000sw mod 1 1 1 r/m data data if s w e 01
Immediate with Accumulator 0011110w data data if w e 1
AAS e ASCII Adjust for Subtract 00111111
DAS e Decimal Adjust for Subtract 00101111
MUL e Multiply (Unsigned) 1111011w mod 1 0 0 r/m
IMUL e Integer Multiply (Signed) 1111011w mod 1 0 1 r/m
AAM e ASCII Adjust for Multiply 11010100 00001010
DIV e Divide (Unsigned) 1111011w mod 1 1 0 r/m
IDIV e Integer Divide (Signed) 1111011w mod 1 1 1 r/m
AAD e ASCII Adjust for Divide 11010101 00001010
CBW e Convert Byte to Word 10011000
CWD e Convert Word to Double Word 10011001
Mnemonics © Intel, 1978
27
8086
Table 2. Instruction Set Summary (Continued)
Mnemonic and
Instruction Code
Description
LOGIC 76543210 76543210 76543210 76543210
NOT e Invert 1111011w mod 0 1 0 r/m
SHL/SAL e Shift Logical/Arithmetic Left 110100vw mod 1 0 0 r/m
SHR e Shift Logical Right 110100vw mod 1 0 1 r/m
SAR e Shift Arithmetic Right 110100vw mod 1 1 1 r/m
ROL e Rotate Left 110100vw mod 0 0 0 r/m
ROR e Rotate Right 110100vw mod 0 0 1 r/m
RCL e Rotate Through Carry Flag Left 110100vw mod 0 1 0 r/m
RCR e Rotate Through Carry Right 110100vw mod 0 1 1 r/m
AND e And:
Reg./Memory and Register to Either 001000dw mod reg r/m
Immediate to Register/Memory 1000000w mod 1 0 0 r/m data data if w e 1
Immediate to Accumulator 0010010w data data if w e 1
TEST e And Function to Flags, No Result:
Register/Memory and Register 1000010w mod reg r/m
Immediate Data and Register/Memory 1111011w mod 0 0 0 r/m data data if w e 1
Immediate Data and Accumulator 1010100w data data if w e 1
OR e Or:
Reg./Memory and Register to Either 000010dw mod reg r/m
Immediate to Register/Memory 1000000w mod 0 0 1 r/m data data if w e 1
Immediate to Accumulator 0000110w data data if w e 1
XOR e Exclusive or:
Reg./Memory and Register to Either 001100dw mod reg r/m
Immediate to Register/Memory 1000000w mod 1 1 0 r/m data data if w e 1
Immediate to Accumulator 0011010w data data if w e 1
STRING MANIPULATION
REP e Repeat 1111001z
MOVS e Move Byte/Word 1010010w
CMPS e Compare Byte/Word 1010011w
SCAS e Scan Byte/Word 1010111w
LODS e Load Byte/Wd to AL/AX 1010110w
STOS e Stor Byte/Wd from AL/A 1010101w
CONTROL TRANSFER
CALL e Call:
Direct within Segment 11101000 disp-low disp-high
Indirect within Segment 11111111 mod 0 1 0 r/m
Direct Intersegment 10011010 offset-low offset-high
seg-low seg-high
Indirect Intersegment 11111111 mod 0 1 1 r/m
Mnemonics © Intel, 1978
28
8086
Table 2. Instruction Set Summary (Continued)
Mnemonic and
Instruction Code
Description
JMP e Unconditional Jump: 76543210 76543210 76543210
Direct within Segment 11101001 disp-low disp-high
Direct within Segment-Short 11101011 disp
Indirect within Segment 11111111 mod 1 0 0 r/m
Direct Intersegment 11101010 offset-low offset-high
seg-low seg-high
Indirect Intersegment 11111111 mod 1 0 1 r/m
RET e Return from CALL:
Within Segment 11000011
Within Seg Adding Immed to SP 11000010 data-low data-high
Intersegment 11001011
Intersegment Adding Immediate to SP 11001010 data-low data-high
JE/JZ e Jump on Equal/Zero 01110100 disp
JL/JNGE e Jump on Less/Not Greater 01111100 disp
or Equal
JLE/JNG e Jump on Less or Equal/ 01111110 disp
Not Greater
JB/JNAE e Jump on Below/Not Above 01110010 disp
or Equal
JBE/JNA e Jump on Below or Equal/ 01110110 disp
Not Above
JP/JPE e Jump on Parity/Parity Even 01111010 disp
JO e Jump on Overflow 01110000 disp
JS e Jump on Sign 01111000 disp
JNE/JNZ e Jump on Not Equal/Not Zero 01110101 disp
JNL/JGE e Jump on Not Less/Greater 01111101 disp
or Equal
JNLE/JG e Jump on Not Less or Equal/ 01111111 disp
Greater
JNB/JAE e Jump on Not Below/Above 01110011 disp
or Equal
JNBE/JA e Jump on Not Below or 01110111 disp
Equal/Above
JNP/JPO e Jump on Not Par/Par Odd 01111011 disp
JNO e Jump on Not Overflow 01110001 disp
JNS e Jump on Not Sign 01111001 disp
LOOP e Loop CX Times 11100010 disp
LOOPZ/LOOPE e Loop While Zero/Equal 11100001 disp
LOOPNZ/LOOPNE e Loop While Not 11100000 disp
Zero/Equal
JCXZ e Jump on CX Zero 11100011 disp
INT e Interrupt
Type Specified 11001101 type
Type 3 11001100
INTO e Interrupt on Overflow 11001110
IRET e Interrupt Return 11001111
29
8086
Table 2. Instruction Set Summary (Continued)
Mnemonic and
Instruction Code
Description
76543210 76543210
PROCESSOR CONTROL
CLC e Clear Carry 11111000
CMC e Complement Carry 11110101
STC e Set Carry 11111001
CLD e Clear Direction 11111100
STD e Set Direction 11111101
CLI e Clear Interrupt 11111010
STI e Set Interrupt 11111011
HLT e Halt 11110100
WAIT e Wait 10011011
ESC e Escape (to External Device) 11011xxx mod x x x r/m
LOCK e Bus Lock Prefix 11110000
NOTES: if s w e 01 then 16 bits of immediate data form the oper-
AL e 8-bit accumulator and
AX e 16-bit accumulator if s w e 11 then an immediate data byte is sign extended
CX e Count register to form the 16-bit operand
DS e Data segment if v e 0 then ‘‘count’’ e 1; if v e 1 then ‘‘count’’ in (CL)
ES e Extra segment x e don’t care
Above/below refers to unsigned value z is used for string primitives for comparison with ZF FLAG
Greater e more positive;
SEGMENT OVERRIDE PREFIX
Less e less positive (more negative) signed values
if d e 1 then ‘‘to’’ reg; if d e 0 then ‘‘from’’ reg 0 0 1 reg 1 1 0
if w e 1 then word instruction; if w e 0 then byte instruc-
tion REG is assigned according to the following table:
if mod e 11 then r/m is treated as a REG field
16-Bit (w e 1) 8-Bit (w e 0) Segment
if mod e 00 then DISP e 0*, disp-low and disp-high are
absent 000 AX 000 AL 00 ES
if mod e 01 then DISP e disp-low sign-extended to
001 CX 001 CL 01 CS
16 bits, disp-high is absent
if mod e 10 then DISP e disp-high; disp-low 010 DX 010 DL 10 SS
if r/m e 000 then EA e (BX) a (SI) a DISP 011 BX 011 BL 11 DS
if r/m e 001 then EA e (BX) a (DI) a DISP 100 SP 100 AH
if r/m e 010 then EA e (BP) a (SI) a DISP
101 BP 101 CH
if r/m e 011 then EA e (BP) a (DI) a DISP
if r/m e 100 then EA e (SI) a DISP 110 SI 110 DH
if r/m e 101 then EA e (DI) a DISP 111 DI 111 BH
if r/m e 110 then EA e (BP) a DISP*
Instructions which reference the flag register file as a 16-bit
if r/m e 111 then EA e (BX) a DISP
object use the symbol FLAGS to represent the file:
DISP follows 2nd byte of instruction (before data if re-
FLAGS e X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
quired)
*except if mod e 00 and r/m e 110 then EA e disp-high;
disp-low.
Mnemonics © Intel, 1978
DATA SHEET REVISION REVIEW
The following list represents key differences between this and the -004 data sheet. Please review this summa-
ry carefully.
1. The Intel 8086 implementation technology (HMOS) has been changed to (HMOS-III).
2. Delete all ‘‘changes from 1985 Handbook Specification’’ sentences.
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