CSCI 4717/5717 Buses – Common Characteristics

• Multiple devices communicating over a single set of

Computer Architecture wires
• Only one device can talk at a time or the message
is garbled
Topic: Buses • Each line or wire of a bus can at any one time
contain a single binary digit. Over time, however, a
Reading: Stallings, Sections 3.4, 3.5, and 7.7 sequence of binary digits may be transferred
• These lines may and often do send information in
parallel
• A computer system may contain a number of
different buses
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Buses – Structure Buses – Structure (continued)

• Serial versus parallel • Bus lines (parallel)
• Around 50-100 lines although it's possible – Data
to have as few as 3 or 4 – Address
– Control
• Lines can be classified into one of four
– Power
groups
– Data lines • Bus lines (serial)
– Data, address, and control are sequentially sent down
– Address Lines single wire
– Control Lines – There may be additional control lines
– Power – Power

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Buses – Structure (continued) Bus Structure – Control lines

• Because multiple devices communicate on a line,
control is needed
• Data Lines • Timing
– Passes data back and forth • Typical lines include:
– Number of lines represents width – Memory Read or Write
– I/O Read or Write
• Address lines – Transfer ACK
– Designates location of source or destination – Bus request
– Width of address bus specifies maximum – Bus grant
memory capacity – Interrupt request
– Interrupt acknowledgement
– High order selects module and low order – Clock
selects a location within the module – Reset

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 Operation – Sending Data Operation – Requesting Data
• Obtain the use of the bus • Obtain the use of the bus
• Transfer the data via the bus • Transfer the data request via the bus
• Possible acknowledgement • Wait for other module to send data
• Possible acknowledgement

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Physical Implementations
Classic Bus Arrangement
• All components attached to bus (STD bus) • Parallel lines on circuit
• Due to Moore's law, more and more functionality boards (ISA or PCI)
exists on a single board, so major components • Ribbon cables (IDE)
are now on same board or even the same chip

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Physical Implementations (continued) Single Bus Problems

• Strip connectors on Lots of devices on one bus leads to:
mother boards (PC104) • Physically long buses
– Propagation delays – Long data paths mean that co-
• External cabling (USB or
ordination of bus use can adversely affect
Firewire) performance
– Reflections/termination problems
• Aggregate data transfer approaches bus
capacity
• Slower devices dictate the maximum bus speed

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 Multiple Buses Multiple Buses – Benefits
• Most systems use multiple buses to overcome • Isolate processor-to-memory traffic from
these problems I/O traffic
• Requires bridge to buffer (FIFO) data due to • Support wider variety of interfaces
differences in bus speeds • Processor has bus that connects as direct
• Sometimes I/O devices also contain buffering interface to chip, then an expansion bus
(FIFO) interface interfaces it to external devices
(ISA)
• Cache (if it exists) may act as the interface
to system bus

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Expansion Bus Example Mezzanine Approach

• Differences in I/O speeds demands separating
devices.
• Separate items that are high-speed and those
that are not
• An additional high-speed bus is added to
communicate with the faster devices and also
the slower expansion bus
• Advantage is that high-speed devices are
brought closer to processor

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Mezzanine Approach (continued)

Pentium
Example

(Source: http://www.amd.com/us-
en/assets/content_type/white_papers_and_tech_docs/21644.pdf)
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 Bus Types Bus Types
Dedicated vs. Time Multiplexed Physical Dedication
• Dedicated
– Physically separating buses and controlling
– Separate data & address lines
them with a "channel changer“
• Time multiplexed – Advantages – faster
– Shared lines – Disadvantages – physically larger
– Address valid or data valid control line
– Advantage - fewer lines
– Disadvantages
• More complex control
• Degradation of performance

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Bus Arbitration Centralised vs. Distributed Arbitration

• Listening to the bus is not usually a • Centralised Arbitration

problem – Single hardware device controlling bus
• Talking on the bus is a problem – need access – Bus Controller/Arbiter
arbitration to allow more than one module – May be part of CPU or separate
to control the bus at one time • Distributed Arbitration
• Arbitration may be centralised or – Each module may claim the bus
distributed – Access control logic is on all modules
– Modules work together to control bus

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Synchronous Bus Timing

Bus Timing
• Events determined by clock signals
• Co-ordination of events on bus • Control Bus includes clock line
• Synchronous – controlled by a clock • A single 1-0 cycle is a bus cycle
• Asynchronous – timing is handled by well- • All devices can read clock line
defined specifications, i.e., a response is
delivered within a specified time after a • Usually sync on leading/rising edge
request • Usually a single cycle for an event
• Analogy – Orchestra conductor with baton
• Usually stricter in terms of its timing
requirements
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 Synchronous Bus Timing
Asynchronous Timing
• Devices must have certain tolerances to
provide responses to signal stimuli
• More flexible allowing slower devices to
communicate on same bus with faster
devices.
• Performance of faster devices, however, is
limited to speed of bus

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Asynchronous Timing – Read Asynchronous Timing – Write

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Peripheral Component
Bus Width Interconnection (PCI) Bus
• Wider the bus the better the data transfer Brief history
rate or the wider the addressable memory • Original PC came out with 8-bit ISA bus which
space was slow, but had enormous amount of existing
equipment.
• Serial “width” is determined by • For AT, IBM expanded ISA bus to 16-bit by
length/duration of frame adding connector
• Many PC board manufacturers started making
higher speed, proprietary buses
• Intel released the patents to its PCI and this
soon took over as the standard
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 PCI Bus (continued) Required PCI Bus Lines (Table 3.3)
Brief list of PCI 2.2 characteristics • Systems lines – clock and reset
• General purpose • Address & Data
• Mezzanine or peripheral bus – 32 time multiplexed lines for address/data
• Supports single- and multi-processor – Parity lines
architectures • Interface Control
• 32 or 64 bit – multiplexed address and data – Hand shaking lines between bus controller and
devices
• Synchronous timing
– Selects devices
• Centralized arbitration (requires bus controller)
– Allows devices to indicates when they are
• 49 mandatory lines (see Table 3.3) ready
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Required PCI Bus Lines Optional PCI Bus Lines

(continued) There are 51 optional PCI 2.2 bus lines
• Arbitration • Interrupt lines
– Not shared – Not shared
– Direct connection to PCI bus arbiter – Multiple lines for multiple interrupts on a single device
• Cache support
• Error lines – parity and critical/system
• 64-bit Bus Extension
– Additional 32 lines
– Time multiplexed
– 2 lines to enable devices to agree to use 64-bit transfer
• JTAG/Boundary Scan – For testing procedures

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PCI Commands PCI Transaction Types

• Transaction between initiator (master) and • Interrupt acknowledge – prompts identification
target from interrupting device
• Special cycle – message broadcast
• Master claims bus
• I/O read – read to I/O address space
• During address phase of write, 4 C/BE
• I/O write – write to I/O address space
lines signal the transaction type
• Memory read – 1 or 2 data transfer cycles
• One or more data phases
• Memory read line – 3 to 12 data transfer cycles
• Memory read multiple – more than 12 data
transfers

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 PCI Read Timing Diagram
PCI Transaction Types (continued)
• Memory write – writing 1 or more cycles to memory
• Memory write and invalidate – writing 1 or more cycles to
memory allowing for cache write-back policy
• Configuration read – reading PCI device's configuration
(up to 256 configuration registers per device)
• Configuration write – writing PCI device's configuration
(up to 256 configuration registers per device)
• Dual address cycle – indication of 64-bit addressing on
32 bit lines

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PCI Bus Arbitration Between Two Masters

PCI Bus Arbiter

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Higher Performance External Buses IEEE 1394 FireWire

• Inexpensive alternative needed for SCSI
• Historically, parallel has been used for high • High performance serial bus
speed peripherals (e.g., SCSI, parallel port zip • Serial implies cheaper cabling (fewer wires, less
drives rather than serial port). High speed shielding, less synchronization)
serial, however, has begun to replace this need
• Small connectors for smaller devices
• Serial communication also used to be restricted
• Fast
to point-to-point communications. Now there's
an increasing prevalence of multipoint • Low cost
• Easy to implement
• Also being used in digital cameras, VCRs and
TVs

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 FireWire Configuration FireWire 3 Layer Stack
• Daisy chain/tree structure (Mac O/S Help
indicates that daisy chain is preference for
up to 16 devices)
• Up to 63 devices on single port – really 64
of which one is the interface itself
• Up to 1022 buses can be connected with
bridges
• Automatic configuration for addressing
• No bus terminators
• Hot swappable

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FireWire 3 Layer Stack Arbitration – Basic form

Physical Layer
• Upon automatic configuration, each tree
designates a root
• Transmission medium, electrical and
signaling characteristics • Parent/child relationship forms tree topology
• Root acts as central arbitrator
• Up to 400 Mbps
• Requests are first-come-first-serve
• Arbitration – basic form • Simultaneous requests are granted first to the
– Fair arbitration closest node to the root and second to the lower
– Urgent arbitration ID number
• Link layer packet transmission • Two additional functions are used to best allocate
– Asynchronous the use of the bus
– Fair arbitration
– Isochronous
– Urgent arbitration

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Fair arbitration Urgent arbitration

• Keeps one device from monopolizing the bus by • Allows overriding of fairness interval by
allowing only one request during a set fairness nodes configured as having an urgent
interval priority
• At beginning of interval, all devices set • Provides support for devices with severe
arbitration_enable flag latency requirements or high throughput
• Each device may compete for bus access such as video
• If bus access is granted, arbitration_enable flag • They may use the bus up to 75% of the
is cleared prohibiting bus access until next time, i.e., for each non-urgent packet,
fairness interval three urgent packets may be sent

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 FireWire 3 Layer Stack
Asynchronous
Link Layer
• Transmission of data in packets Packets contain
• Two types of transmission supported: • Variable amount of data
– Asynchronous • Several bytes of transaction layer
– Isochronous information
• Addressing information
• Acknowledgement

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Asynchronous Sequence Asynchronous Sequence (continued)

• Arbitration sequence – gives one device control of
the bus
• Packet transmission – packet contains source and
destination IDs, type, CRC, and possible data
• Acknowledgement gap – allows destination to
receive and process message
• Acknowledgement – destination sends packet
containing source and destination IDs and code
indicating action taken
• Subaction gap – idle period between packets to
avoid bus contention
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Isochronous Isochronous Sequence

• Fixed packet size w/variable amount of data
• Simplified addressing
• No acknowledgement
• Periodically, cycle_start packet is sent
indicating period where only isochronous
packets are transmitted
• Transaction – Request-response protocol
(This is what your code sees. It separates
the programmer from the packet-level stuff)

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