Syeda Haima Batool Naqvi CS-18022
CA ASSIGNMENT
Complex Engineering Problem
Q1) Create your own sequence of integer instructions that shows
existence of data hazards for this pipeline.
Answer: The following set of instructions shows change in
order of R/W accesses to operands where destination Register
($2) writes in 7th cycle but 3 instructions coming later requests to
read content of $2 before it is written hence showing data
hazard.
SUB $2, $1,
$3 XOR $4,
$1, $2 ADD
$5, $2, $6
OR $7, $1, $2
AND $8, $2, $2
DEPENDENICES ARE DESCRIBED AS:
I1: Register ($2), written by SUB
I2: 2 nd operand ($2) depends on SUB
I3: 1 st operand ($2) depends on SUB
I4: 2 nd operand ($2) depends on SUB
I5: 1 st ($2) & 2nd ($2) operands depend on SUB
Q2) Design a Forwarding Unit for the first execution unit (EX) that can
reduce the stalls introduced due to data hazards for this sequence.
Write the necessary conditions for all possible forwarding paths for
this unit and show the final design with all inputs and outputs.
Answer: The idea of forwarding means passing the result to one which needs the
result. For this we have a special unit which selects right value for ALU.
Now ALU has privilege to make 3 different decisions:
a. Take input from register file
Syeda Haima Batool Naqvi CS-18022
b. Provision of getting last computed value
c. Provision of getting earlier computed value
This forwarding unit will be EX stage since ALU forwarding multiplexers are in
that stage.
Problems arising for forwarding:
1. . Sometimes register will not be writing to register and hence flow of data
will be damaged as it will forward even at times when it shouldn’t be, so we
have to ensure if RegWrite = 1.
2. We want to avoid using Register $0 for destination operand in pipeline
because it’s value is fixed i.e. 0 and can’t be overwritten.
ASSUMPTIONS (for stating conditions of forwarding): We are assuming
only instructions we need to forward are R-type.
Syeda Haima Batool Naqvi CS-18022
CONDITIONS FOR DETECTING HAZARDS:
1a. (EX/MEM.RegWrite && (EX/MEM.Reg_Rd != 0) && (EX/MEM. Reg_Rd ==
ID/EX. Reg_Rs)
1b. (EX/MEM.RegWrite && (EX/MEM. Reg_Rd != 0) && (EX/MEM. Reg_Rd ==
ID/EX. Reg_Rt)
2a. (MEM/WB.RegWrite && (MEM/WB. Reg_Rd != 0) && (MEM/WB. Reg_Rd ==
ID/EX. Reg_Rs)
2b. (MEM/WB.RegWrite && (MEM/WB. Reg_Rd != 0) && (MEM/WB. Reg_Rd ==
ID/EX. Reg_Rt)
For the above stated conditions,
o SUB-XOR is a type 1b hazard:
EX/MEM. Reg_Rd == ID/EX. Reg_Rt = $2
The SUB-ADD is not a hazard because register file supplies the proper data during
the decode stage of OR, as DECODE reads in 2nd half cycle while new value of $2
has already been written in 1st half cycle of 6 th cycle.
Syeda Haima Batool Naqvi CS-18022
FINAL DESIGN WITH ALL INPUTS AND OUTPUTS:
Summarising results of FU output values:
Q3) Create another sequence of instructions where stalls due to data
hazards have to be inserted even with all forwarding options
available.
Answer:
Not all potential data hazards can be handled by bypassing. From LW ->
ADD or any R-type instruction, we can’t forward because our result is not
ready hence we’ll need stalls.
Called load-used hazard where LW is producing and another instruction
will use it in EX stage.
. Consider the following sequence of instructions
Syeda Haima Batool Naqvi CS-18022
LW $1, 0($2)
SUB $5, $3, $1
OR $3, $1, $6
ADD $7, $1, $6
The LW instruction does not have the data until the end of clock cycle 6 (its
MEM cycle).
While the SUB instruction needs to have the data by the beginning of that
clock cycle. Thus, the data hazard from using the result of a load instruction
cannot be completely eliminated with simple hardware.
We can forward the result immediately to the ALU from the MEM/WB
registers for use in the OR operation, which begins three clock cycles after
the load
Likewise, the ADD instruction has no problem, since it receives the value
through the register file, written in first half cycle of WB stage while read in
2nd half cycle by ADD instruction.
Q4) Design the Hazard Detection Unit (HDU) working in ID stage for
these types of hazards. An HDU can only insert a single stall per cycle.
Moreover, also specify which registers are required to remain
unchanged with the insertion of stall. Draw the final design of the ID
stage showing HDU’s input and outputs.
Answer:
To insert a stall between the load and its use ID we need a Hazard Detection Unit
in the ID stage.
Syeda Haima Batool Naqvi CS-18022
HAZARD DETECTION STALLS THE PIPELINE IF:
(ID/EX.MemRead && ((ID/EX.RegisterRt = IF/ID.RegisterRs) Or (ID/EX.RegisterRt =
IF/ID.RegisterRt)))
The first line tests to see if the instruction now in the EX stage is a lw; the next
two lines check to see if the destination register of the lw matches either source
register of the instruction in the ID stage (the load-use instruction)
To prevent the instructions in the IF and ID stages from progressing down the
pipeline – HDU works in this manner:
1. Freezes the IF/ID pipeline register
2. Freezes the PC register from changing
3. Turns Control signals = 0. Not all control signals are turned 0 but to
prevent new updating in register or memory just set RegWrite=0 and
MemWrite=0 so it can also serve our target.
HDU checks every two instructions, if after LW another instruction is using its
result it insert a “bubble” between the lw instruction (in the EX stage) and the
load-use instruction (in the ID stage) (i.e., insert a NOP in the execution stream).
And set the control bits in the EX, MEM, and WB control fields of the ID/EX
pipeline register to 0 (NOP). The Hazard Unit controls the mux that chooses
between the real control values and the 0’s. After this one cycle stall, the
forwarding logic can handle the remaining data hazards.
Syeda Haima Batool Naqvi CS-18022
Where,
Yellow colored boxes show hazards, while brown colored boxes show stalls.
Green boxes show decode can be easily done.
HDU freezes pipeline register which has 32-bit of SUB contained. Also, PC value is
also same in 2 consecutive cycles so next instruction is again going to be SUB
FINAL DESIGN WITH ALL INPUTS AND OUTPUTS:
Syeda Haima Batool Naqvi CS-18022
Summarising results of HDU output values:
Q5) For the sequence shown below
FADD F2,F4,F8
FADD F2,F2,F8
FADD F2,F2,F10
Using a pipeline diagram show how many cycles would be required
for proper execution of these instructions if forwarding is not
implemented.
Answers:
If forwarding is not implemented then:
I1: FADD F2, F4, F6
I2: FADD F2, F2, F8
I3: FADD F2, F2, F10
Syeda Haima Batool Naqvi CS-18022
Where, Yellow colored boxes show hazards, while brown colored boxes show
stalls. Green boxes show decode can be easily done.
Total cycles required are = 18
EXPLANATION:
It is to be noted that the common register among all instructions is F2 and
we have to enumerate added values every time back to this 64-bit register.
First Instruction I1 comes and executes for 8 clock cycles since it is 64-bit
instruction hence takes 2 EX stages.
Second instruction cannot come till 2 CC delay because IF was busy fetching
I1 in 2 stages of instruction fetch.
After fetching of I2, now it needs to decode the registers: F2 and F8 but
value of F2 is not ready till 8th cycle, while no forwarding is possible so we
also cannot bypass contents of F2 register so none option is left other than
to add stalls for 3 cycles.
At the 1st half of 8th clock cycle register F2 has been written which is
decoded by I2 in second half of same cycle.
Now I2 will execute smoothly.
Meanwhile at 8th cycle instruction I3 arrives which faces same problem of
unable to decode register F2 so it also has to wait for 3 cycles until new
value of F2 is written in first half of 13th cycle which is read by I3 in second
half of 13th cycle. Now it’ll run smoothly till end of instruction
Now no new instruction comes so total cycles we obtained were 18.
Syeda Haima Batool Naqvi CS-18022
Q6) Design a Forwarding Unit for the EX-1 stage of the second
execution unit that can reduce the stalls for instruction involving
floating point operations. Write the necessary conditions for all
possible forwarding paths for this unit and show the final design with
all inputs and outputs.
Answer:
The above diagram shows the Functional unit for first ALU for FP instructions.
While for 2nd ALU it’ll take 32-bits of result produced through ALU-1 and 32-bits
of remaining FP instruction as it is broken down to half for multistage operation
. This potential data hazard can occur when there is a conflict between the result
of the WB stage instruction and the MEM stage instruction – in such case which
should be forwarded? So we’ve to sum vector of numbers of register that are
overwritten again and again, hence we’ll alter only MEM/WB portion
CORRECTED DATA FORWARDING CONTROL CONDITIONS FOR SUM OF VECTORS
OF REGSITERS:
MEM/WB hazard:
Syeda Haima Batool Naqvi CS-18022
if (MEM/WB.RegWrite && (EX/MEM.Reg_Rd != ID/EX.Reg_Rs) &&
(MEM/WB.Reg_Rd = ID/EX.Reg_Rs))
ForwardA = 01
if (MEM/WB.RegWrite && (EX/MEM. Reg_Rd != ID/EX. Reg_Rt) &&
(MEM/WB. Reg_Rd = ID/EX. Reg_Rt))
ForwardB = 01
FINAL DESIGN WITH ALL INPUTS AND OUTPUTS:
