ISSN 2395-1680 (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, JULY 2015, VOLUME: 01, ISSUE: 02

DOI: 10.21917/ijme.2015.0015

NETWORK ON-CHIP AND ITS RESEARCH CHALLENGES

K. Paramasivam
Department of Electronics and Communication Engineering, Karpagam College of Engineering, India
E-mail:[email protected]

Abstract frequency, supply voltage, aspect ratio of device,

Networks-On-Chip (NoCs) have been proposed as a promising threshold voltage and leakage current.
solution for power, performance demands and scalability of next Several other factors like verification, testing, quick-time-to
generation Systems-On-Chip (SOCs) to overcome the several market, etc. are several drawbacks of SoC design in
challenges of current SoC with conventional architecture. In this
conventional architecture.
article, NoC, its architecture and features are presented. Further the
article is extended with research challenges. Major areas of scope for In order to design the SoC effectively, Network on Chip is
research are addressed briefly with the view that microelectronic field proposed. NoC is an advanced concept that overcomes the
researchers get benefitted. Performance analysing parameters and challenges focused by conventional chip architecture with
simulation tools for NoC are also included. Future SoC design needs dedicated bus structure between modules and IP cores in SoC. It
lot of innovations and creativity to explore its complete features. combines the features of IC technology and communication
Research on NoC is mandatory at this critical juncture.
paradigm to replace the traditional bus structure. NoC connects
the IP cores through set of links and routers which are placed in
Keywords: a given network topology.
Network on Chip, System on Chip, Power Dissipation, Research NoC is a Communication subsystem on an Integrated circuit
Challenges, NOC Architecture, Network Interface (commonly called a "chip"), typically between IP cores in a
system on a chip. The architecture of SoC are getting
1. INTRODUCTION communication- bound both from physical wiring and
distributed computation point of view. Wiring delays are
Today's modern lifestyle has been transformed with the becoming dominates over gate delays, which favours short links.
development of latest micro electronic technologies like The overall computation is heterogeneous and localized rather
pervasive and ubiquitous computing, ambient intelligence, than evenly balanced over the chip for larger Soc. These two
communication and internet. The developed electronic gadgets factors motivate NoC that brings the techniques developed for
are enhancing the way of communication, learning and macro-scale, multi-hop networks into a chip[1].
entertainment. SoC, the latest development in solid state Network-On-Chip technology is hastily shifting traditional
electronics is vital driving force for these advancements. SoC bus and crossbar approaches for SoC on-chip interconnect.
packs complete system in a single integrated chip. The most Many terms are being used in the industry. On-Chip Networks,
important features of SoC are smaller in size, faster in speed, Interconnect Fabrics, Networks-On-Chips and so on. The term
larger in capacity, lighter in weight, lesser in power consumption “on-chip interconnect” is considered an umbrella name for all
and lesser in cost. Though it is developed in great extent SoC approaches. The Network-on-Chip is one specific architecture
has following challenges to grow further; and is defined as “an on-chip interconnect with decoupled
1. Signal integrity effects in deep submicron technology transaction layer, transport layer and physical layer”[1].
such as interconnect delay, crosstalk, inter symbol The wires in the links of the NoC are shared by many
interference, substrate coupling, etc. signals. A high level of parallelism is achieved, because all links
2. Synchronization problem between global and local in the NoC can operate simultaneously on different data packets.
circuits due to non-proportionate technology scaling in Therefore, as the complexity of integrated systems keeps
wires and gates. growing, a NoC provides enhanced performance (such as
3. Bus System: The bus system implemented in most of throughput) and scalability in comparison with previous
SoCs is dedicated signal wires. The parameters such as communication architectures (e.g., dedicated point-to-point
bandwidth, clock frequency and power are not improved signal wires, shared buses, or segmented buses with bridges).
as expected due to non-proportionate scaling between bus NoCs can span synchronous and asynchronous clock
and system size. Further, the bus structure has following domains or use unclocked asynchronous logic. NoC technology
limitations. applies networking theory and methods to on-chip
a. Limited parallel data transfer capability communication and brings notable improvements over
conventional bus and crossbar interconnections. NoC improves
b. Performance degradation with increase in integration
the scalability of SoCs, and the power efficiency of complex
technology
SoCs compared to other designs.
c. Energy inefficient in data transfer
As the number of IP modules in Systems-on-Chip increases,
4. Power dissipation: Power dissipation is becoming critical bus-based interconnection architectures may inhibit these
problem in latest VLSI circuits as operating frequency is systems to meet the performance required by many applications.
increased. It is very challenging task to solve the power For systems with intensive parallel communication requirements
problem with constrained parameters such as clock buses may not provide the required bandwidth, latency, and

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power consumption. A solution for such a communication 8. Offers varying guarantees for transfers.
bottleneck is the use of an embedded switching network, called 9. It offers support for system testing.
Network-on-Chip, to interconnect the IP modules in SoCs [2].
Network-on-chip is the most important area of research 1.1 NoC ARCHITECTURE
carries out by many R&D institutions all around the world. The
NoC is composed of three main blocks. Network Interfaces
latest contributions on key design issues at different levels of
(NI), Router and Links is shown in Fig.1. NI makes the logic
abstraction, namely, design technology, architecture design &
connection between the IP cores and the network, since each IP
optimization, physical link design, performance and power
have a distinct interface protocol with respect to the network.
characterization. Applying the networking concept to on chip
communication is part of the breakthrough solutions urged by
the advances in silicon manufacturing technology [3].
The term NoC is used in research today in a very broad sense
ranging from gate level physical implementation, across system
layout aspects and applications, to design methodologies and
tools [4].
Traditionally, ICs have been designed with dedicated point-
to-point connections, with one wire dedicated to each signal. For
large designs, in particular, this has several drawbacks from a
physical design viewpoint. The wires occupy much of the area Fig.1. Basic Architecture of NoC [1]
of the chip, and in nanometer CMOS technology, interconnects
dominate both performance and dynamic power dissipation, as Router is like a "much smarter buffer". It basically receives
signal propagation in wires across the chip requires multiple the packets from the shared links and according to the address
clock cycles. informed in each packet, it forwards the packet to the core
attached to it or to another shared link. Router is composed of a
NoC links can reduce the complexity of designing wires for
number of input and output ports, a switching matrix connecting
predictable speed, power, noise, reliability, etc., thanks to their
the input ports to the output ports and a local port to access the
regular, well controlled structure. From a system design
IP core connected to this router. The buffering policy is the
viewpoint, with the advent of multi-core processor systems, a
strategy used to store information in the router when there is
network is a natural architectural choice. A NoC can provide
congestion in the network and a packet cannot be forwarded
separation between computation and communication; support
right away [2].
modularity and IP reuse via standard interfaces, handle
synchronization issues, serve as a platform for system test, and Links are used to physically connect the nodes and establish
hence, increase engineering productivity. the communication. It composed of a set of wires and connects
two router in the network. The concept of flits is defined at this
With NoCs, it is possible to take advantage of part of the
level. A packet which is split into smaller data unit is known as
technology developed for packet switched networks in the field
flit.
of communication theory and computer networks, adapting those
concepts to the particular constraints of on chip interconnection.
NoC can achieve a very high degree of flexibility, using 2. RESEARCH CHALLENGES IN NoC
modularity (extensive use of parameterized independent
functional blocks) and reconfigurability (functional blocks can The major goal of communication-centric deign and NoC
be mutually connected in different manners in order to create the paradigm is to achieve greater design productivity and
particular topology needed for a given application). NoC performance by handling the increasing parallelism,
provides good scope to easily integrate IP cores developed by manufacturing complexity, wiring problems and reliability. The
different people or companies, provided that this module shares three critical challenges for NoC according to Owens et al. are:
a common interface for communication with the external power, latency and CAD compatibility [1].
environment.
2.1 CRITICAL ANALYSIS OF NoC
The basic properties of the NoC paradigm are listed as
follows [5]: In order to overcome the problems associated with bus-based
1. It separates communication from computation. interconnects, several approaches for networks-on-chip have
been proposed, thereby employing reuse of communication
2. Avoids global, centralized controller for communication.
resources and providing enhanced reusability and
3. Allows arbitrary number of terminals. programmability by using standardized and layered
4. It has a topology that allows the addition of links as the communication protocols. A popular approach for NoCs is to
system size grows. employ a regular mesh structure with packet switching, thereby
5. Does not utilize long, global wires spanning the whole allowing total system bandwidth to increase for each additional
chip. network element, since the number of simultaneous
communication paths increase. In contrast to the shared bus
6. Allows multiple voltage and frequency domains.
approaches, NoCs provide greater performance scalability and
7. It delivers data in-order either naturally or via layered multiple simultaneous transactions are supported, resulting in
protocol. more efficient network resource utilization. Furthermore, the

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relation between wire length and system size depends on the 3. Traffic characterization: latency-critical, data-stream and
distribution of area between network elements, and hence, on the best effort.
regularity of the network; a 2D mesh NoC assumes a constant The purpose of the network adapter (NA) is to interface the
wire length, independent of system size [6]. core to the network and make communication services
transparently available with a minimum of effort from the core.
2.2 NoC ISSUES AND CHALLENGES At this point, the boundary between computation and
To improve system productivity, it is very important that an communication is specified. The research area in network
architect be able to abstract, represent and address most of the adapters is given below,
design issues and concerns at a high level of abstraction. 1. Encapsulation, service management
System-level design affords one the opportunity to review 2. Sockets: plug and play, IP reuse
several different software-hardware architectures that meet the
The emerging research area in network are listed below
functional specifications equally well, to quickly trade-off
among different QoS metrics such as latency, power, cost, size 1. Topology: regular vs irregular topologies, switch layout
and ease of integration. Similarly, there are several issues related 2. Protocol: routing, switching and control schemes
to NoC, such as the nature of the NoC link, link length, serial vs 3. Flow control: deadlock avoidance, virtual channels and
parallel links, bus vs packet-based switching, and leakage buffering.
current [7].
4. Quality-of-service: service classification and negotiation.
2.2.1 Serial vs Parallel Link:
5. Features: error-correction, broadcast, multicast,
The transportation of data packets among various cores in a narrowcast and virtual wires.
NoC can be performed by the use of either a serial or a parallel The research area in link level is synchronization, reliability
link. Parallel links make use of a buffer-based architecture and and encoding.
can be operated at a relatively lower clock rate in order to reduce
power dissipation. However, these parallel links will incur high The system includesapplications and architecture (cores and
silicon cost due to inter-wire spacing, shielding and repeaters. network). At this level, most of the network implementation
This can be minimized up to a certain limit by employing details may still be hidden. Much research done at this level is
multiple metal layers. On the other hand, serial links allow applicable to large scale SoC design in general.
savings in wire area, minimization in signal interference and The NA is the first level which is network aware. The
noise, and further eradicate the need for having buffers. Serial network consists of the routing nodes, links, etc, defining the
links offer the advantages of a simpler layout and simpler timing topology and implementing the protocol and node-to-node flow
verification. Serial links sometimes suffer from ISI (Inter- control.
symbol Interference) between successive signals while operating The network adapter decouples the cores from the network.
at high clock rates. Nevertheless, such drawbacks can be It handles the end to end flow control, encapsulating the
addressed by encoding and with asynchronous communication messages or transactions generated by the cores for the routing
protocols. strategy of the Network. These are broken into packets which
2.2.2 Interconnect Optimization: contain information about their destination, or connection-
oriented streams which do not, but have had a path setup prior to
Communication in a NoC is based on modules connected via
transmission.
a network of routers with links between the routers that comprise
of long interconnects. Thus it is very important to minimize The lowest level is the link level. The research in link level
interconnects in order to achieve the required system regards the node-to-node links. Hence links consist of one or
performance. Timing optimization of global wires is typically more channels which can be either virtual or physical. Link-
performed by insertion of repeaters. It results in a significant level research deals mostly with encoding and synchronization
increase in cost, area, and power consumption. Recent studies issues [4].
indicate that in the near future, inverters operating as repeaters The key issues in NoC research are Noc network
will use a large portion of chip resources. Thus, there is a need architecture, Noc network performance analysis and NoC
for optimizing power on the NoC. Encoding is an effective way communication refinement.
of reducing dynamic power consumption. In order to make NoC 2.3.1 Topology:
architectures more effective, innovative ways will have to be
introduced to optimize the power consumed by the on-chip In network architecture the topology defines how the nodes
repeaters [7]. are interconnected in a network. Numerous topologies including
mesh, torus, fat tree, butterflies [8], crossbar, express cube and
2.3 CLASSIFICATION OF RESEARCH AREA irregular [9] have been proposed. The most common topologies
are 2-D mesh and torus which constitute over 60% of cases.
The NoC research area is classified as system level, network Both have connection between 4 neighbour nodes but torus has
adapters, network and link level [4]. The system level research is wraparound links connecting the nodes on network edges [1].
composed of:
2.3.2 Switching Techniques:
1. Design methodology and abstraction.
Switching techniques defines how the data is transmitted
2. Architecture domain: system composition, clustering and from the source node to destination node. In the circuit
reconfigurability. switching approach, a path is formed from source to destination

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prior to transfer by reserving the routers and links. All the data In Handshaking signal based flow control, a VALID signal is
follow that route and path is torn down after the transfer has sent whenever a sender transmits any flit. The receiver
completed [1]. acknowledges by asserting a VALID signal after consuming the
Packet based switching is one, where all flits of the packet data flit. Zeferino et al. used handshaking signals in their SoCIN
are sent, as the header establishes connection between routers NOC implementation [11].
[2]. There is a need to buffer packets in the switch, which In the ACK/NACK protocol a copy of a data flit is kept in a
implies that switches will occupy more space on the silicon area. buffer until an ACK signal is received. On declaration of ACK,
The packet based switch is classified as wormhole switching, the flit is deleted from the buffer; instead if a NACK signal is
Virtual cut through switching, and switch & forward switching. asserted then the flit is scheduled for retransmission.
In wormhole switching, the messages are divided into The T-Error flow control scheme is very complex as
smaller fixed length flow units called flits. A limitation of this compared to other flow control mechanisms. It aims at
method is that messages are not interleaved, only one message improving the performance at the cost of reliability. Real time
can sent over a given physical connection at the same time [9]. systems operating in a noisy environment must avoid the use of
Switch and Forward switching technique forwards a packet this flow control mechanism. None of the present NoC
only when there is enough space available in the receiving buffer implementations has employed this flow control scheme [7].
to hold the whole packet. There is no need to divide a packet.
This minimizes the overhead problem.
2.4 PERFORMANCE ANALYSIS
Virtual-cut through is much like the wormhole switching and The implementation and performance of a network on chip
the main difference is that the header flit can travel ahead of the can be evaluated by several parameters. They are area
remaining flits and undergo processing, where the other flits are consumption, power consumption, bandwidth, throughput and
passing through the network. latency [2]. Area and power are related with hardware part of
2.3.3 NoC Routing: NoC.
The bandwidth refers to the maximum rate of data
The NoC routing mechanism is responsible for correct and
propagation once a message is in the network. The unit of
efficient routing of packets that are traversing the network from
measures of bandwidth is bit per second (bps) and it usually
source to target [9].
considers the whole packet, including the bits of the header,
Routing algorithm decides the path that a packet should take payload and tail.
to reach to its destination. High performance, load-balance,
Throughput is defined as the maximum traffic accepted by
deadlock-free and livelock-free, fault-tolerant are the desirable
the network that is the maximum amount of information
properties of a routing algorithm for NoC [8].
delivered per time unit.
Routing scheme can be classified into various categories:
Latency is the time elapsed between the beginning of the
The routing can be static or dynamic, distributed or source
transmission of a message and its complete reception at the
routing and minimal or non-minimal. In static routing permanent
target node.
paths from a given source to destination are defined. It may use
single path or split the traffic is a predefined way among several
paths. In dynamic routing, the traffic between a source target 3. NoC SIMULATION TOOLS
changes its route with time. In distributed routing, each packet
carries the destination address [9]. In source routing, the pre- Several types of software simulation tools are used and being
computed routing tables are stored in the NI at the system developed by scientific research teams [14]. Primarily they are
modules. The power consumption introduced by non-minimal used for simulation and synthesis purpose. Few simulation tools
routing prohibitively increases the expensive in the NoC. addressed in the literatures [14] are given as follows;
2.3.4 Flow Control: 1. NS-2 is used for prototyping and simulating conventional
computer networks. Since NoCs shares many
Another research area in NoC is flow control [7]. It characteristics with computer networks, NS-2 was widely
determines how network resources, such as channel bandwidth, used by many NoC researchers to simulate NoCs [15-16].
buffer capacity, and control state, are allocated to a packet
traversing the network. The flow control may be classified as 2. Noxim This tool has been proposed by the Computer
buffered or bufferless. Architecture team at the University of Catania [17]. It is
developed in SystemC language. It allows the user to
The bufferless flow control has more latency and less define a 2D mesh NoC architecture with various
throughput than the buffered flow control. The buffered flow parameters including: 1) Network size 2) Buffers size 3)
control can be further categorized into credit based flow control, Packet size 4) Routing algorithm 5) Injection rate of
ACK/NACK flow control, STALL/GO flow control, T-Error packets. Noxim allows the evaluation of NoCs in terms of
flow control, and Handshaking Signal based flow control. throughput, latency and power consumption.
In credit based flow control, an upstream node keeps count 3. DARSIM is a NoC simulator which was developed at the
of data transfers, and thus the available free slots are termed as Massachusetts Institute of Technology (MIT). This tool
credits. Once the transmitted data packet is either consumed or allows the simulation of mesh NoC architectures of 2 and
further transmitted, a credit is sent back. Bolotin et al. used 3 dimensions [18].
Credit Based flow control in QNOC [7].

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4. SunFloor - 3D SunFloor: SunFloor is a support tool for [7] Ankur Agarwal, Cyril Iskander and Ravi Shankar, “Survey
NoC design. It can be used at earlier design phases to of Network on Chip (NoC) architecture and contributions”,
synthesize the most appropriate topology with these Journal of Engineering Computing and Architecture,
constraints as input (Model, Energy and Space, Design Vol. 3, No. 1, pp. 21-27, 2009.
Objectives). From these data, SunFloor generates a [8] Yongfeng Xu, Jianyang Zhou and Shunkui Liu, “Research
system specification ready to be translated into and Analysis of Routing Algorithms for NoC”,
comprehensive architecture, usually in SystemC language Proceedings of 3rd International Conference on Computer
and by the intervention of a second tool which is Research and Development, pp. 98-102, 2011.
xpipesCompiler. SunFloor 3D is an extension of the later
[9] Giovanni De Micheli and Luca Benini, “Networks-on-
version [19].
Chips: Technology and Tools”, Morgan Kaufmann
5. ORION 2.0 is the successor of the version proposed by a Publishers, 2006.
team from Princeton University in 2003 [20]. It is a
[10] Dan Marconett, “A survey of Architectural Design and
simulator dedicated primarily to the estimation of power
Implementation Tradeoffs in Network on Chip Systems”,
and space for NoCs architectures.
University of California, pp.1-8, 2006.
[11] C. A. Zeferino and A. A. Susin, “SoCIN: A parametric and
4. CONCLUSION
scalable network-on-chip”, Proceedings of 16th Symposium
on Integrated Circuits and Systems Design, pp. 169-174,
NoC encompasses a wide spectrum of research, ranging from
2003.
highly abstract software related issues, across system topology
to physical level implementation. This paper gives an overview [12] U. Y. Ogras and R. Marculescu, “Modeling, Analysis and
of state-of-the art network-on-chip. The emerging field of NoC Optimizationof Network-on-Chip Communication
research and design challenges were discussed. Network on Architectures”, Lecture Notes in Electrical Engineering,
Chip is a very active research field with many practical Vol. 184, 2013.
applications in industry. This work focuses on the system, [13] O. Tayan, “Network-on-chip: challenges, trends and
network and link level issues of the communication mechanisms for enhancements”, Proceedings of
infrastructure. NoC research areas have to be explored to meet International Conference on Information and
the design challenges in advanced SOC system that becomes Communication Technologies, pp. 57-62, 2009.
leader in microelectronics. [14] Ahmed Ben Achballah and Slim Ben Saoud, “A Survey of
Network-On-Chip Tools”, International Journal of
REFERENCES Advanced Computer Science and Applications, Vol. 4,
No. 9, pp. 61-67, 2013.
[1] Erno Salminen, Ari Kulmala and Timo D. Hamalainen, [15] M. Ali, Michael Welzl, A. Adnan and F. Nadeem, “Using
“Survey of Network-on-chip Proposals”, White Paper, the NS-2 Network Simulator for Evaluating Network on
OCP-IP, 2008. Chips (NoC)”, International Conference on Emerging
[2] Erika Cota, Alexandre de Morais Amory and Marcelo Technologies, pp. 506 – 512, 2006.
Soares Lubaszewski, “Reliability, Availability and [16] NS-2 website. Available:
Serviceability of Networks-on-Chip”, Springer, 2012. http://nsnam.isi.edu/nsnam/index.php/Main_Page
[3] Davide Bertozzi, Shashi Kumar and Maurizio Palesi, [17] Noxim website. Available: www.noxim.org
“Networks-on-Chip: Emerging Research Topics and Novel
[18] Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Pengju
Ideas”, VLSI Design, Vol. 2007, Article No. 26454, pp.1-3,
Ren, Omer Khan and Srinivas Devadas, “DARSIM: A
2007.
Parallel Cycle-Level NoC Simulator”, 6thAnnual Workshop
[4] Tobias Bjerregaard and Shankar Mahadevan, “A Survey of on Modeling, Benchmarking and Simulation, 2010.
Research and Practices of Network-on-Chip”, ACM
[19] C. Seiculescu, S Murali, L Benini and G. De Micheli,
Computing Surveys, Vol. 38, No. 1, 2006.
“SunFloor 3D: A Tool for Networks on Chip Topology
[5] Erno Salminen, Ari Kulmala and Timo D. Hamalainen, Synthesis for 3D Systems on Chips”, Proceedings of
“On Network-on-Chip comparison”, Tenth Euromicro Design, Automation and Test in Europe Conference &
Conference on Digital System Design: Architectures, Exhibition, pp. 9-14, 2009.
Methods and Tools, pp. 503-510, 2007.
[20] Hang-Sheng Wang, Xinping Zhu, Li-Shiuan Peh and S.
[6] C. A. Zeferino, M. E. Kreutz, L. Carro and A. A. Susin, “A Malik, “Orion: A Power-Performance Simulator for
study on communication issues for systems-on-chip”, Interconnection Networks”, Proceedings of 35thAnnual
Proceedings of the 15th Symposium on Integrated Circuits IEEE/ACM International Symposium on
and Systems Design, pp. 121-126,2002. Microarchitecture, pp. 294-305, 2002.
[21] http://en.wikipedia.org/wiki/Network_on_a_chip.

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