Instruction Set
Architecture (ISA)
Objectives
To understand the importance of
Instruction Set Architecture,
discuss the features that need to
be considered and discuss an
example ISA
Instruction Set Architecture (ISA)
software
instruction set
hardware
Instruction Set Architecture
• Understanding the language of the hardware is key to understanding
the hardware/software interface
– To command a computer, you must speak its language
– Instructions are the words of a computer’s language
– Instruction set is its vocabulary
• A program (in say, C) is compiled into an executable that is composed
of machine instructions – this executable must also run on future
machines – for example, each Intel processor reads in the same x86
instructions, but each processor handles instructions differently
• Java programs are converted into portable bytecode that is converted
into machine instructions during execution (just-in-time compilation)
• What are important design principles when defining the instruction
set architecture (ISA)?
4
ISA Contd.
• Important design principles when defining the
instruction set architecture (ISA):
keep the hardware simple – the chip must only
implement basic primitives and run fast
keep the instructions regular – simplifies the
decoding/scheduling of instructions
We will later discuss RISC vs CISC
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A Basic Instruction
C code: a=b+c;
Assembly code: (human-friendly machine instructions)
add a, b, c # a is the sum of b and c
Machine code: (hardware-friendly machine instructions)
00000010001100100100000000100000
Translate the following C code into assembly code:
a = b + c + d + e;
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Example
C code a = b + c + d + e;
translates into the following assembly code:
add a, b, c add a, b, c
add a, a, d or add f, d, e
add a, a, e add a, a, f
• Instructions are simple: fixed number of operands (unlike C)
• A single line of C code is converted into multiple lines of
assembly code
• Some sequences are better than others… the second
sequence needs one more (temporary) variable f
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Subtract Example
C code f = (g + h) – (i + j);
Assembly code translation with only add and sub instructions:
add t0, g, h add f, g, h
add t1, i, j or sub f, f, i
sub f, t0, t1 sub f, f, j
• Each version may produce a different result because
floating-point operations are not necessarily
associative and commutative… more on this later
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Operands
• In C, each “variable” is a location in memory
• In hardware, each memory access is expensive – if
variable a is accessed repeatedly, it helps to bring the
variable into an on-chip scratchpad and operate on the
scratchpad (registers)
• To simplify the instructions, we require that each
instruction (add, sub) only operate on registers
• Note: the number of operands (variables) in a C program is
very large; the number of operands in assembly is fixed…
there can be only so many scratchpad registers
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Interface Design
A good interface:
• Lasts through many implementations
(portability, compatability)
• Is used in many different ways (generality)
• Provides convenient functionality to higher
levels
• Permits an efficient implementation at lower
levels
Evolution of Instruction Sets
• Design decisions must take into
account
• Technology
• Machine organization
• Programming languages
• Compiler technology
• Operating systems
• And they in turn influence these
Information in an instruction
• Operation to be done
• Source operands
• Destination operand
• Address of the next instruction
• Use of Program Counter
• Three address, two address, single address and zero address
instructions
Classifying Instruction Set Architectures
Based on the type of Internal Storage in a
processor
• Stack
• Accumulator
• General-purpose register (GPR)
• Register–Memory
• Register-register/load-store
• Memory – Memory (not used now)
Classifying Instruction Set Architectures
Classification is based on:
• Number of memory operands in
an ALU operation
• Total number of operands in an
ALU operation
Comparison of ISAs
Stack Accumulator
Push A Load A
Push B Add B
Add Store C
Pop C
Code sequence for (C = A + B) for different
classes of instruction sets
Comparison of ISAs
Register Register
(register-memory) (load-store)
Load R1,A Load R1,A
Add R1,B Load R2,B
Store C, R1 Add R3,R1,R2
Store C,R3
Code sequence for (C = A + B) for different
classes of instruction sets
Registers are the class that won out.
The more registers on the CPU, the better.
GPR Architectures
Number of Type of
Maximum number of Examples
memory addresses Architecture
operands allowed
0 3 Register-register MIPS, SPARC
IBM360/370,
1 2 Register-memory Intel 80x86
2 2 Memory- VAX
memory
3 3 Memory-memory VAX
Features to be considered while designing the ISA
Types of instructions (Operations in the
Instruction set)
Types and sizes of operands
Addressing Modes
Addressing Memory
Encoding and Instruction Formats
Compiler related issues
Types of instructions
Choose commonly used instructions
Make them faster
Specialized instructions depending upon the
application of the processor
Eg. Media and Signal Processing
• Single-instruction multiple-data (SIMD) or
vector instructions
• Saturating arithmetic operations
• Multiply-accumulate (MAC) instructions
Categories of instructions and examples
• Arithmetic and Logical - Integer
arithmetic and logical operations: add,
subtract, and, or, multiply, divide
• Data transfer - Loads-stores (move
instructions on computers with
memory addressing)
• Control - Branch, jump, procedure call
and return, traps
Categories of instructions and examples
• System - Operating system call, virtual
memory management instructions
• Floating point - Floating-point
operations:add, multiply, divide,
compare
• Decimal - Decimal add, decimal
multiply, decimal-to-character
conversions
Categories of instructions and examples
• String - String move, string compare,
string search
• Graphics - Pixel and vertex
operations,
compression/decompression
operations
Types and Sizes of operands
• Common operand types - Character
(8 bits), Half word (16 bits), Word
(32 bits), Single Precision Floating
Point (1 Word), Double Precision
Floating Point (2 Words)
• Integers are two’s complement
binary numbers
Types and Sizes of operands
• Characters are usually in ASCII
• Floating point commonly follows
the IEEE Standard 754
• Packed and unpacked decimal
Memory Addressing
Memory Addressing includes
Interpreting Memory Addresses
Addressing Modes
Interpreting Memory Addresses - Endian-ness
Two major formats for transferring values between registers and memory
Memory: low address 45 7b 87 7f high address
Little-endian register: the first byte read goes in the low end of the register
Register: 7f 87 7b 45
Most-significant byte Least-significant byte (x86)
Big-endian register: the first byte read goes in the big end of the register
Register: 45 7b 87 7f
Most-significant byte Least-significant byte (MIPS, IBM)
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Alignment
• Data must be aligned on a boundary
equal to its size
• An access to an object of size s bytes
at byte address A is aligned if A mod s
=0
• Misalignment typically results in an
alignment fault that must be handled
by the Operating System
Addressing Modes
Addressing Example Meaning Usage
Mode Instruction
Register Add R4, R3 R[R4] <- When a
R[R4] + R[R3] value is in a
register
Immediate Add R4, #3 R[R4] <- For
R[R4] + 3 constants
Addressing Modes
Displacement Add R4, R[R4] <- Accessing
100(R1) R[R4] + local
variables
M[100+R[R1
]]
Register Add R4, R[R4] <- Using a
Deferred (R1) R[R4] + pointer or a
computed
M[R[R1] ] address
Absolute Add R4, R[R4] <- Used for
(1001) R[R4] + static data
M[1001]
Instruction Encoding
Three basic variations in instruction
encoding are Variable length, fixed
length and hybrid
(a) Variable (e.g., VAX, Intel 80x86)
Operation and no. Address Address Address Address
of operands Specifier 1 field 1 Specifier n field n
Instruction Encoding
(b) Fixed (e.g., Alpha, ARM, MIPS, PowerPC,
SPARC, SuperH)
Operation Address field 1 Address field 2 Address field 3
Instruction Encoding
(c) Hybrid (e.g., IBM360/370, MIPS16, Thumb, TI TMS320C54x)
Address
Operation Specifier Address field
Address Address
Operation Specifier 1 Specifier 2 Address field
Address
Operation Specifier Address field Address field
1 2
The Role of Compilers
Compiler goals
• All correct programs execute
correctly
• Most compiled programs execute
fast (optimizations)
• Fast compilation
• Debugging support
OPTIMIZATIONS
Optimizations performed by modern
compilers can be classified by the style of
the transformation, as follows:
• High-level optimizations are often done on
the source with output fed to later
optimization passes
• Local optimizations optimize code only
within a straight-line code fragment (called
basic block by compiler people)
OPTIMIZATIONS
• Global optimizations extend the local
optimizations across branches and
introduce a set of transformations aimed at
optimizing loops
• Register allocation associates registers with
operands
• Processor-dependent optimizations attempt
to take advantage of specific architectural
knowledge
Architect’s help to the Compiler Writer
• Regularity
• Orthogonality
• Composability
Compilers perform a giant case analysis
• too many choices make it hard
Orthogonal instruction sets
• operation, addressing mode, data type
Architect’s help to the Compiler Writer
One solution or all possible solutions
• 2 branch conditions eq, lt
• or all six eq, ne, lt, gt, le, ge
• not 3 or 4
There are advantages to having instructions
that are primitives
Let the compiler put the instructions together
to make more complex sequences
Evolution of Instruction Sets
Single Accumulator (EDSAC 1950)
Accumulator + Index Registers
(Manchester Mark I, IBM 700 series 1953)
Separation of Programming Model
from Implementation
High-level Language Based Concept of a Family
(B5000 1963) (IBM 360 1964)
General Purpose Register Machines
Complex Instruction Sets Load/Store Architecture
(Vax, Intel 432 1977-80) (CDC 6600, Cray 1 1963-76)
RISC
(Mips,Sparc,HP-PA,IBM RS6000,PowerPC . . .1987)
LIW/”EPIC”? (IA-64. . .1999)
Evolution of Instruction Sets
• Major advances in computer architecture
are typically associated with landmark
instruction set designs
• Ex: Stack vs. GPR (System 360)
• CISC vs. RISC
Summary
• Importance of ISA design
• Features that need to de decided
while designing the ISA of a
processor
• Taxonomy of ISAs
Thank You
