HDL Lab Manual 18ECL58
PROGRAM 1A: Write Verilog program to realize 2 to 4 decoder using NAND
gates only (structural model)along with test bench to verify the design:
Block diagram:
enable
ACTIVE HIGH y(3:0)
a(1:0) 2:4 DECODER
Example of decoder:
Truth Table:
EN A B D3 D2 D1 D0
0 x x 1 1 1 1
1 0 0 1 1 1 0
1 0 1 1 1 0 1
1 1 0 1 0 1 1
1 1 1 0 1 1 1
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HDL Lab Manual 18ECL58
VERILOG SOURCE CODE:
module dec24str (A,B,EN,D3,D2,D1,D0);
input A,B,EN;
output D3,D2,D1,D0;
wire Abar,Bbar;
nandgate not1 (Abar,A,A,A);
nandgate not2 (Bbar,B,B,B);
nandgate nand0 (D0,Abar,Bbar,EN);
nandgate nand1 (D1,Abar,B,EN);
nandgate nand2 (D2,A,Bbar,EN);
nandgate nand3 (D3,A,B,EN);
endmodule
module nandgate (y,a,b,c);
input a,b,c;
output y;
assign y = ~(a&b&c);
endmodule
Testbench:
module test_dec24str;
reg test_A,test_B,test_EN;
wire test_D3,test_D2,test_D1,test_D0;
dec24str DUT (test_A,test_B,test_EN,test_D3,test_D2,test_D1,test_D0);
initial
begin
test_A =1'b0; test_B=1'b0;test_EN=1'b0;
#20 test_A =1'b0; test_B=1'b0;test_EN=1'b1;
#20 test_A = 0; test_B=1;
#20 test_A = 1; test_B=0;
#20 test_A = 1; test_B=1;
#20;
end
initial
begin
$monitor($time,"test_A:%b, test_B:%b,test_EN:%b, test_D3:%b,
test_D2:%b,test_D1:%b,test_D0:%b ",test_A,test_B,test_EN, test_D3,
test_D2,test_D1,test_D0);
$dumpfile("dec.vcd");
$dumpvars;
end
endmodule
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HDL Lab Manual 18ECL58
WAVEFORM OF 2 TO 4 DECODER:
UCF:
NET "EN" LOC = "p80";
NET "A" LOC = "p81";
NET "B" LOC = "p82";
NET "D<3>" LOC = "p93";
NET "D<2>" LOC = "p94";
NET "D<1>" LOC = "p95";
NET "D<0>" LOC = "p97";
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HDL Lab Manual 18ECL58
PROGRAM 1B(1): 8 TO 3 ENCODER (without priority)
Block diagram:
enable
8:3 ENCODER y(2:0)
d(7:0)
Truth Table:
enable d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) y(2) y(1) y(0)
0 X X X X X X X X 0 0 0
1 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 0 0 0 1
1 0 0 0 0 0 1 0 0 0 1 0
1 0 0 0 0 1 0 0 0 0 1 1
1 0 0 0 1 0 0 0 0 1 0 0
1 0 0 1 0 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 0 1 1 1
VERILOG SOURCE CODE:
module encoder83(d, enable, y);
input enable;
input [7:0] d;
output [2:0] y;
reg [2:0] y;
always @ (enable,d)
begin
if (!enable)
y = 3'b000;
else
case (d)
8'b00000001 : y = 3'b000;
8'b00000010 : y = 3'b001;
8'b00000100 : y = 3'b010;
8'b00001000 : y = 3'b011;
8'b00010000 : y = 3'b100;
8'b00100000 : y = 3'b101;
8'b01000000 : y = 3'b110;
8'b10000000 : y = 3'b111;
default: begin end
endcase
end
endmodule
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HDL Lab Manual 18ECL58
Testbench Code:
module TB_encoder83();
regtest_enable;
reg [7:0] test_d;
wire [2:0] test_y;
encoder83 dut (.enable(test_enable), .d(test_d), .y(test_y));
initial
begin
test_d = 8'b00000001;
#20 test_enable = 1'b0;
#20 test_enable = 1'b1;
#20 test_d = 8'b00000010;
#20 test_d = 8'b00000100;
#20 test_d = 8'b00001000;
#20 test_d = 8'b00010000;
#20 test_d = 8'b00100000;
#20 test_d = 8'b01000000;
#20 test_d = 8'b10000000;
#20;
end
initial
begin
$monitor($time, " test_enable:%b, test_d:%b, test_y:%b ", test_enable, test_d, test_y);
$dumpfile("dec1.vcd");
$dumpvars;
$dumpvars(1);
end
endmodule
WAVEFORM OF 8 TO 3 ENCODER :
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HDL Lab Manual 18ECL58
UCF:
NET "d<7>" LOC = "p80" ;
NET "d<6>" LOC = "p81" ;
NET "d<5>" LOC = "p82" ;
NET "d<4>" LOC = "p84" ;
NET "d<3>" LOC = "p83" ;
NET "d<2>" LOC = "p88" ;
NET "d<1>" LOC = "p85" ;
NET "d<0>" LOC = "p92" ;
NET "enable" LOC = "p114" ; FRC-3
NET "y<2>" LOC = "p93" ;
NET "y<1>" LOC = "p94" ;
NET "y<0>" LOC = "p95" ;
PROGRAM 1B(2): 8 TO 3 ENCODER (with priority)
Block diagram:
8:3
d(7:0) y(2:0)
Priority Encoder
VALID
Truth Table:
d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) y(2) y(1) y(0)
VALID
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 X 0 0 1 1
0 0 0 0 0 1 X X 0 1 0 1
0 0 0 0 1 X X X 0 1 1 1
0 0 0 1 X X X X 1 0 0 1
0 0 1 X X X X X 1 0 1 1
0 1 X X X X X X 1 1 0 1
1 X X X X X X X 1 1 1 1
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HDL Lab Manual 18ECL58
VERILOG SOURCE CODE:
module encoder83p (d , y, valid) ;
input [7:0] d ;
output [2:0] y ;
output valid ;
reg [2:0] y ;
reg valid ;
always @ (d)
begin
casex(d)
8'b1xxxxxxx : y = 3'd7;
8'b01xxxxxx : y = 3'd6;
8'b001xxxxx : y = 3'd5;
8'b0001xxxx : y = 3'd4;
8'b00001xxx : y = 3'd3;
8'b000001xx : y = 3'd2;
8'b0000001x : y = 3'd1;
8'b00000001 : y = 3'd0;
default: begin
end
endcase
if (d==8'b00000000)
valid=1'b0;
else
valid=1'b1;
end
endmodule
Testbench Code:
module TB_encoder83p();
reg [7:0] test_d;
wire [2:0] test_y;
encoder83p dut (.d(test_d), .y(test_y));
initial
begin
#20 test_d = 8'b11111111;
#20 test_d = 8'b01111111;
#20 test_d = 8'b00111111;
#20 test_d = 8'b00011111;
#20 test_d = 8'b00001111;
#20 test_d = 8'b00000111;
#20 test_d = 8'b00000011;
#20 test_d = 8'b00000001;
#20 test_d = 8'b00000000;
#20;
end
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HDL Lab Manual 18ECL58
initial
begin
$monitor($time, " test_d:%b, test_y:%b ", test_d, test_y);
$dumpfile("dec1.vcd");
$dumpvars;
//$dumpvars(1);
end
endmodule
WAVEFORM OF 8 TO 3 PRIORITY ENCODER:
UCF:
NET "d<7>" LOC = "p80";
NET "d<6>" LOC = "p81";
NET "d<5>" LOC = "p82";
NET "d<4>" LOC = "p84";
NET "d<3>" LOC = "p83";
NET "d<2>" LOC = "p88";
NET "d<1>" LOC = "p85";
NET "d<0>" LOC = "p92";
NET "y<2>" LOC = "p93";
NET "y<1>" LOC = "p94";
NET "y<0>" LOC = "p95";
NET "valid " LOC="P96";
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HDL Lab Manual 18ECL58
PROGRAM 1C: 8:1 MULTIPLEXER USING CASE STATEMENT
Block diagram:
din(7:0)
8:1 MULTIPLEXER
dout
sel(2:0)
Truth Table:
Selection Lines Input data Lines o/p
i/ps
sel(2) sel(1) sel(0) din(7) din(6) din(5) din(4) din(3) din(2) din(1) din(0) dout
0 0 0 X X X X X X X 0/1 din(0)
0 0 1 X X X X X X 0/1 X din(1)
0 1 0 X X X X X 0/1 X X din(2)
0 1 1 X X X X 0/1 X X X din(3)
1 0 0 X X X 0/1 X X X X din(4)
1 0 1 X X 0/1 X X X X X din(5)
1 1 0 X 0/1 X X X X X X din(6)
1 1 1 0/1 X X X X X X X din(7)
VERILOG SOURCE CODE:
module mux81(
input [7:0] din,
input[2:0] sel,
output dout);
reg dout;
always@(din , sel)
begin
case(sel)
3'b000 :dout = din[0];
3'b001 :dout = din[1];
3'b010 :dout = din[2];
3'b011 :dout = din[3];
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HDL Lab Manual 18ECL58
3'b100: dout = din[4];
3'b101 :dout = din[5];
3'b110 :dout = din[6];
3'b111 :dout = din[7];
default: begin
end
endcase
end
endmodule
Testbench Code:
module TB_mx81();
reg [7:0] test_din;
reg [2:0] test_sel;
wire test_dout;
mux81 DUT (test_din, test_sel, test_dout);
initial
begin
test_din =8'b10101010;
test_sel= 3'b000;
#10 test_sel= 3'b001;
#10 test_sel= 3'b010;
#10 test_sel= 3'b011;
#10 test_sel= 3'b100;
#10 test_sel= 3'b101;
#10 test_sel= 3'b110;
#10 test_sel= 3'b111;
#10;
end
initial
begin
$monitor($time," din = %b, sel= %b, dout= %b",
test_din,test_sel, test_dout);
$dumpfile("mux.vcd");
$dumpvars;
end
endmodule
WAVEFORM OF 8:1 MULTIPLEXER:
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HDL Lab Manual 18ECL58
PROGRAM 1C: 8:1 MULTIPLEXER USING IF STATEMENT
VERILOG SOURCE CODE:
module mux81(
input [7:0] din,
input[2:0] sel,
output dout);
reg dout;
always@(din, sel)
begin
if (sel == 3'b000)
dout = din[0];
else if (sel == 3'b001)
dout = din[1];
else if (sel == 3'b010)
dout = din[2];
else if (sel == 3'b011)
dout = din[3];
else if (sel == 3'b100)
dout = din[4];
else if (sel == 3'b101)
dout = din[5];
else if (sel == 3'b110)
dout = din[6];
else if (sel == 3'b111)
dout = din[7];
end
endmodule
Testbench Code:
module TB_mx81();
reg [7:0] test_din;
reg [2:0] test_sel;
wire test_dout;
mux81 DUT (test_din,test_sel,test_dout);
initial
begin
test_din =8'b11001100;
test_sel= 3'b000;
#10 test_sel= 3'b001;
#10 test_sel= 3'b010;
#10 test_sel= 3'b011;
#10 test_sel= 3'b100;
#10 test_sel= 3'b101;
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HDL Lab Manual 18ECL58
#10 test_sel= 3'b110;
#10 test_sel= 3'b111;
#10;
end
initial
begin
$monitor($time," din = %b, sel= %b, dout= %b",
test_din,test_sel, test_dout);
$dumpfile("mux.vcd");
$dumpvars;
end
endmodule
WAVEFORM OF 8:1 MULTIPLEXER:
UCF:
NET "din<7>" LOC = "p80";
NET "din<6>" LOC = "p81";
NET "din<5>" LOC = "p82";
NET "din<4>" LOC = "p84";
NET "din<3>" LOC = "p83";
NET "din<2>" LOC = "p88";
NET "din<1>" LOC = "p85";
NET "din<0>" LOC = "p92";
NET "SEL<2>" LOC = "p114”;
NET "SEL<1>" LOC = "p115";
NET "SEL<0>" LOC = "p134";
NET "dout" LOC = "p93" ;
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HDL Lab Manual 18ECL58
PROGRAM 1D: 4-BIT BINARY TO GRAY CONVERTER
Block diagram:
bin(3:0) 4-BIT BINARY TO GRAY gray (3:0)
CONVERTER
Truth Table:
4-bit Binary Numbers 4-bit Gray Numbers
bin(3) bin(2) bin(1) bin(0) gray(3) gray(2) gray(1) gray(0)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
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HDL Lab Manual 18ECL58
(a)Logic Diagram of 4-bit Binary-to-Gray Code converter using 1-bit Adder and Subtractor
circuit:
VERILOG SOURCE CODE:
Top-level Module:
Module bin_gray (B,G);
input [3:0] B ;
output [3:0] G ;
assign G[3] = B[3];
ha_hs h1 (B[3], B[2], G[2], , );
ha_hs h2 (B[2], B[1], G[1], , );
ha_hs h3 (B[1], B[0], G[0], , );
endmodule
Low level Module for Half Adder and Half Subtractor:
Module ha_hs (a, b, Sum_Diff, Cout, Bout);
input a ;
input b ;
output Sum_Diff;
output Cout, Bout;
assign Sum_Diff = a ^ b;
assign Cout = a & b;
assign Bout = (~a)& b;
endmodule
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HDL Lab Manual 18ECL58
Verilog Testbench for 4-bit Binary-to-Gray code Converter:
Module TB_bin_gray();
reg [3:0] test_B;
wire [3:0] test_G;
bin_graydut (.B(test_B), .G(test_G));
initial
begin
test_B = 4'b0000;
repeat (16) begin
#20test_B = test_B + 1;
end
end
initial
begin
$monitor($time, " B:%b, G:%b ", test_B, test_G);
$dumpfile("BG1.vcd");
$dumpvars;
end
endmodule
(b)4-bit Binary- to- Gray Code Converter using 1-bit Gray-to-Binary Code Converter
1-bit Gray-to-Binary Converter:
Verilog Source Code:
Top-level Module:
module bin_gray_1 (B,G);
input [3:0] B ;
output [3:0] G ;
assign G[3] = B[3];
one_bit_G_to_B GB1 (B[3], B[2], G[2]);
one_bit_G_to_B GB2 (B[2], B[1], G[1]);
one_bit_G_to_B GB3 (B[1], B[0], G[0]);
endmodule
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HDL Lab Manual 18ECL58
Low level Module for 1-Bit Gray-to-Binary Code Converter:
//1-Bit Gray-to-Binary Code Converter Module
Module one_bit_G_to_B (A, B, C);
input A ;
input B ;
output C;
assign C = A ^ B;
endmodule
Verilog Testbench for 4-bit Binary-to-Gray code Converter:
module TB_bin_gray_1();
reg [3:0] test_B;
wire [3:0] test_G;
bin_gray_1 dut (.B(test_B), .G(test_G));
initial
begin
test_B = 4'b0000;
repeat (16) begin
#20test_B = test_B + 1;
end
end
initial
begin
$monitor($time, " B:%b, G:%b ", test_B, test_G);
$dumpfile("BG1.vcd");
$dumpvars;
end
endmodule
WAVEFORM OF 4-BIT BINARY TO GRAY CONVERTOR:
UCF:
NET "bin<0>" LOC = "P80" ;
NET "bin<1>" LOC = "P81" ;
NET "bin<2>" LOC = "P82" ;
NET "bin<3>" LOC = "P84" ;
NET "gray<0>" LOC = "P93" ;
NET "gray<1>" LOC = "P94" ;
NET "gray<2>" LOC = "P95" ;
NET "gray<3>" LOC = "P97" ;
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HDL Lab Manual 18ECL58
PROGRAM 2A: Model in Verilog for a full adder and add functionality to perform logical
operations of XOR, XNOR, AND and OR gates. Write test bench with appropriate input
patterns to verify the modelled behaviour.
Block Diagram:
A Sum
B Full Adder
Cout
Cin
Truth Table:
Inputs Outputs
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Simplification Using K-Map
K-Map for Sum
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HDL Lab Manual 18ECL58
K-Map for Cout
Logical Expression for Sum:
Sum = A’ B’ Cin + A’ BCin’ + AB’Cin’ + A BCin
= Cin (A’ B’ + A B) + Cin’ (A’ B + AB’)
Sum =Cin (A XNOR B) + Cin’ (A XOR B)
Let y = A XOR B
Then y’ = A XNOR B
Sum = Cin y’ + Cin’y
Sum = Cin XOR y
Sum = Cin XOR A XOR B
Sum = A XOR B XOR Cin
Logical Expression for Cout:
Cout = AB + BCin + ACin
Source Code:
module fa_dataflow (A, B, Cin, Sum, Cout);
input A;
input B;
input Cin ;
output Sum ;
output Cout ;
wire s1,s2 ;
assign s1 = Cin& (~(x ^ y));
assign s2 = ~Cin& (x ^ y);
assign Sum = s1 | s2;
assign Sum = Cin& (~(A ^ B)) | ~Cin& (A ^ B);
assign Cout = (A & B) | (B &Cin) | (A&Cin) ;
endmodule
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HDL Lab Manual 18ECL58
Testbench Code:
moduleTB_fa_dataflow();
reg test_A;
reg test_B;
reg test_Cin;
wire test_Sum;
wire test_Cout;
fa_dataflow dut (.A(test_A), .B(test_B), .Cin(test_Cin), .Sum(test_Sum), .Cout(test_Cout));
initial
begin
test_A = 1'b0; test_B = 1'b0; test_Cin = 1'b0;
#20 test_A= 1'b0; test_B= 1'b0; test_Cin = 1'b1;
#20 test_A= 1'b0; test_B = 1'b1; test_Cin = 1'b0;
#20 test_A = 1'b0; test_B = 1'b1; test_Cin = 1'b1;
#20 test_A= 1'b1; test_B= 1'b0; test_Cin = 1'b0;
#20 test_A = 1'b1; test_B = 1'b0; test_Cin = 1'b1;
#20 test_A = 1'b1; test_B = 1'b1; test_Cin = 1'b0;
#20 test_A = 1'b1; test_B = 1'b1; test_Cin = 1'b1;
#20 ;
end
initial
begin
$monitor($time, " A:%b, B:%b, Cin:%b, Sum:%b, Cout:%b ", test_A, test_B, test_Cin,
test_Sum, test_Cout);
$dumpfile("fa.vcd");
$dumpvars;
end
endmodule
Waveforms:
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HDL Lab Manual 18ECL58
PROGRAM 4: 8-BIT ALU WITH ENABLE
Block diagram: A(31:0) B(31:0) Truth Table:
OPCODE ALU OPERATION
opcode(2:0) 1. A+B
2. A-B
3. A Complement
32- BIT 4. A*B
enable 5. A AND B
ALU 6. A OR B
7. A NAND B
8. A XOR B
Results(32:0)
VERILOG CODE (BEHAVIORAL MODEL):
module alu_32bit( enable, opcode ,A,B,Results,ack);
input enable;
input [2:0] opcode;
input [31:0] A,B;
output [32:0] Results;
output ack;
reg [32:0] Results;
reg ack;
always@ (A,B, enable, opcode)
begin
if (~enable) begin
Results =33'dz;
ack =1'b0;
end
else
case (opcode)
3'b000: begin Results = A + B; ack = 1'b1;end
3'b001: begin Results = A + (~ B)+1; ack = 1'b1;end
3'b010: begin Results = A +1; ack = 1'b1;end
3'b011: begin Results = A-1; ack = 1'b1;end
3'b100: begin Results = A;ack = 1'b1;end
3'b101: begin Results = ~A;ack = 1'b1;end
3'b110: begin Results = (A | B);ack = 1'b1;end
3'b111: begin Results = (A & B); ack = 1'b1;end
default :begin
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HDL Lab Manual 18ECL58
end
endcase
end
endmodule
TEST BENCH
module alu_TB;
reg enable;
reg [2:0] opcode;
reg [31:0] A,B;
wire[32:0] Results;
wire ack;
alu_32bit A1( .enable(enable),.opcode(opcode),.A(A),.B(B),.Results(Results),.ack(ack));
initial
begin
enable = 1'b0;
A=32'd3; B = 32'd2;
#10 enable = 1'b1;
#10 opcode= 3'b000;
#10 opcode = 3'b001;
#10 opcode = 3'b010;
#10 opcode = 3'b011;
#10 opcode = 3'b100;
#50 enable = 1'b0;
#10 enable = 1'b1;
#10 opcode = 3'b101;
#10 opcode = 3'b110;
#10 opcode = 3'b111;
#10;
end
initial
begin
$monitor($time, " enable:%b, opcode :%b, A:%b, B:%b, Results:%b, ack
:%b",enable,opcode,A,B,Results,ack);
$dumpfile("ALU.vcd");
$dumpvars;
end
endmodule
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HDL Lab Manual 18ECL58
WAVEFORM OF 8-BIT ALU:
UCF :
NET "enable" LOC = "p80";
NET "opcode<3>" LOC = "p81";
NET "opcode<2>" LOC = "p82";
NET "opcode<1>" LOC = "p84";
NET "opcode<0>" LOC = "p83";
NET "a<7>" LOC = "p93" ;
NET "a<6>" LOC = "p94" ;
NET "a<5>" LOC = "p95" ;
NET "a<4>" LOC = "p97" ;
NET "a<3>" LOC = "p98" ;
NET "a<2>" LOC = "p99" ;
NET "a<1>" LOC = "p100" ;
NET "a<0>" LOC = "p104" ;
NET "b<7>" LOC = "p114" ;
NET "b<6>" LOC = "p115" ;
NET "b<5>" LOC = "p134" ;
NET "b<4>" LOC = "p116" ;
NET "b<3>" LOC = "p118" ;
NET "b<2>" LOC = "p119" ;
NET "b<1>" LOC = "p120" ;
NET "b<0>" LOC = "p123" ;
NET "data_out<7>" LOC = "p121" ;
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HDL Lab Manual 18ECL58
NET "data_out<6>" LOC = "p124" ;
NET "data_out<5>" LOC = "p127" ;
NET "data_out<4>" LOC = "p126" ;
NET "data_out<3>" LOC = "p132" ;
NET "data_out<2>" LOC = "p140" ;
NET "data_out<1>" LOC = "p139" ;
NET "data_out<0>" LOC = "p143" ;
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HDL Lab Manual 18ECL58
CLOCK DIVISION PROGRAM
Generally Flip Flop and Counter outputs are seen using LED. But whenever a LED becomes
ON or OFF with a high frequency clock, human being can not visualize the change (ON and
OFF) by looking into it. Thus we need to reduce the frequency of clock. Use the following
clock division program for all the FLIP FLOPS and COUNTERS for implementing the
designs and download into FPGA kit.
Note : For simulation don’t include the clock division program in the Verilog source code
(Use on board 4 MHz clock only)
Verilog Clock Division Program:
• Declare the two SIGNALs nclk and div_reg inside a Verilog source code.
reg [20:0] div_reg;
wire nclk;
• Use the following block of verilog code to divide the clk.
always @ (posedge clk)
div_reg = div_reg + 1;
assign nclk = div_reg [20] ;
• Use the low frequency SIGNAL nclk in place of clk in the Verilog Source code
Note : Do simulation with clk.
Note : Do downloading(Implementation) with nclk.
PROGRAM 5A: SR FLIP FLOP
Block diagram:
s q
clk SR FLIP FLOP
r qb
o
reset
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Truth Table:
clk reset s r q qb Operation
X 0 X X 0 1 Active low asyn. reset
1 0 0 NC NC No Change state
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Invalid Invalid Indeterminate state
VERILOG SOURCE CODE:
module srff (input reset, clk, s, r , output q, qb);
reg q ;
always @ (negedge reset, posedge clk)
begin
if
(!reset) q
<= 1'b0;
else
begin
case ({s,r}) 2'b00 : q <= q;
2'b01 : q <= 1'b0; //FF-reset
2'b10 : q <= 1'b1; // FF-set
2'b11 : q <=1'bx ;
default : q<=1'bz ;
endcase
end
end
assign qb = ~q ;
endmodule
VERILOG TEST BENCH CODE:
module srff_test;
reg reset,clk,s,r;
wire q,qb;
srff UUT (.reset(reset),.clk(clk),.s(s),.r(r),.q(q),.qb(qb));
initial
begin
clk = 1'b0;
end
always # 5 clk = ~clk;
initial
begin
reset = 1'b0;
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#15 reset = 1'b1;s = 1'b0; r = 1'b0;
#10 s = 1'b0; r = 1'b1;
#10 s = 1'b1; r = 1'b0;
#10 s = 1'b1; r = 1'b1;
#10;
end
initial
begin
$monitor($time, "reset = %b, clk = %b, s=%b, r=%b,q = %b, qb = %b", reset, clk, s, r,q, qb);
$dumpfile("sr.vcd");
$dumpvars();
#60 $finish ;
end
endmodule
WAVEFORM OF SR- FLIP FLOP:
UCF:
NET "reset" LOC = "p80" ;
NET "s" LOC = "p81" ;
NET "r" LOC = "p82" ;
NET "clk" LOC = "p55" ;
NET "q" LOC = "p93" ;
NET "qb" LOC = "p94" ;
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PROGRAM 5B: D FLIP FLOP
Block diagram:
d q q
D Flip Flop
clk clk qb qb
reset
Truth Table:
clk reset d q qb operation
Active low asyn. reset
X 0 X 0 1
Data ‘0’ transferred
1 0 0 1
Data ‘1’ transferred
1 1 1 0
VERILOG SOURCE CODE:
module dff (input reset, clk , d, output q, qb) ;
reg q ;
always @ (negedge reset , posedge clk)
begin
if(!reset)
q <= 1'b0 ;
else
q <= d ;
end
assign qb =~ q ;
endmodule
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DFF Test Bench
module dff_test;
reg reset,clk,d;
wire q,qb;
dff UUT (.reset(reset),.clk(clk),.d(d),.q(q),.qb(qb));
initial
begin
clk = 1'b0;
end
always # 5 clk = ~clk;
initial
begin
reset = 1'b0;
#10 reset = 1'b1;d = 1'b0;
#10 d = 1'b1;
#10 d = 1'b0;
#10;
end
initial
begin
$monitor($time, "reset = %b, clk = %b, d=%b,q = %b, qb = %b", reset, clk, d, q, qb);
$dumpfile("d.vcd");
$dumpvars();
#45 $finish ;
end
endmodule
WAVEFORM OF D- FLIP FLOP:
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UCF:
NET "reset" LOC = "p80";
NET "d" LOC = "p81";
NET "clk" LOC = "p55";
NET "q" LOC = "p93";
NET "qb" LOC = "p94";
PROGRAM 5C: JK FLIP FLOP
Block diagram:
j q
clk JK Flip Flop
k qb
o
reset
Truth Table:
clk reset j k q qb operation
X 0 X X 0 1 Active low asyn. reset
1 0 0 NC NC No Change state
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 qb q Toggle
VERILOG SOURCE CODE:
module jkff(
input reset, clk, j, k, output q, qb);
reg q;
always @ (negedge reset, posedge clk) begin
if (!reset)
q <= 1'b0;
else
begin case ({j,k})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~ q; default: q <= 1'bz; endcase
end end
assign qb = ~ q;
endmodule
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JK FF Test Bench
module jkff_test;
reg reset,clk,j,k;
wire q,qb;
jkff UUT (.reset(reset),.clk(clk),.j(j),.k(k),.q(q),.qb(qb));
initial
begin
clk = 1'b0;
end
always # 5 clk = ~clk;
initial
begin
reset = 1'b0;
#15 reset = 1'b1;j = 1'b0; k = 1'b0;
#10 j = 1'b0; k = 1'b1;
#10 j = 1'b1; k = 1'b0;
#10 j = 1'b1; k = 1'b1;
#10 j = 1'b1; k = 1'b1;
#10 j = 1'b1; k = 1'b1;
#10 j = 1'b1; k = 1'b1;
#10;
end
initial
begin
$monitor($time, "reset = %b, clk = %b, j=%b, k=%b,q = %b, qb = %b", reset, clk, j, k,q, qb);
$dumpfile("jk.vcd");
$dumpvars();
#100 $finish ;
end
endmodule
WAVEFORM OF JK- FLIP FLOP:
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UCF:
NET "reset" LOC = "p80";
NET "j" LOC = "p81";
NET "k" LOC = "p82";
NET "clk" LOC = "p55";
NET "q" LOC = "p93";
NET "qb" LOC = "p94";
PROGRAM 6A: 4-bit BCD synchronous counter
VERILOG SOURCE CODE:
module bcd_syn_counter(
input reset, clk ,
output [3:0] q );
reg [3:0] q ;
always @ (negedge reset or posedgeclk)
begin
if(!reset)
q<=4'b0000 ;
else
begin
q<=q+1 ;
if (q == 4'b1001) //checking the condition
q<=4'b0000 ;
end
end
endmodule
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Test Bench for BCD counter:
moduletb_bcd;
reg reset;
regclk =1'b0;
wire [3:0] q;
bcd_syn_counter DUT (reset,clk,q);
always #5 clk = ~ clk ;
initial
begin
reset = 1'b0;
#15 reset =1'b1;
#200 $finish;
end
initial
begin
$monitor($time,"reset=%b,clk=%b,q = %b",reset,clk,q);
$dumpfile("bcd.vcd");
$dumpvars();
end
endmodule
WAVEFORM FOR BCD COUNTER:
UCF:
NET "reset" LOC = "p80";
NET "clk" LOC = "p55";
NET "q<3>" LOC = "p93";
NET "q<2>" LOC = "p94";
NET "q<1>" LOC = "p95";
NET "q<0>" LOC = "p97";
Note : Use same UCF for all counters.
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Program 8: Write Verilog code for counter with given input clock and check whether it works
as clock divider performing division of clock by 2, 4, 8 and 16. Verify the functionality of the
code.
module binary_counter( input reset, clk, output div_2, div_4, div_8, div_16);
reg [3:0] q;
always @ (posedgeclk) begin
if(!reset) q<=4'b0000;
else q<=q+1;
end
assign div_2 = q[0];
assign div_4 = q[1];
assign div_8 = q[2];
assign div_16 = q[3];
endmodule
Test_Bench
module tb_bcd;
reg reset;
reg clk =1'b0;
wire div_2, div_4, div_8, div_16;
binary_counter DUT (reset,clk,div_2, div_4, div_8, div_16);
always #5 clk = ~ clk ;
initial
begin
reset = 1'b0;
#15 reset =1'b1;
#200 $finish;
end
initial
begin
$monitor($time,"reset=%b,clk=%b,div_2 = %b, div_4 = %b, div_8 = %b, div_16 =
%b",reset,clk,div_2, div_4, div_8,div_16);
$dumpfile("cdiv.vcd");
$dumpvars();
end
endmodule
WAVEFORMS
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