POLITECNICO DI TORINO

Corso di Laurea Magistrale in Ingegneria Elettronica

Tesi di Laurea Magistrale

Design, Simulation and

Prototyping of a 20kW
Three-Phase Inverter for
heavy-duty applications

Relatore Candidato
Prof. Francesco Musolino Gabriele Castellini
matricola: 253679

Supervisore Aziendale
Dott. Ing. Luca Vola Gera

Anno Accademico 2018-2019

Abstract
This thesis concerns the design of a three-phase Voltage Source Inverter for future
applications inside heavy-duty vehicles. In particular, all the preliminary aspects
that are needed to be considered for a prototype fabrication will be discussed,
including: selection of the components, development, design, simulation, circuit
schematic and PCB implementation of an evaluation board; the purpose of this
prototype is to verify that the hardware implemented is suitable for an application
with a DC bus voltage of 700V and a maximum power of 20kW.
The first step of the project deals with the development of a model which is
capable to simulate and evaluate the main parameters of the inverter behaviour in
different working conditions, in order to obtain a method to compare power elec-
tronics components and modulation techniques from the point of view of achievable
efficiency and performances. This model is developed using few hardware resources
with the aim to run a fast and efficient simulation; furthermore, the validity of the
data obtained by implementing this model in MATLAB/SIMULINK environment
is checked by a comparison with the results given from some simulators available on
different semiconductor manufacturer websites. Once the components have been
chosen, the design of the different inverter parts and a first evaluation of the physical
dimensions of the system has be done.
The main step in order to evaluate the real performances of the system is the
schematic and PCB design; it is carried out taking into account the flexibility, the
development time and the maintenance easiness, that are characteristics needed to
build an evaluation board of the system.
This Thesis discusses the introductory studies carried out in the framework of
a long-term task commissioned to Flag-MS company, which is an innovative small
and medium-sized enterprise hosted by the Innovative Enterprise Incubator (I3P)
of the Politecnico di Torino and is a member of MESAP, the Innovation Cluster for
Smart Products and Manufacturing.

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Acknowledgements
At the end of my studies there are so many people that I would like to thanks, I
apologize if I forget someone.
The first due thanks go to my parents for the sacrifices and patience spent in
these years, to my brother as continuous source of inspiration and security, and to
all my family members which have always believed in me.
A special thanks to all the guys of the FLAG-MS for the friendly and cordial
work environment in which they welcomed me, especially my tutor Luca Vola Gera
who guides me in this project. Thanks also to Professor Francesco Musolino for
the time and kindness spent to follow the thesis work.
Last but not the least, thanks to all my closest friends: they bear me even if I’m
always right.

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Contents

List of Tables vi

List of Figures vii

1 Introduction 1
1.1 The heavy-duty sector . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Overview of electrified powertrains . . . . . . . . . . . . . . . . . . 3
1.3 Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Inverter 7
2.1 Three-phase two-level Voltage Source Inverter . . . . . . . . . . . . 9
2.2 Modulation techniques . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Sinusoidal PWM (SPWM) . . . . . . . . . . . . . . . . . . . 11
2.2.2 Square wave modulation . . . . . . . . . . . . . . . . . . . . 13
2.2.3 Third harmonic injection . . . . . . . . . . . . . . . . . . . . 15
2.2.4 Space-Vector modulation (SV PWM) . . . . . . . . . . . . . 16

3 Evaluation of power losses 23

3.1 MATLAB/SIMULINK model . . . . . . . . . . . . . . . . . . . . . 24
3.1.1 Sinusoidal PWM . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.2 Space-Vector PWM . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Simulation and calculation of losses . . . . . . . . . . . . . . . . . . 34

4 Analysis of the DC-link Current 47

4.1 Calculation of DC and AC components of the DC-Link Current . . 47
4.2 Selection of the DC-link capacitor . . . . . . . . . . . . . . . . . . . 52
4.3 Overview of alternative harmonic filtering solutions . . . . . . . . . 61

5 Design of the inverter 65

5.1 Selection of the electronics components . . . . . . . . . . . . . . . . 65
5.2 Sizing of the components . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3 Estimation of the efficiency . . . . . . . . . . . . . . . . . . . . . . . 81
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6 Prototype 83
6.1 Design of the Printed Circuit Board . . . . . . . . . . . . . . . . . . 84
6.1.1 Electric schematic . . . . . . . . . . . . . . . . . . . . . . . . 84
6.1.2 Layout of the PCB . . . . . . . . . . . . . . . . . . . . . . . 88
6.2 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7 Conclusions and future works 109

A MATLAB codes 111

A.1 Scripts for inverter model simulation . . . . . . . . . . . . . . . . . 111
A.1.1 Sinusoidal PWM . . . . . . . . . . . . . . . . . . . . . . . . 111
A.1.2 Space-Vector PWM . . . . . . . . . . . . . . . . . . . . . . . 111
A.2 Script for losses evaluation . . . . . . . . . . . . . . . . . . . . . . . 112
A.2.1 IGBT losses . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
A.2.2 MOSFET losses . . . . . . . . . . . . . . . . . . . . . . . . . 115
A.3 Scripts for capacitance evaluation . . . . . . . . . . . . . . . . . . . 116

B SIMULINK models 119

B.1 Inverter with IGBT and Sinusoidal PWM . . . . . . . . . . . . . . 119
B.2 Inverter with IGBT and Space-Vector PWM . . . . . . . . . . . . . 125
B.3 Inverter with power MOSFET and Sinusoidal PWM . . . . . . . . . 128
B.4 Inverter with power MOSFET and Space-Vector PWM . . . . . . . 131

C Electric schematic of the prototype 133

C.1 Flyback power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 133
C.2 Blocks of the gate driver board . . . . . . . . . . . . . . . . . . . . 134
C.3 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
C.4 12V-to-5V buck converter . . . . . . . . . . . . . . . . . . . . . . . 136
C.5 Current sense amplifier and LDO . . . . . . . . . . . . . . . . . . . 137

Bibliography 139

v
List of Tables
2.1 The eight switch states in a three-phase VSI with the corresponding
space vector of each line voltage combination. . . . . . . . . . . . . 18
3.1 Specifications for the Inverter. . . . . . . . . . . . . . . . . . . . . . 24
3.2 Phase leg reference voltages of Space-Vector PWM. . . . . . . . . . 31
3.3 MOSFETs and IGBTs suitable for the application of this project. . 35
3.4 Parameter values for losses simulation. . . . . . . . . . . . . . . . . 40
3.5 Average power losses for the switches of Table 3.3. . . . . . . . . . . 43
3.6 SemiSel simulation results. . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 Parameter values for the evaluation of the DC-link current spectrum. 57
4.2 Constraints for the selection of DC-link capacitors. . . . . . . . . . 60
5.1 Wurth Elektronik 750343953 characteristics. . . . . . . . . . . . . . 75
6.1 BOM of the flyback board. . . . . . . . . . . . . . . . . . . . . . . . 87
6.2 BOM of the gate driver board. . . . . . . . . . . . . . . . . . . . . . 88

vi
List of Figures
1.1 Deloitte Global Automotive Consumer Study: comparison of inter-
ested consumers in an electrified powertrain between 2018 and 2019.
[49] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 In-depth view of a Mercedes-Benz eActors heavy-duty electric truck. 2
1.3 Battery Electric Vehicle configuration. [54] . . . . . . . . . . . . . . 4
2.1 Wye-connected balanced load (Z1 = Z2 = Z3 ). A, B and C are called
"line" while N is called "neutral". [6] . . . . . . . . . . . . . . . . . 8
2.2 3-phase Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 PWM modulator. [42] . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Waveforms in a SPWM 3-phase 2-level VSI with delta-load connec-
tion: (a) carrier and modulating signals; (b) phase voltage between
phase A and neutral; (c) phase voltage between phase B and neutral;
(d) AC line voltage between phase A and phase B. [42] . . . . . . . 12
2.5 Harmonics h of the fundamental in a three-phase SPWM inverter
with ma = 0.8 and mf = 15. [42] . . . . . . . . . . . . . . . . . . . 13
2.6 Fundamental AC output component of the line voltage in a VSI
SPWM inverter. [48] . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7 Square wave inverter output waveforms: the three phase voltages
vAN , vBN , vCN and one of the line voltages vAB . [42] . . . . . . . . 14
2.8 Control signal in a third harmonic injection inverter. [42] . . . . . . 16
2.9 Relationship between abc reference system and stationary αβ system.
[42] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10 Space vector representation in the αβ complex plane. [48] . . . . . 19
2.11 Modulating vector construction. [27] . . . . . . . . . . . . . . . . . 20
2.12 SV PWM symmetric switching pattern for Sector 1. [27] . . . . . . 21
3.1 Three-Phase Dynamic Load simulation parameters. . . . . . . . . . 25
3.2 PWM control waveform of Sinusoidal modulation with ftr = 15kHz
and fCT RL = 1kHz. On the y-axis the time is expressed in second [s]. 26
3.3 Switched current of IGBT M 5 with ftr = 15kHz, fCT RL = 1kHz and
Sinusoidal PWM. On the y-axis the time is expressed in seconds [s],
while on the x-axis the current is expressed in Ampere [A]. . . . . . 26
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3.4 Line voltage vLL with ftr = 15kHz, fCT RL = kHz and Sinusoidal
PWM. On the y-axis the time is expressed in seconds [s], while on
the x-axis the voltage is expressed in Volt [V]. . . . . . . . . . . . . 27
3.5 Sinusoidal references signals, each one with a phase shift of 120◦ . On
the y-axis the time is expressed in seconds [s], while on the x-axis
the voltage is expressed in Volt [V]. . . . . . . . . . . . . . . . . . . 28
3.6 Switched current of power MOSFET M 5 with ftr = 15kHz, fCT RL =
1kHz and Sinusoidal PWM. On the y-axis the time is expressed in
seconds [s], while on the x-axis the current is expressed in Ampere [A]. 29
3.7 Phase voltage vLN with ftr = 15kHz, fCT RL = 1kHz and Sinusoidal
PWM. On the y-axis the time is expressed in seconds [s], while on
the x-axis the voltage is expressed in Volt [V]. . . . . . . . . . . . . 29
3.8 Phase leg references signals for leg A (signal U), leg B (signal V) and
leg C (signal W). On the y-axis the time is expressed in seconds [s]. 31
3.9 PWM control waveform of Space-Vector technique with ftr = 15kHz
and fCT RL = 1kHz. On the y-axis the time is expressed in second [s]. 32
3.10 Switched current of IGBT M 5 with ftr = 15kHz, fCT RL = 1kHz and
Space-Vector PWM. On the y-axis the time is expressed in seconds
[s], while on the x-axis the current is expressed in Ampere [A]. . . . 32
3.11 Line voltage vLL with ftr = 15kHz, fCT RL = 1kHz and Space-Vector
PWM. On the y-axis the time is expressed in seconds [s], while on
the x-axis the voltage is expressed in Volt [V]. . . . . . . . . . . . . 33
3.12 Switched current of power MOSFET M 5 with ftr = 15kHz, fCT RL =
1kHz and Space-Vector PWM. On the y-axis the time is expressed
in seconds [s], while on the x-axis the current is expressed in Ampere
[A]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.13 Output current of the three-phase VSI with ftr = 15kHz, fCT RL =
1kHz and Space-Vector PWM. On the y-axis the time is expressed
in seconds [s], while on the x-axis the current is expressed in Ampere
[A]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.14 Screenshot of the GUI of Grabit while grabbing points. . . . . . . . 36
3.15 One period of the transistor M 5 current used to calculate losses. . . 39
3.16 Current amplitude values during the transitions. . . . . . . . . . . . 40
3.17 Instantaneous conduction losses of Semikron SK100GD12T4T. . . . 41
3.18 Instantaneous switching losses of Semikron SK100GD12T4T. . . . . 41
3.19 Energy losses of Semikron SK100GD12T4T with respect of the collector-
emitter current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.20 SemiSel simulation results for the SEMiX101GD12Vs. . . . . . . . . 44
3.21 Instantaneous conduction losses of Cree CCS050M12CM2 with Sace-
Vector PWM. On the left MOSFET conduction losses, on the right
body-diode conduction losses. . . . . . . . . . . . . . . . . . . . . . 45
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3.22 Instantaneous switching losses of Cree CCS050M12CM2 with Sace-
Vector PWM. Turn-on losses in blu, turn-off losses in black, recovery
losses in red. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.23 Total power losses in function of increasing switching frequency and
with different PWM strategies. . . . . . . . . . . . . . . . . . . . . 46
4.1 Construction of the DC-link current by means of switching func-
tions: (a)(i) inverter leg voltage, (a)(ii)fundamental component of leg
voltage, (a)(iii)sinusoidal current; (b) switching function; (c),(d),(e)
DC-link current of the three legs; (f) total DC-link current. [16] . . 49
4.2 Example of switching function construction for leg A. . . . . . . . . 50
4.3 DC-link current of leg A. . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4 DC-link current of the three legs. . . . . . . . . . . . . . . . . . . . 51
4.5 Total theoretical DC-link current of the inverter with fSW = 20kHz
and fout = 50Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6 Variations of ripple component of the DC-link current with respect
to ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.7 Variations of ripple component of the DC-link current with respect
to cos (φ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.8 Simulation results of the SIMULINK model for different power factor
cos (φ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.9 Simulation results of the SIMULINK model for different modulation
index ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.10 DC-link current waveform of the three-phase VSI under RMS worst-
case conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.11 Spectrum of the three-phase VSI DC-link current under RMS worst-
case conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.12 Capacitance value versus the DC-link voltage ripple. . . . . . . . . . 59
4.13 ESR value versus the DC-link voltage ripple. . . . . . . . . . . . . . 59
4.14 DC-link voltage versus the capacitance value. . . . . . . . . . . . . 60
4.15 PRDCL soft switching inverter. [44] . . . . . . . . . . . . . . . . . . 62
4.16 Modulating vector construction: on the left the classic SV PWM
approach, on the right the EDC PWM approach. [45] . . . . . . . . 63
4.17 Variation of inverter input current during a switching period for SV
PWM and EDC PWM. [45] . . . . . . . . . . . . . . . . . . . . . . 63
5.1 Pin configuration of the ISO5452-Q1. . . . . . . . . . . . . . . . . . 66
5.2 Modes of operation for the LM5180-Q1. . . . . . . . . . . . . . . . . 68
5.3 Protection of DESAT pin with a resistor RS and a Schottky Diode. 71
5.4 Typical output characteristics of the Cree/Wolfspeed CCS050M12CM2
for TJ = 25◦ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5 Typical gate charge characteristics of the Cree/Wolfspeed CCS050M12CM2. 73
5.6 Schematic of the power supply circuit. [52] . . . . . . . . . . . . . . 74
5.7 Programmable input voltage UVLO with hysteresis of the LM5180-Q1. 75
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5.8 RC filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.9 Schematic of the LM46002-Q1. . . . . . . . . . . . . . . . . . . . . . 79
5.10 Maximum power dissipation for the MOSFETs of the Cree/Wolf-
speed CCS050M12CM2 with respect case temperature. . . . . . . . 82
6.1 Creepage distances to avoid failure due to tracking. [25] . . . . . . . 89
6.2 Layout of the top side of the flyback board. . . . . . . . . . . . . . 90
6.3 Top side of the flyback PCB. . . . . . . . . . . . . . . . . . . . . . . 90
6.4 Layout of the bottom side of the flyback board. . . . . . . . . . . . 91
6.5 Bottom side of the flyback PCB. . . . . . . . . . . . . . . . . . . . . 91
6.6 Layout of the top side of the gate driving board. . . . . . . . . . . . 92
6.7 Top side of the gate driving PCB. . . . . . . . . . . . . . . . . . . . 92
6.8 Layout of the bottom side of the gate driving board. . . . . . . . . 93
6.9 Bottom side of the gate driving PCB. . . . . . . . . . . . . . . . . . 93
6.10 Output voltage of the flyback converter with a zoom of its ripple. . 96
6.11 Output voltage of the flyback converter with an input voltage of 9V. 96
6.12 Output voltage of the flyback converter with an input voltage of 24V. 97
6.13 The 15V and -5V voltages supplied by the flyback. . . . . . . . . . 97
6.14 Pin SW with respect ground when the nominal voltage is applied. . 98
6.15 Pin SW with respect ground when the minimum voltage is applied. 98
6.16 Pin SW with respect ground when the maximum voltage is applied. 99
6.17 Example of an InSight GUI. . . . . . . . . . . . . . . . . . . . . . . 100
6.18 Example of the gate drivers controlled by PWM. . . . . . . . . . . . 100
6.19 Gate of the low-side transistor (red wave) and phase voltage (yellow
wave). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.20 Experimental test setup. . . . . . . . . . . . . . . . . . . . . . . . . 101
6.21 Prototype connected to a DC-bus of 100V and driven with two pulses
of 20µs distanced by 50µs. The waveform reported are: gate of the
low-side transistor (yellow), phase voltage (blue), output current (red).102
6.22 Prototype connected to a DC-bus of 200V and driven with two pulses
of 10µs distanced by 50µs. The waveform reported are: gate of the
low-side transistor (yellow), phase voltage (blue), output current (red).102
6.23 Prototype connected to a DC-bus of 200V and driven with two pulses
of 10µs distanced by 50µs. Zoom of the start-up with zero output
current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.24 Prototype connected to a DC-bus of 200V and driven with two pulses
of 10µs distanced by 50µs. Zoom of the start-up with output current
different from zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.25 Prototype connected to a DC-bus of 550V and driven with one pulse
of 0.5µs. The waveform reported are: gate of the low-side transistor
(yellow), phase voltage (blue), output current (red). . . . . . . . . . 104
x
6.26 Prototype connected to a DC-bus of 550V and driven with one pulse
of 0with two pulses of 0.5µs distanced by 6µs. Zoom of the start-up
with output current different from zero. . . . . . . . . . . . . . . . . 104
6.27 Prototype connected to a DC-bus of 350V and driven with two pulses
of 0.5µs distanced by 6µs. The waveform reported are: gate of the
low-side transistor (yellow), gate of the high-side transistor (blue),
output current (red). . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.28 Prototype connected to a DC-bus of 350V and driven with two pulses
of 0.5µs distanced by 6µs. Zoom of the waveforms. . . . . . . . . . . 105
6.29 Prototype connected to a DC-bus of 400V and driven with two pulses
of 0.5µs distanced by 6µs. The waveform reported are: gate of the
low-side transistor (yellow), gate of the high-side transistor (blue),
output current (red). . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.30 Prototype connected to a DC-bus of 500V and driven with two pulses
of 0.5µs distanced by 6µs. The waveform reported are: gate of the
low-side transistor (yellow), gate of the high-side transistor (blue),
output current (red). . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.31 Prototype connected to a DC-bus of 200V. The waveform reported
are: gate of the low-side transistor (yellow), DESAT pin (green),
output current (red). . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.32 Prototype connected to a DC-bus of 550V. The waveform reported
are: gate of the low-side transistor (yellow), DESAT pin (blue), out-
put current (red). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.33 Prototype connected to a DC-bus of 250V. The output current is
reported in red, while the vltage across the shunt is reported in yellow.108
B.1 First section of the SIMULINK model for the evaluation of IGBT
losses with Sinusoidal PWM. . . . . . . . . . . . . . . . . . . . . . . 119
B.2 Second section of the SIMULINK model for the evaluation of IGBT
losses with Sinusoidal PWM. . . . . . . . . . . . . . . . . . . . . . . 120
B.3 Subsystem "INVERTER" (Figure B.2) of the three-phase inverter
with IGBT transistors. . . . . . . . . . . . . . . . . . . . . . . . . . 121
B.4 Subsystem "MEASUREMENT" (Figure B.2) for the evaluation of
phase and line voltages. . . . . . . . . . . . . . . . . . . . . . . . . 122
B.5 Subsystem "S PWM" (Figure B.1) for the generation of the Sinu-
soidal PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
B.6 First section of the SIMULINK model for the evaluation of IGBT
losses with Space-Vector PWM. . . . . . . . . . . . . . . . . . . . . 125
B.7 Second section of the SIMULINK model for the evaluation of IGBT
losses with Space-Vector PWM. . . . . . . . . . . . . . . . . . . . . 126
B.8 Subsystem "SV PWM" (Figure B.6) for the generation of the Space-
Vector PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
xi
B.9 First section of the SIMULINK model for the evaluation of power
MOSFET losses with Sinusoidal PWM. . . . . . . . . . . . . . . . . 128
B.10 Second section of the SIMULINK model for the evaluation of power
MOSFET losses with Sinusoidal PWM. . . . . . . . . . . . . . . . . 129
B.11 Subsystem "INVERTER" (Figure B.10) of the three-phase inverter
with power MOSFET transistors. . . . . . . . . . . . . . . . . . . . 130
B.12 First section of the SIMULINK model for the evaluation of power
MOSFET losses with Space-Vector PWM. . . . . . . . . . . . . . . 131
B.13 Second section of the SIMULINK model for the evaluation of power
MOSFET losses with Space-Vector PWM. . . . . . . . . . . . . . . 132

xii
Chapter 1

Introduction
In the last decades the energy demand has considerably increased and fossil fuel
sources, the main energy source, have become a risk for human health due to the
adverse effects of CO2 emissions in the environment, and, in 2009, it was detected
that the 29% of these greenhouse gas emissions was produced by the transportation
sector [62]. This pollution figure could be reduced with a progressive penetration
of electric vehicles in the transportation sector; thus, both the industrial and auto-
motive world started to invest resources in the electric energy source, leading to an
ongoing improvement of the power electronics field because the appeal of an electric
vehicle is intensifying globally, with more consumers attracted by a vehicle with an
electric powertrain (Figure 1.1). Moreover, observing the research development and
investments trend, it can be noticed that the request for new and improved power
converters will grow further in the next years. The challenge will be to find the
best trade-off: on one hand the market will ask for power converter systems with
higher efficiency, higher reliability and functionality, on the other one it will ask for
lower costs, weight, volume and development time [32].

Figure 1.1. Deloitte Global Automotive Consumer Study: comparison of inter-

ested consumers in an electrified powertrain between 2018 and 2019. [49]

1
 1 – Introduction

1.1 The heavy-duty sector

Riding the wave of this electrification trend, different OEMs (Original Equipment
Manufacturers) are directing their efforts to realize modern and avant-garde Heavy-
Duty Vehicles (HDVs), in order to replace the classic fuel powertrain with a modern
electrified one. The word HDV means a vehicle designed for heavy work but with
different uses and drive cycles: it can refer to a freight vehicle of more than 3.5
Tonnes (such as trucks) or passenger transport vehicles with more than eight seats
(buses and coaches). Even if the HDV fleet is very heterogeneous, most of them have
in common the engine typology: they are powered by diesel engines that emit high
levels of particulates, nitrogen oxides, and other pollutants. This is the reason why
both the European Union and the United States are redacting new HDV emission
standards [50], and the only suitable alternative to diesel powertrains for this type
of vehicles is an electric powertrain, due to their high torque demand at wheels and
controllability requirements [34].

Figure 1.2. In-depth view of a Mercedes-Benz eActors heavy-duty electric truck.

From the situation described above it is clear that the heavy-duty sector is very
sizzling: from the first to the third of July of 2019, the IQPC’s Powertrain Electri-
fication Conference for medium and heavy-duty vehicles has been held in Berlin.
Companies are looking for more capable power units with fewer production costs
and the biggest OEMs are trying to overcome as fast as possible the technological
obstacles of this segment: high impact on grid power quality, high energy cells,
highly efficient systems to increase the range and higher cooling power [53]. The
battery voltage range for heavy-duty application is of 600V-700V, whereas the elec-
tric cars available in the market have batteries of around 300V. Another issue for
2
 1.2 – Overview of electrified powertrains

this sector is the technological growth rate because it does not allow for the reduc-
tion of power components level costs; the situation is the opposite for high voltage
battery: cost reduction in kWh is more visible than power components such as
inverter, motor and high voltage auxiliary components. Instead, with power rating
lower than 2kW, assembly costs, cable and electrical connectors are the main con-
tributors of costs [33]. The use of DC input voltages above 600V is not an arbitrary
choice and it is becoming a standard also in electric cars, proof of this is the new
and powerful Porsche Taycan with a DC-bus voltage of 800V. Using higher voltages,
the amount of current required to achieve a given power level is reduced and this
allows for thinner and lighter cables inside the vehicle, thinner and lighter cables
on the fast recharging stations and the motor will sink less current producing less
heat. Thus, thanks to the higher voltage level, a smaller and cooler high efficient
system can be manufactured.
Figure 1.2 shows one of the few available full-electric heavy-duty vehicle: it is the
power distribution configuration of a Mercedes-Benz eActors, and it has recently
been adopted by the Dachser company for daily journeys of about 80km.

1.2 Overview of electrified powertrains

Electric vehicles can run on solely electric propulsion or they can have an internal
combustion engine working alongside, hence they can be categorized as follows [54]:
• Battery Electric Vehicle (BEV);
• Hybrid Electric Vehicle (HEV);
• Plug-in Hybrid Electric Vehicle (PHEV);
• Fuel Cell Electric Vehicle (FCEV);

HEVs are implemented with two or more types of energy source, storage or convert-
ers with at least one of those used to provide electrical energy. However, the goal
for the heavy-duty sector is the fabrication of BEV with only batteries to provide
power to the drive train but capable to combine acceptable costs and long-range
capability. The general powertrain scheme of a Battery Electric Vehicle is reported
in Figure 1.3 where the main topic of this Thesis is visible: the inverter.
A power inverter is the most important component for controlling the electric
motor, because the DC power coming from a battery pack must be converted into
the most suitable AC voltages and currents. Focused about this aspect, the project
presented in the next pages is developed with the purpose to obtain an efficient,
small and cheap motor driver.

3
 1 – Introduction

Figure 1.3. Battery Electric Vehicle configuration. [54]

1.3 Thesis organization

The primary aim of this work is to fabricate a prototype of a three-phase voltage
source inverter for heavy-duty application fed by a DC bus of 700V and it will
stand with a maximum power of 20kW; due to the lack of information at this very
beginning stage of the task about the topology of the electric motor that will be
implemented in the final application, the Thesis describes the design of a general-
purpose AC electric drive. This choice makes possible to define a procedure by
which most of the design issues of the inverter can be studied and tackled, increasing
the technical competences in this specific sector while letting for future works the
integration of this inverter with the electric motor. As for the automotive world,
a stand-alone isolated power converter is needed because, unlike a grid-connected
system, the generation of power is close to the demand centre. In Chapter 2 the
basic background needed in order to develop the project are illustrated.
Considering the biggest challenges of the heavy-duty sector, the main trade-off
taken into account during the design is the one between cost and efficiency but, at
the same time, keeping the volume the smallest as possible. Thus, looking for a
highly power density and highly efficient converter, the semiconductor state-of-the-
art transistors, Gallium Nitride (GaN) MOSFET, should be implemented. They
are the latest in technology but they have had slow adoption due to cost, yield
and reliability concerns [5]. GaN transistors can reach higher switching frequencies
compared with Silicon Carbide (SiC) or Silicon (Si) thanks to its higher electron
mobility. Their negative aspect consist in their low thermal conductivity, that leads
to a fewer power density potential. Furthermore, while the blocking voltages of GaN
MOSFETs is limited to around 650V, SiC devices are well suited for applications
from around 650V through 1.2kV (and higher) thanks also to their lower cost and
robustness, given by the greater maturity of the technology. The best choice for
the specific application of this Thesis is SiC technology because, on the contrary of
4
 1.3 – Thesis organization

Silicon, it is a wide band gap semiconductor: higher breakdown voltage compared

with Si of the same scale, lower on state resistance and higher thermal conductivity
[36].
SiC semiconductors combined with a 700V DC-bus voltage respond to the differ-
ent needs of the heavy-duty sector because high power density combined with high
frequency are essential features for lower overall cost, weight and cooling require-
ments. Since there are different types of SiC MOSFETs available on the market,
a preliminary analysis of their performances, costs and dimension is necessary. In
order to allow a better and faster choice and in order to verify the actual improve-
ment of SiC MOSFETs with respect Si MOSFETs or IGBTs, the starting point of
this Thesis is the creation of a MATLAB/SIMULINK model: it simulates a typi-
cal three-phase inverter application and allows to evaluate the power dissipation of
the switches in different operating conditions and with different modulation tech-
niques. The behaviour of a three-phase inverter is simulated with a SIMULINK
model while all the analytical calculations are performed with MATLAB func-
tions; the customizable parameters of the simulations are different: power ratings,
modulation techniques and modulation parameters (modulation index, frequency).
The temperature contribution is not considered and all the temperature-depending
parameters are reported with their mean values (between the maximum and the
minimum temperature), in fact the thermal design is not addressed in this first
step of the three-years project and only electric tests will be performed on the final
evaluation Printed Circuit Board (PCB). This model can be used also if in the
future the GaN technology will be available for higher power ratings and its imple-
mentation is described in the Chapter 3, furthermore it is validated comparing its
results with the thermal simulator of an important semiconductor manufacturers.
Another important task performed by the model is the analytical computation of
the ripple component of the DC-link current and the evaluation of the input voltage
ripple. Inverters are switching converters, hence they are non-linear devices: the
output spectrum of both voltages and currents is full of unwanted harmonics, and
they are reflected to the DC-side of the inverter in the form of a polluted current. In
order to keep the DC voltage clean and stable, complex harmonic filtering systems
must be used. Chapter 4 deals with the design and selection of a DC-link capacitor
to be connected in parallel with the DC source in order to create a low-impedance
path towards ground for the polluted current. However, since the root mean square
(rms) and peak value of the ripple DC-link current to be filtered are large suitable
capacitors may be heavy, unreliable and expensive; for this reason, other solutions
are discussed in Chapter 4.3, even though they will not be implemented in this
work.
All the simulations performed together with the selection of the best switches
and capacitor for the application is the pillar for the other steps of the design
addressed in the Chapter 5; all the aspects concerning the gate driver design, the
power supply design and heavy-duty certification criteria (insulation, health issues,
5
 1 – Introduction

standards) are explored in this Chapter. All the integrated circuits chosen are
AEC-Q100 qualified: it is a failure mechanism based stress test qualification for
packaged integrated circuits. The purpose of this specification is to determine that
a device is capable of passing the specified stress tests and thus can be expected to
give a certain level of quality/reliability in the application [2]. Furthermore, also
the passive components are adequately chosen to ensure the best reliability for the
stressing condition of heavy-duty environments: they are AEC-Q200 qualified, the
counterpart stress test qualification for passive components [3].
Finally, the schematic and layout design of an evaluation board has been made,
in order to verify all the previous steps and to evaluate the gate drivers and the
power supply performance. This board is manufacturer on a two-layer PCB with
small sizes, a well suited choice when a cheap and fast delivery system is needed
for in house testing purposes. The Thesis ends with the Chapter 7 in which the
main contributions and findings of this work are summarized and an outlook on
the future perspectives and applications is investigated.

6
Chapter 2

Inverter
In this Chapter, some basic concepts about switching power converters will be
reviewed in order to better describe nd justify some criteria adopted in the design
of the inverter for heavy-duty applications. Inverters, are circuits that convert
power from a DC source to an AC load in the most efficient way in order to not
lose energy, and they can be classified in function of the number of outputs, the
type of inputs and the kind of modulation they employ to get energy conversion.
Inverters are four quadrants converter with bipolar output voltage and bidirectional
output current; this is necessary because the load is usually not resistive but also
because bi-directionality can be a desired feature.
Taking into account the number of outputs phases, inverter can be classified into:

• single-phase inverters with one current and one voltage as output;

• three-phase inverters with three different outputs shifted by 120◦ each to the
other.

Taking into account the input, there are:

• VSI (Voltage Source Inverter) with constant input voltage; the amplitude of
output voltage does not depend on the load while the waveform of load current
as well as its magnitude depends upon the nature of the load impedance;

• CSI (Current Source Inverter) with constant input current; the amplitude of
output current is independent of load while the magnitude of output voltage
and its waveform is dependent upon the nature of load impedance.

Taking into account the modulation, among several possible techniques [23], must
be cited:

• the sinusoidal modulation with a sinusoidal control voltage used to control

both the output magnitude and the output frequency;
7
 2 – Inverter

• the square wave modulation used to control just the output frequency; In order
to change the output magnitude it is needed to change the DC input voltage
magnitude;

• the voltage cancellation method that it is an improvement of the square wave

modulation in terms of spectral purity of the output signal which is suitable
only for single-phase inverters.

A single-phase VSI inverter is suitable for low power applications, while a three-
phase VSI inverter is recommended for medium and high power applications [48].
The inverter designed in this Thesis has to deal with high power application, so
a three-phase VSI inverter has been considered in what follows. Taking into ac-
count a three-phase system with a balanced wye-connected load (Figure 2.1), some
important relationships for the voltages and the currents of the inverter outputs
are reported as follows:
√
Pout = 3VLL ILL cos (φ)
rms rms
(2.1)

√
rms
VLL = 3VLN
rms
(2.2)

rms
ILL = ILN
rms
(2.3)

where VLL rms

is the rms value of the line voltage (see, for example, vAB in Figure
2.1), VLN is the rms value of the phase voltage (see, for example, vAN in Figure
rms

2.1), ILL
rms
is the rms value of the line current and ILN
rms
is the rms value of the phase
current; Pout is the active power while cos (φ), where (φ) is the cosine of the phase
angle between current and voltage, is the Power Factor and it is the ratio between
the real power absorbed by the load and the apparent power flowing in a circuit.

Figure 2.1. Wye-connected balanced load (Z1 = Z2 = Z3 ). A, B and C are called

"line" while N is called "neutral". [6]

8
 2.1 – Three-phase two-level Voltage Source Inverter

2.1 Three-phase two-level Voltage Source Inverter

The topology adopted in the following project is a Three-phase two-level Voltage
Source Inverter. It is made by three fundamental switching poles (Figure 2.2), one
for each phase, called also legs and it is a two level converter because the output
voltage can be positive or negative with respect to the mid potential of the DC bus
[20].

Figure 2.2. 3-phase Inverter.

In order to obtain a four quadrants converter, VSIs have switches capable to

manage the bipolarity and the bi-directionality. Moreover, this inverter topology
is used for mid to high power applications, so power MOSFETs and IGBTs can be
used as switches [59]. Their electrical characteristics must be as close as possible
to that of an ideal switch, that means high blocking voltage and high conduction
voltage are required. Furthermore, they should be capable to dissipate as low as
possible (very low on-resistance) with a high switching frequency.
A power MOSFET is intrinsically a bidirectional device thanks to the body diode
while an IGBT is intrinsically unidirectional in current, but they are built with
an additional diode inside the same package to allow for conducting current in the
opposite direction [59]. Thus, both of them are capable to work in the four quadrant
application. For what concerns their features: MOSFETs show lower switching
time because they are unipolar devices (only one kind of carriers is involved in
conduction), while some IGBTs show lower on-resistance. Since the IGBT is built
from the basic structure of a vertical MOSFET, both of them need a control voltage
to the input control terminal (the gate terminal) in order to turn-on the device.
There are some advantages in using only n-channel MOSFETs and IGBTs due
to their lower on-resistance, higher frequency applications and lower costs with
respect to p-channel devices. The consequence is that the upper transistor of the
9
 2 – Inverter

leg (called high-side transistor) is biased as a common drain/collector, while the

bottom transistor of the leg (called the low-side transistor) is biased as a common
source/emitter. The difficulty is the absence of a common gate and a common
source/emitter point and thus there is no way to have a single drive signal for
controlling both of the leg transistors [20]. The control signal of each transistor
must be separated and isolated from each other beacause the source/emitters are at
different potentials. Since all the low-side source/emitters of each leg are connected
to the negative side of the DC bus, they are at the same potential and the control
signals does not need to be isolated.

2.2 Modulation techniques

In order to have an output voltage with the desired waveform, amplitude and
frequency, the control signals for transistor switching can be generated with the
carrier-based PWM (Pulse Width Modulation) technique: it defines the on and off
states of each switch by comparing one (or more) control voltage vCT RL (modulating
signal) with a triangular carrier signal vtr (Figure 2.3) [48]. Since the ratio between
the amplitude of the control signal and the amplitude of the carrier signal deter-
mines the pulse width, a parameter called modulation index can be introduced:

v̂CT RL
ma = (2.4)
v̂tr
where the sign ôver the voltages in (2.4) means the peak value.

Figure 2.3. PWM modulator. [42]

The modulation index is an important parameter because the amplitude of the

output first harmonic of the output voltage of the inverter is determined by the
pulse width, as it will be described in what follows. Instead, the ratio between the
switching frequency and the control signal frequency takes the name of frequency-
modulation index:
fsw
mf = (2.5)
fCT RL
10
 2.2 – Modulation techniques

The switching frequency fsw acts as a sampling signal while the control signal fCT RL
acts as the sampled signal; the PWM modulator behaves like a two-tone system,
hence the Nyquist–Shannon sampling theorem must be satisfied in order to obtain
the right behaviour.
The modulator output is a pulsed waveform obtained from a smooth input signal:
this is a non-linear operation and the output spectrum of a non-linear two-tone
system presents both harmonics and intermodulation products (IIP) that must
be filtered out [43]. It is useful to introduce a quantity in order to taking into
account the quality of the AC output voltage or current; this parameter is the
Total Harmonic Distortion (THD) [22] and, neglecting the output DC component,
it is generally defined as follows:
ñq
∞
h=2 v̂o2h
T HD = (2.6)
v̂o1

where v̂o1 is the amplitude of the fundamental output component and v̂oh is the
amplitude of the harmonic of order h.
There are several implementation methods for the PWM technique and each of
them gives different results with respect of the others, not only in terms of the
output amplitude and waveform, but also in terms of spectral purity and power
dissipation.

2.2.1 Sinusoidal PWM (SPWM)

Since most of the applications need sinusoidal output voltages, the output of a
three phase SPWM inverter should be a set of three voltage sine waves with a
phase shift of 120◦ among each other. Thus, the legs are driven by sinusoidal
control signals (Figure 2.4.a) with the same frequency and phase difference of the
target outputs but with a considerably smaller amplitude. These three modulating
signals are compared with a unique carrier signal vtr , whose frequency is equal to
the switching frequency.
The phase voltages vAN and vBN (Figure 2.4.b, 2.4.c) have basically the same
behaviour of the modulation signal of switches M1 and M3, respectively, with a
different amplitude. These phase voltages, as well as vCN (not showed in Figure
2.4), are composed by a DC component and by an AC component vLN . Taking
into account the relation (2.4), the first harmonic amplitude of each phase voltage
can be written as:
Vd
v̂LN = ma (2.7)
2
while the amplitude of the line voltages vLL (Figure 2.4.d) is:
√
3
v̂LL = ma Vd (2.8)
2
11
 2 – Inverter

Equations (2.7) and (2.8) shows that the amplitude of the AC output voltages is a
function of the modulation index ma , but this is always verified only in the linear
operation region (i.e. for ma ≤ 1, Figure 2.6). This means that the maximum
amplitude of the line voltage fundamental harmonic is:
√
3
v̂LL,max = Vd (2.9)
2

Figure 2.4. Waveforms in a SPWM 3-phase 2-level VSI with delta-load con-
nection: (a) carrier and modulating signals; (b) phase voltage between phase A
and neutral; (c) phase voltage between phase B and neutral; (d) AC line voltage
between phase A and phase B. [42]

12
 2.2 – Modulation techniques

Furthermore, another condition must be satisfied in order to obtain the fea-

tures of a three-phase SPWM inverter with a single carrier signal: the frequency-
modulation index should be an odd multiple of 3 [48]. As Figure 2.5 shows, with
this choice only odd intermodulation products (sidebands) appear in the output
spectrum.

Figure 2.5. Harmonics h of the fundamental in a three-phase SPWM inverter

with ma = 0.8 and mf = 15. [42]

2.2.2 Square wave modulation

Supposing to further increase the control signal amplitude v̂CT RL making it larger
than the carrier signal amplitude v̂tr , the modulation index ma will be greater than
one and the inverter will be driven in the so-called overmodulation region (Figure
2.6).

Figure 2.6. Fundamental AC output component of the line voltage in

a VSI SPWM inverter. [48]

13
 2 – Inverter

When the instantaneous value of v̂CT RL is higher than the instantaneous value
of v̂tr , the output voltage will increase leading to an higher amplitude of the funda-
mental AC output voltage; on the other hand, low-order harmonics are generated
[48]. The linear relation (2.8) is no longer valid because of the saturation effect due
to overmodulation.

Figure 2.7. Square wave inverter output waveforms: the three phase voltages
vAN , vBN , vCN and one of the line voltages vAB . [42]

By further increasing the modulation index, when the output voltage becomes
a totally AC square voltage, the square-wave modulating technique (Figure 2.6)
is reached. Each transistor conducts for one-half cycle of the ac output period,
so during each of the six intervals, three transistors are in the ON-state while the
remaining three are in the OFF-state (Figure 2.7). In this region, the fundamental
AC line voltage of the output has the following amplitude:
√ 4 Vd
v̂LL = 3 (2.10)
π 2
The relation (2.10) shows that the only way to change the fundamental amplitude
is to control the DC input voltage Vd .
The square wave modulating technique allows exploiting simpler control circuit
and the switching frequency is significantly lower than in PWM inverters with the
14
 2.2 – Modulation techniques

additional beneficial of lower switching losses. The drawback is in the purity of the
output spectrum: square wave consists of a superposition of odd harmonics with
a magnitude inversely proportional to their order which distort the output voltage
and in many applications such distortions are not tolerable, mostly when the use
of filter circuits to filter out satisfactorily the harmonics is not suitable.
In this project, the inverter drives an AC motor load which are inductive in
nature with the intrinsic property to low-pass filtering the harmonic currents. De-
spite this inherent quality, the load current can still contain some harmonics, and
they cause extra iron and copper losses in the motor but also unwanted torque
pulsations. The motor speed hardly changes in response to these torque pulsations
and, in some cases, they produce unwanted resonance in the mechanical system of
the drive [21]. For these reasons, in the project described in this paper the square
wave modulation will not be taken into account.

2.2.3 Third harmonic injection

From the previous analysis, it can be noticed that a SPWM inverter has a good
purity in terms of output spectrum, a linear relation between modulation index
ma and fundamental output voltage amplitude v̂LL but the maximum value of v̂LL
output voltage is limited. The opposite situation happens considering the square
wave inverter, with an higher amplitude of the fundamental v̂LL but with a distorted
output voltage due to the presence of many low-order harmonics. The goal is to
achieve a higher value of the fundamental without cross the linear region, hence
with a maximum value of ma = 1.
Let’s consider to use a control signal that is the sum of two tones f1 and 3f1 , as
shown in Figure 2.8:

vCT RL = VC1 sin (ω1 t) + VC3 sin (3ω1 t) (2.11)

In this way, it is possible to obtain an higher fundamental line voltage at the output
but at the same time keeping the control voltage amplitude lower the triangular
waveform amplitude, which means to work in linear region with ma ≤ 1. Further-
more, when the line voltage is considered, the third harmonic component disappear
due to the phase shift of the three-phase inverter.

15
 2 – Inverter

Figure 2.8. Control signal in a third harmonic injection inverter. [42]

It can be shown that, by having k = Vo3 /Vo1 = 1/6, the maximum amplitude of
the fundamental output line voltage is:
√
v̂LL,max = 3v̂LN,max = Vd (2.12)

2.2.4 Space-Vector modulation (SV PWM)

With the spread of fast Digital Signal Processors (DSPs), microcontrollers and mi-
croprocessors, all the control techniques can be implemented using digital systems
and the developing of digital modulation strategies has lead to the Space-Vector
modulation, a technique that allows to increase the amplitude of the output voltage
fundamental until the value obtained with the third harmonic injection technique
and, moreover, to push the harmonics at higher frequency.
Space-Vector PWM has become a popular pulse width modulation strategies for
three-phase VSI for AC motor driving because of its different features: high torque
to current ratio, large power to weight ratio, higher efficiency, and robustness [37].
The SV PWM is a digital technique with the objective to generate PWM load
line voltages that are, on average, equal to given load line voltages [48]. This is
done explicitly varying the position of the inactive states of operation of a converter
within each half carrier period, in fact it is one of the modulation strategies based
on Zero Space Vector Placement and it is based on the Park’s transformations [23].

Clarke transform
When a high-side transistor is switched on, the corresponding low-side is switched
off because it is not possible to short the input voltage supply. Hence, there are
23 possible switching states combinations for the three inverter legs, referred to
16
 2.2 – Modulation techniques

the conduction state of three high-sides M1, M3, M5: (000), (100), (110), (010),
(011), (001), (101), and (111); the lower phase leg switches (M2, M4, M6) are
represented as logical NOT of the upper phase leg switches. Each of these produces
a specific combination of the phase and line output voltage: the first and the last one
produce a null line voltage, while the other six states produce a voltage applicable
to the motor. The Clarke transform is a mathematical representation of these space
vectors and it transform the voltage equations in the natural three-phase coordinate
system abc into the stationary αβ reference system (Figure 2.9).
Since in a balanced 3-phase system the scalar sum of the three variables ua , ub ,
uc is zero at any instant, the complex vector that defines abc quantities in the αβ
system can be introduced
è é
þu (t) = C ua (t) + ub (t) ejγ + uc (t) ej2γ (2.13)
and it is the representation of the three line voltages in the 2D system αβ:
è é
þvαβ = þvα + jþvβ = C vAB + vBC ejγ + vCA ej2γ (2.14)
where γ = 120◦ and C is a normalization factor used to maintain the amplitude
equal across the transform because without it the amplitude of the αβ variables is
higher than the abc variables. Placing the factor C = 2/3 in order to obtain an
amplitude invariant space vector, the following system is obtained:
1
    
vα − 1/2 − 1/2 vAB
2 √ √
vβ  = 0 3/2 − 3/2 vBC  (2.15)
   
3
v0 1 1 1 vCA

Figure 2.9. Relationship between abc reference system and stationary αβ system. [42]

17
 2 – Inverter

Table 2.1 shows the valid switch states for a three-phase VSI and the corre-
sponding space-vectors, six active ones (not nulls) and two null ones, obtained
from equation (2.15). Assuming a wye-connection at the load, the combination
of phase voltages are reported from the third through the fifth column and in the
sixth, seventh and eight column the line voltages are showed. The eight space-
vector in the last column of Table 2.1 are represented in the complex plane αβ of
Figure 2.10 normalized with respect to Vd . It can be noticed that the six active
vectors are separated by 60◦ and they have a magnitude of
2
||þvx || = √ (2.16)
3
Each pair of them forms a sector, while the two null vectors lie in the origin of the
system, hence six equal sectors are represented. Two important features can be
extrapolated from previous analysis:
1. two adjacent active vectors are just one bit different;
2. the active vectors differ from one of the two null vectors of one only bit.
It is easy to deduce how such a control scheme can be easily implemented with
a DSP, and this is one of the reason why in this project the Space-Vector PWM
technique is the adopted control method.

State # vAN vBN vCN vAB vBC vCA Space-Vector

1 √ 2
100 1 2/3V
d
− 1/3V
d
− 1/3V
d Vd 0 −Vd þv1 = 1 + j 33 Vd
110 2 1/3V
d
1/3V
d
− 2/3V
d 0 Vd −Vd þv2 = j √23 Vd
1 √ 2
010 3 − 1/3V
d
2/3V
d
− 1/3V
d −Vd Vd 0 þv3 = −1 + j 3
Vd
1 √3 2
011 4 − 2/3V
d
1/3V
d
1/3V
d −Vd 0 Vd þv4 = −1 − j 33 Vd
001 5 − 1/3V
d
− 1/3V
d
2/3V
d 0 −Vd Vd þv5 = −j √23 Vd
1 √ 2
101 6 1/3V
d
− 2/3V
d
1/3V
d Vd −Vd 0 þv6 = 1 − j 33 Vd
111 7 0 0 0 0 0 0 þv7 = 0
000 8 0 0 0 0 0 0 þv8 = 0

Table 2.1. The eight switch states in a three-phase VSI with the corresponding
space vector of each line voltage combination.

Space-Vector Modulated Inverter

The goal is to combine in a proper way the six active vectors and the two null (or
static) vectors to build the desired sinusoidal output line voltages. When these three
sinusoids are manipulated by the Clarke transform, they correspond to a rotating
vector in the αβ plane with constant magnitude over each cycle. Moreover, every
18
 2.2 – Modulation techniques

time instant it is the projection of the line voltages, thus it becomes the base of the
control signal and it is called modulating vector þvc (Figure 2.10).
The modulating vector is generated by switching between two nearest active
vectors and zero vector [27]; supposing to construct it from space vectors þv1 and þv2
(Figure 2.11), the modulating vector is defined as:

þvc = r1þv1 + r2þv2 (2.17)

where r1 and r2 represent the normalized time interval, with respect to TSW , during
which þv1 and þv2 are applied and they can be evaluated by geometric analysis:
2 ||þvc || π 1 π
3 4 3 4
r1 = √ sin −θ = ||þvc || sin −θ (2.18)
3 ||þv1 || 3 Vd 3

2 ||þvc || 1
r2 = √ sin (θ) = ||þvc || sin (θ) (2.19)
3 ||þv1 || Vd
In order to keep the linear operation the condition

r1 + r2 ≤ 1 (2.20)

must be imposed, because the total time during which space vectors are applied
has to be lower than the modulation switching period TSW .

Figure 2.10. Space vector representation in the αβ complex plane. [48]

Taking into account Figure 2.10, in order to keep linear operation the circle
formed by the modulating vector must not exceed the hexagon borders. Further-
more, it can be noticed that the maximum of ||þvc || corresponds to its radius.
19
 2 – Inverter

Figure 2.11. Modulating vector construction. [27]

The radius of the circle formed by the modulating vector can be geometrically
evaluated
1 1
-
π
3 4 -
||þvc || sin −θ + ||þvc || sin (θ)-- ≤1 (2.21)
-
Vd 3 Vd θ=θt

and considering that the limit case r1 = r2 = 0.5 occurs at θt = π/6 where

1 1 1 1
=⇒ ||þvc ||max + ||þvc || max ≤ 1 (2.22)
Vd 2 Vd 2

one important result is found:

||þvc || = v̂LL,max = Vd (2.23)

With the Space-Vector PWM technique, the maximum fundamental amplitude

√
of the output line voltage is 2/ 3 Ä 1.15 higher than the one of the Sinusoidal
PWM reported in (2.9) and it has the same amplitude achievable with the third
harmonic injection technique obtained in (2.12). Taking into account the linear
relation between the modulation index ma and the fundamental amplitude v̂LL ,
the following relation is obtained:

v̂LL = ma Vd , 0 ≤ ma ≤ 1 (2.24)

The limit case r1 = r2 = 0.5 that leads to these results is not always verified when
the modulating vector is constructed by averaging the space vectors [23], because
the switching period TSW must remain constant.
20
 2.2 – Modulation techniques

Figure 2.12. SV PWM symmetric switching pattern for Sector 1. [27]

This issue is easily bypassed by properly combining the null vectors with the
active vectors. In fact, it is a Zero Space Vector Placement technique and it allows
to have the degree of freedom to choose the location and duration of the null vectors
within one period TSW . The positioning can be done according to the specific
application and, in this project, the pattern of the switching frequency is obtained
by centring the active vectors and equally spacing the inactive vectors (Figure
2.12), in such a way that each leg change its sate only once in one switching period
[27]. With this symmetric switching sequence, six commutations happen over one
switching period leading to another features of this modulation technique: the less
commutation are done, the less is the harmonic content at the output; in particular,
the symmetric SV PWM has the lowest THD achievable with this technique [24].

21
22
Chapter 3

Evaluation of power losses

This chapter focuses on a step-by-step development of MATLAB/SIMULINK model
of the inverter controlled by two configurable technique: the Sinusoidal PWM and
the Space-Vector PWM. The reason why the square wave modulation technique
and the third harmonic injection technique are not implemented in the model is
related to their feauters explained in Chapter 2 and some of them are refreshed
here:
• the output spectrum of the SPWM and SV PWM techniques, due to their
low harmonic content, is more suitable in motor drive application because
harmonics leads to resonance in the mechanical system of the drive;
• the third harmonic injection technique requires two oscillators and so it is more
expensive;
• the SV PWM method is a intrinsic digital technique and so it is fast and easy
implementable in a microcontroller or DSPs.
The main goal of the model is to evaluate the conduction and the switching losses of
the three-phase inverter and to derive the current and voltage waveforms necessary
fo the electric design.
The analysis carried out in this Thesis concerns a general purpose three-phase
VSI because the load requirement will be defined only in further and later de-
veloping. Hence, the given specifications reported in Table 3.1 does not contain
indications about the motor that the inverter has to drive. From the specifications
reported in Table 3.1, a model capable to run an electric simulation of the inverter
has been derived. Both IGBTs and MOSFETs behaviour are taken into account
because they are the only switches topology available for this power rating.
In particular, four SIMULINK models have been developed in order to choose the
right topology and modulation for the given application: two models of the three-
phase VSI with IGBT switches, one with Sinusoidal PWM and one with Space-
Vector, and two models of the three-phase VSI with power MOSFET switches,
23
 3 – Evaluation of power losses

one with Sinusoidal PWM and one with Space-Vector. These SIMULINK models,
discussed in what follows and fully reported in Appendix B, and the MATLAB codes
necessary for the simulation, also listed in Appendix A, are analysed in the next
section. Furthermore, in the computation of the power losses only one transistor of
one leg is evaluated because with a balanced load all the legs carry the same shape
of the currents during a period.

Max. DC bus voltage Vd 700V

Max. Output Power Po ut 20kW
Max. DC current Id 29A
Max. Switching Frequency 20kHz
Max. Operating Temperature 125◦
Typ. Output Frequency fout 50Hz
Min. Power Factor cos (φ) 0.5
Max Phase Current 60A
Table 3.1. Specifications for the Inverter.

3.1 MATLAB/SIMULINK model

3.1.1 Sinusoidal PWM
The block-diagram of a three-phase two-level Voltage Source Inverter with IGBT
switches controlled by a Sinusoidal PWM is shown in Figure B.1 and B.2. The six
IGBT switches are inserted in the subsystem IN V ERT ER (Figure B.3) and the
modulating technique used to drive them is generated by the subsystem S P W M
(Figure B.5). As explained in Chapter 2, it consists of three sine waves shifted by
120◦ that are compared with the triangular carrier signal. The presence of delay
blocks can be noticed: they set the dead time of the PWM and it is mandatory to
avoid to short-circuiting the leg [60]. Since the load to be driven is not assigned in
the project specifications, the SIMULINK block T hree − P hase Dynamic Load is
used in order to implements a three-phase, three-wire balanced load where active
and reactive power absorbed by the load vary as function of the input P Q (Figure
3.1). This block allows to limit the maximum phase current according to Table 3.1
by controlling the input P Q with the Current control function listed in Appendix
B.1.
The simulation is initialized with the Matlab script inverter_parameter at-
tached in Appendix A.1.1: with this script it is possible to set all the parame-
ter of Table 3.1 and all the modulation parameter illustrated in Chapter 2. The
main waveforms obtained from some simulations are reported in the next fig-
ures. The value of the simulation parameters can be extrapolated from the script
inverter_parameter.
24
 3.1 – MATLAB/SIMULINK model

The gate control signal generated with the Sinusoidal PWM technique are shown
in Figure 3.2: they leads to a pulsed current with a sinusoidal envelope in each IGBT
and the one associated with switch M 5 is reported in Figure 3.3. When the gate
signal is high the transistor is turned on and it is turned off when the gate pulse
goes low.

Figure 3.1. Three-Phase Dynamic Load simulation parameters.

25
 3 – Evaluation of power losses

Figure 3.2. PWM control waveform of Sinusoidal modulation with ftr = 15kHz
and fCT RL = 1kHz. On the y-axis the time is expressed in second [s].

Figure 3.3. Switched current of IGBT M 5 with ftr = 15kHz, fCT RL = 1kHz and
Sinusoidal PWM. On the y-axis the time is expressed in seconds [s], while on the
x-axis the current is expressed in Ampere [A].

26
 3.1 – MATLAB/SIMULINK model

The line voltage obtained from the simulation confirms the analysis of Chapter
2: as Figure 3.4 shows, the line voltage has zero mean value and the AC component
follows equation (2.8).

Figure 3.4. Line voltage vLL with ftr = 15kHz, fCT RL = kHz and Sinusoidal
PWM. On the y-axis the time is expressed in seconds [s], while on the x-axis the
voltage is expressed in Volt [V].

The Sinusoidal PWM works in the linear region, in fact the maximum amplitude
of the control voltages vCT RL is equal to 0.7465V (Figure 3.5) and it is lower than
the maximum amplitude of vtr = 1V .

27
 3 – Evaluation of power losses

Figure 3.5. Sinusoidal references signals, each one with a phase shift of
120◦ . On the y-axis the time is expressed in seconds [s], while on the x-axis
the voltage is expressed in Volt [V].

The only difference between the model with IGBTs and the one with power
MOSFETs consists in the subsystem IN V ERT ER showed in Figure B.11. They
are initialized with the same script listed in Appendix A.1.1 and the control sub-
system has the same behaviour. The current of power MOSFET M 5 controlled
with the pulsed signal of Figure 3.2 is reported in Figure 3.6.

28
 3.1 – MATLAB/SIMULINK model

Figure 3.6. Switched current of power MOSFET M 5 with ftr = 15kHz,

fCT RL = 1kHz and Sinusoidal PWM. On the y-axis the time is expressed in seconds
[s], while on the x-axis the current is expressed in Ampere [A].

In Figure 3.7 the phase voltage is √

reported: it is evaluated with the script listed
in Appendix B.1 and its rms value is 3 times lower than the one of the line voltage
of Figure 3.4.

Figure 3.7. Phase voltage vLN with ftr = 15kHz, fCT RL = 1kHz and Sinusoidal
PWM. On the y-axis the time is expressed in seconds [s], while on the x-axis the
voltage is expressed in Volt [V].

29
 3 – Evaluation of power losses

3.1.2 Space-Vector PWM

The main difference between the model with the Sinusoidal PWM and the one with
Space-Vector PWM is in the control subsystem SV P W M , reported in Figure B.8:
it is composed of two MATLAB functions that generate the three control signals to
be compared with the triangular carrier signal. In order to write these functions,
it is necessary to evaluate the average of the output phase voltages referred to the
mid potential of the DC bus vN :
Vd
vN = (3.1)
2
Taking into account the symmetric switching pattern of Figure 2.12, using the
general relation of the mean value of the phase voltages [23],

Vd 1
v̄AN = (r1 + r2 )TSW (3.2)
2 tsw

Vd 1
v̄BN = (−r1 + r2 )TSW (3.3)
2 tsw
Vd 1
v̄CN = (−r1 − r2 )TSW (3.4)
2 tsw
replacing equations (2.18) and (2.19) into equations (3.2), (3.3) and (3.4), imposing
the relation (2.24) and taking into account that in the first quadrant
π
0≤θ≤ (3.5)
3
it is possible to find, after some simplifications [23], the phase voltage mean values
in the first quadrant:
1 π
3 4
v̄AN = ma Vd cos θ − (3.6)
2 6
√
3 2
3 4
v̄BN = ma Vd cos θ − π (3.7)
2 3
1 5
3 4
v̄CN = ma Vd cos θ + π (3.8)
2 6
By iterating the previous steps for all the six active sectors, it is possible to obtain
the reference voltages of the phase leg of the Space-Vector technique reported in
Table 3.2. The outputs dutyU , dutyV and dutyW of the function Ref erence
V oltage in the subsystem SV P W M (Figure B.8) generate the reference voltage
of Table 3.2, taking into account the simulation parameter set with the script
inverter_parameter listed in Appendix A.1.2.
30
 3.1 – MATLAB/SIMULINK model

Sector Leg A Leg B Leg C

1 2 √ 1 2 1 2
1 1
m V cos θ − π6
2 √a d 2
3
ma Vd cos θ − 23 π 1
m V cos θ + 56 π
2 a d
2 2
3
ma Vd cos
1 (θ) 2
1
m V sin (θ) 2
2 a d1 √
− 12 ma Vd sin
1 (θ) 2
3 1
m V cos θ + π6
2 a d
1
m V cos θ + − 53 π
2√ a d 2
3
ma Vd cos θ + 23 π
1 2 1 2 1 2
4 1
m
2 √a d
V cos θ − π
6 2
3
m V
a d cos θ − 2
3
π 1
m
2 a d
V cos θ + 5
6
π
5 2
3
ma Vd cos
1 (θ) 2
1
m V sin (θ) 2
2 a d1 √
− 2 ma Vd sin
1
1 (θ) 2
6 1
m V cos θ + π6
2 a d
1
m V cos θ + − 53 π
2 a d 2
3
ma Vd cos θ + 23 π

Table 3.2. Phase leg reference voltages of Space-Vector PWM.

With a modulation index ma = 0.8 and a control frequency fCT RL = 1kHz, the
reference signals of Figure 3.8 are generated. The similitude with the reference
voltages of the third harmonic injection technique (Figure 2.8) turns out and this is
the reason why Space-Vector PWM produces higher amplitude mean line voltages
(equation 2.24) with respect to Sinusoidal PWM: the phase leg reference voltages
are generated by sine waves injected with third-harmonic components without the
use of more expensive modulator, such as in the case of the third harmonic injection
technique.

Figure 3.8. Phase leg references signals for leg A (signal U), leg B (signal V) and
leg C (signal W). On the y-axis the time is expressed in seconds [s].

The reference voltages of Figure 3.8 are then compared with a triangular carrier
frequency with unitary maximum amplitude and the pulsed gate control signal are
obtained (Figure 3.9).
31
 3 – Evaluation of power losses

Figure 3.9. PWM control waveform of Space-Vector technique with ftr = 15kHz
and fCT RL = 1kHz. On the y-axis the time is expressed in second [s].

The control signals of Figure 3.9 drive the IGBT gate terminals of Figure B.3
and the pulsed current flowing into the switch M 5 is reported in Figure 3.10.

Figure 3.10. Switched current of IGBT M 5 with ftr = 15kHz, fCT RL = 1kHz
and Space-Vector PWM. On the y-axis the time is expressed in seconds [s], while
on the x-axis the current is expressed in Ampere [A].

The line voltages of Figure 3.11, obtained with the parameter values listed in
the inverter_parameter script in Appendix A.1.2, have the same amplitude of
the ones obtained with the Sinusoidal PWM, although the modulation index ma
is different. Taking into account equation 2.24, for the Space-Vector PWM it is
obtained ma = 0.6465 while, taking into account equation 2.8, the modulation
factor for the Sinusoidal PWM was ma = 0.7465. The ratio between these two
32
 3.1 – MATLAB/SIMULINK model

modulation index values is about 1.15 and it confirms the theory analysis carried
out in Chapter 2.

Figure 3.11. Line voltage vLL with ftr = 15kHz, fCT RL = 1kHz and Space-Vector
PWM. On the y-axis the time is expressed in seconds [s], while on the x-axis the
voltage is expressed in Volt [V].

For what concern the model with power MOSFET, the block diagram can be
seen in Figure B.12 and Figure B.13.

Figure 3.12. Switched current of power MOSFET M 5 with ftr = 15kHz,

fCT RL = 1kHz and Space-Vector PWM. On the y-axis the time is expressed in
seconds [s], while on the x-axis the current is expressed in Ampere [A].

The pulsed current of transistor M5 (Figure 3.12) combined with the pulsed
currents of the other five transistors give rise to the load output current showed in
Figure 3.13. The frequency of these waveforms follows the frequency of the control
33
 3 – Evaluation of power losses

signals fCT RL and the maximum amplitude is limited to 60 Amps thanks to the
real-time supervision of the Current control function (Appendix B.1).

Figure 3.13. Output current of the three-phase VSI with ftr = 15kHz,
fCT RL = 1kHz and Space-Vector PWM. On the y-axis the time is expressed in
seconds [s], while on the x-axis the current is expressed in Ampere [A].

3.2 Simulation and calculation of losses

All the circuital models illustrated in the previous section have been developed with
the aim to obtain the DC-link current of the inverter and in order to evaluate the
switching losses of the power switches available on the market and, in order to do
this, in Figure B.2, B.7, B.10 and B.13 the SIMULINK block to workspace can be
noticed; it is used to store the MOSFET pulsed current or the IGBT pulsed current
as a time-series in the workspace. The discussion about the DC-link current and
the choice of the harmonic filtering solution is postponed to Chapter 4 while this
Section is divided into three main parts:

1. research on the market and choice of some IGBTs and power MOSFETs well
suited for the application;
34
 3.2 – Simulation and calculation of losses

2. creation of a library with the losses characteristic of chosen components;

3. simulation and real power losses evaluation;

Selection of the semiconductor switches

Looking on the websites of well-known sellers and of different manufacturers, many
solutions are available: single transistors, half-bridge configurations and six-pack
modules. A single transistor is a choice that leads to increase the volume of the
system because its package is not optimized as a module but it allows bettering
thermal dissipation thanks to the bigger size. On the other hand some modules
allow to have all the six switches in a small package, furthermore they are optimized
from a point of view of parasitic components with the drawback of an higher cost.
Half-bridge packaging is a trade off between the other two configurations. The
electric ratings of the transistors must be compliant with the specifications of Table
3.1 After many researches, the components reported in Table have been chosen.

Manufacturer Configuration Topology

CM100TX(P)-24T Mitsubishi six-pack IGBT
SEMiX101GD12E4s Semikron six-pack IGBT
SK100GD12T4T Semikron six-pack IGBT
SEMiX101GD12Vs Semikron six-pack IGBT
FS75R12KT4_B15 Infineon six-pack IGBT
IRGPS60B120KDP Infineon/IR single IGBT
APTMC120TAM33CTPAG Microsemi six-pack SiC MOSFET
CCS050M12CM2 Cree six-pack SiC MOSFET
Table 3.3. MOSFETs and IGBTs suitable for the application of this project.

They have been selected because they have breakdown voltages higher than
the DC bus voltage of 700V, they can handle a current higher than 60A also with
hotter temperatures and they have a good trade off between cost and performances.
Furthermore, all the MOSFETs are SiC devices because they are the state-of-the-art
of the MOSFET for this power rating, as already explained in Chapter 1.

Definition of a library of switch parameters

In order to evaluate the losses, some important parameters typically reported on
the switch data-sheet must be taken into account: the on-resistance, the voltage
drop across the switch during the conduction and the switching energy losses. All
these parameters have been evaluated for the device showed in Table 3.3 and, in
particular, all the switching energy losses curves have been stored in M AT file
35
 3 – Evaluation of power losses

using Grabit (Figure 3.14), which is a GUI program capable to manually extract
data point from a file and to save it.

Figure 3.14. Screenshot of the GUI of Grabit while grabbing points.

For what concerns the on-resistance values, in order to neglect the temperature
variations (the reason of this is reported in the subsection 3.2), they are reported
with its mean value, computed between minimum and maximum value written on
data-sheet. The on-state voltage drop values read from the data-sheet are scaled
with a correction factor equal to the ratio of maximum and minimum value and
then, for an engineering calculation, a safety margin value of 15% is also used [17].
All the MAT files with the switching losses curves have been stored in one file
creating a sort of offline library; this allows to make future comparison with newest
device, for example when a GaN MOSFET will be available for higher power ratings
it will be sufficient acquire its switching energy losses curves, store it in the library
and compare its performance with the other ones.
36
 3.2 – Simulation and calculation of losses

Power losses evaluation

In all the switching devices, power losses might be divided into three groups [59]:
1. conduction losses of the transistor and of the diode; they depend on the load
current, junction temperature and duty cycle;
2. switching losses of the transistor and of the diode; they depend on the load
current and the electric load type (inductive for the interest of this project),
the DC input voltage, junction temperature and the switching frequency;
3. leakage losses, normally neglected because they typically gain importance just
in case of blocking voltages higher than 1kW and/or with operating temper-
atures over 150◦ .
In a Voltage Source Inverter, duty cycle, load current and junction temperature are
not constant because they depend on the fundamental frequency of the AC side
(in the case of this project fout = 50Hz), thus also power losses changes in time
[51]. For the purpose of this project a so in-depth analysis is not required, hence
the following simplifications can be imposed for estimating the expected power
dissipation during converter operation mode in a more practical way:
• switching times are neglected;
• constant junction temperature (approximation due to fout = 50Hz) [59];
• linear modulation.
For what concern the IGBT, instantaneous conduction losses pCT can be estimated
linearising the IGBT by a series connection of DC voltage source vCE0 representing
the on-state collector-emitter voltage drop with a collector-emitter on-resistance
rCE,on ; being iCE the current through the collector-emitter terminals [17]:
pCT (t) = vCE0 iCE (t) + rCE,on i2CE (t) (3.9)
Taking into account the MOSFET instantaneous conduction losses pCM , they can
be calculated using a linear model with the drain-source on-resistance rDS,on ; being
iDS the current through the drain-source terminals [18]:
pCM (t) = rDS,on i2DS (3.10)
For what concern the anti-parallel diode, instantaneous conduction losses pCD can
be evaluated in the same way, for both IGBT and MOSFET, with a diode approxi-
mation composed by a DC voltage source vd0 representing the on-state voltage drop,
connected in series with the diode on-resistance rd ; being vd the voltage across the
diode and if the forward current through the diode [18]:
pCD (t) = vd0 if (t) + rd i2f (t) (3.11)
37
 3 – Evaluation of power losses

The switching losses are estimated storing the instantaneous current of the switch
from the simulation of the SIMULINK models illustrated in the previous section
and using it as an input parameter to read the switching energy losses curves stored
in the library created with GRABIT .
The script used to evaluate the IGBT losses is listed in Appendix A.2.1 while
the one used for power MOSFET is in Appendix A.2.2. The difference between
the two scripts is mainly in the last part, because the MOSFET reverse conduction
opportunities makes the IGBT equations unsuitable for the calculation of MOSFET
conduction losses in an inverter system. A very exhaustive numeric method can be
found in [57] but, in order to be able to directly compare the MOSFET conduction
losses with the IGBT ones, the models must have the same approach. This is
the reason why the linearisation approach of [17] and [18] is the reference one
used during the implementation of scripts A.2.1 and A.2.2. Furthermore, the SiC
MOSFETs selected are with zero reverse recovery current.
Despite the presence of two script, the general flux of the analysis is the same:
1. the first step is loading the parameters of the transistor to simulate by un-
comment the section of the script with the switch identification number and
commenting the other ones;
2. with the switch parameters stored in the workspace, the trigger section of
the script loads the data points of transistor current (Figure 3.10) passed by
the SIMULINK simulation, and then it selects only one period (Figure 3.15)
of this waveform searching the acquisition starting point after ten periods (in
order to have the current at steady state condition);
3. the third section of the codes, called edge detection, isolates all the current
values during the transitions (Figure 3.16) by detecting all the fronts of the
waveform and by storing the current values on it; it also stores the conduction
current values because they are the ones between a rising and a falling edge;
4. the last part is composed of two sections, one for the evaluation of the con-
duction losses and one for the evaluation of the switching losses. In section
conductionlosses, equation (3.9) or equation (3.10) is used during the positive
half part of current period, combined with the equation (3.11) that evaluates
the diode conduction losses during the negative half part. Section switching
losses is the only part with cyclic function because the f or cycle takes the
corresponding switching energy value from the library for each current peak
isolated in edge detection section. The instantaneous on-switching losses are
associated with the rising-edge peaks of the positive half part of the current,
the instantaneous off ones are associated with the falling-edge peaks of the
positive half part of the period, while the instantaneous recovery losses of the
diode are significant only during the rising-edge of the negative half period
of the current [17], [18], [59]. The average value of the conduction losses is
38
 3.2 – Simulation and calculation of losses

obtained integrating the instantaneous power losses over the switching cycle
and in this case the MATLAB function trapz is used.

The code explained in as before has been redacted minimizing the use of cyclic
function and maximizing the use of built-in MATLAB function; the result is a
code more readable, faster and with few hardware resources used [7], hence the
simulation is completed in about six seconds.

Figure 3.15. One period of the transistor M 5 current used to calculate losses.

39
 3 – Evaluation of power losses

Figure 3.16. Current amplitude values during the transitions.

The inverter parameter for the simulation of losses have been setted following the
specifications of Table 3.1 and, for the parameter without restrictions, the values
of Table 3.4.

Phase-to-phase output voltage Vrms 320V

Output Frequency 50Hz
Power Factor cos (φ) 0.8
Switching frequency 15kHz
Death time 200ns
Table 3.4. Parameter values for losses simulation.

The conduction losses of the six-pack module Semikron SK100GD12T4T are

reported in Figure 3.17. The orange curve is the instantaneous power dissipated in
the IGBT while the blue curve is the instantaneous power dissipated during in the
diode: it is visible that the transistor technology is typically more optimized than
the diode, thus the blue curve is higher than the orange one.

40
 3.2 – Simulation and calculation of losses

Figure 3.17. Instantaneous conduction losses of Semikron SK100GD12T4T.

Furthermore, Figure 3.18 shows the instantaneous switching energy losses of

Semikron SK100GD12T4T: the blue curve reports the switching on losses, the
black curve measures the switching off losses and recovery losses associated with
the diode are shown in the red curve. The amplitude of these curves is related to
the energy curves that the manufacturer includes on the data-sheet (Figure 3.19)
where the losses associated with the turn-on are the most relevant while the recovery
switching energy plays a minor role.

Figure 3.18. Instantaneous switching losses of Semikron SK100GD12T4T.

41
 3 – Evaluation of power losses

Figure 3.19. Energy losses of Semikron SK100GD12T4T with respect of the

collector-emitter current.

These curves have been evaluated for all the switches of Table 3.3 and the total
switching losses in the transistor and in the free-wheeling diode have been computed
with the following expressions for average powers [17], [18]:

PM OS = PCM + Pswitch,M OS (3.12)

PIGBT = PCT + Pswitch,IGBT (3.13)

PDIODE = PCD + Pswitch,DIODE (3.14)

The simulation result of these simulations are visible in Table 3.5; it can be helpful
to remember that all the losses there reported are referred to one period of the
output frequency Tout = 0.02s.

42
 3.2 – Simulation and calculation of losses

Data of Table 3.5 have to be validated in order to be sure that wrong choices
will be not induced by these simulations. So, the IGBT modules manufactured by
Semikron have been used as samples to validate the implemented model, because
this company has released a free online simulator called SemiSel with the aim to
help beginners with the design of power converters [59]. In this case, SemiSel has
been used to make a comparison between the power losses obtained with the script
of Appendix A.2.1 and the power losses obtained from this online tool.

Sinusoidal PWM Space-Vector PWM

PIGBT PDIODE PIGBT PDIODE
CM100TX(P)-24T 88.6529W 37.2269W 84.9944W 34.4521W
SEMiX101GD12E4s 100.8295W 32.0871W 91.4382W 29.2488W
SK100GD12T4T 110.0492W 29.3469W 105.4490W 27.3270W
SEMiX101GD12Vs 102.8282W 38.5035W 100.4630W 34.8016W
FS75R12KT4_B15 78.4410W 36.6533W 76.9027W 33.8027W
IRGPS60B120KDP 80.1774W 36.7392W 78.7267W 34.8611W
PM OS PDIODE PM OS PDIODE
APTMC120TAM33CTPAG 54.1831W 26.2657W 52.1495W 25.0484W
CCS050M12CM2 52.8522W 25.6065W 51.4272W 24.6259W

Table 3.5. Average power losses for the switches of Table 3.3.

The SemiSel simulation outputs are reported in Table 3.6; considering that
SemiSel takes into account the temperature variations of the IGBT parameters
(Figure 3.20), the results are pretty close to the one obtained from the simula-
tor implemented in this Thesis project (Table 3.5) and this validate the developed
model described in this Thesis that can be useful for a quick comparison and selec-
tion of a suitable switch for the given application.

PIGBT PDIODE
SEMiX101GD12E4s 102W 29W
SK100GD12T4T 112W 31
SEMiX101GD12Vs 105W 38W
Table 3.6. SemiSel simulation results.

Carefully analysing Table 3.5 and taking into account that the purpose is to
obtain a high power density and high efficient converter, the six-pack module
CCS050M12CM2 manufactured by Cree/Wolfspeed has been chosen because it is
more efficient, it has higher breakdown voltage compared with Silicon of the same
43
 3 – Evaluation of power losses

scale, lower on state resistance and higher thermal conductivity [36]. Further-
more, combined with the Space-Vector modulation technique, it allows to reach
high power density combined with high frequency [13]: essential features for lower
overall cost, weight and cooling requirements that are the main challenges of the
heavy-duty sector.

Figure 3.20. SemiSel simulation results for the SEMiX101GD12Vs.

Thus, after all the theoretical assessments and simulations the choice for the
switches topology and their modulation strategy is Cree/Wolfspeed CCS050
M12CM2 with Space-Vector PWM technique. The losses simulation of this
configuration is reported in Figure 3.21 and Figure 3.22.

44
 3.2 – Simulation and calculation of losses

Figure 3.21. Instantaneous conduction losses of Cree CCS050M12CM2 with

Sace-Vector PWM. On the left MOSFET conduction losses, on the right body-
diode conduction losses.

Figure 3.22. Instantaneous switching losses of Cree CCS050M12CM2

with Sace-Vector PWM. Turn-on losses in blu, turn-off losses in black,
recovery losses in red.

45
 3 – Evaluation of power losses

From Table 3.5, the benefit of the symmetric Space-Vector PWM technique
(Figure 2.12) in terms of power losses reduction is not clearly visible. The reason
is the relatively low switching frequency: when it is increased and the output
frequency is kept constant, the Sinusoidal PWM dissipates much more power and
this is showed in Figure 3.23. Nevertheless, Space-Vector PWM technique gives
much more advantages in terms of output harmonic reduction [24].

Figure 3.23. Total power losses in function of increasing switching frequency and
with different PWM strategies.

46
Chapter 4

Analysis of the DC-link

Current
The DC-link current of a power converter is the input current that it absorbs
from the DC source, which is also called DC-link. In automotive and heavy-duty
applications, the DC-link current is the current absorbed by the inverter from a
rechargeable battery pack and it is the superposition of a DC current provided by
the batteries and of an AC component. This last high ripple component must be
filtered out by a harmonic filtering system.
In this Chapter the DC-link Current of a three-phase two-level Voltage Source
Inverter is evaluated in order to choose the DC-link capacitor: it is necessary to
provide reactive power, attenuate ripple current, reduce the emission of electro-
magnetic interference, and suppress voltage spikes caused by leakage inductance
and switching operations [58]. Furthermore, in the last Section of the Chapter, an
overview of alternative harmonic filtering solutions is described because DC-link
capacitor might be unsuitable for some applications.

4.1 Calculation of DC and AC components of the

DC-Link Current
Taking into account Figure 2.2, assuming a lossless three-phase VSI with a three-
phase wye-connected balanced inductive load, furthermore, assuming that the in-
verter does not store energy and no dead-time is needed by the switches the instan-
taneous power balance assumes the following form:

Vd (t) Id (t) = vAN (t) iA (t) + vBN (t) iB (t) + vCN (t) iC (t) (4.1)

where Id (t) is the DC-link current.

47
 4 – Analysis of the DC-link Current

If only the average values of equation (4.1) are considered, the following expres-
sion holds:

Vd Id = V̂LL IˆLL cos (ωout t) cos (ωout t − φ) +

2 2
3 4 3 4
ˆ
+ V̂LL ILL cos ωout t − π cos ωout t − φ − π +
3 3 3
2 2
4 3 4
ˆ
+ V̂LL ILL cos ωout t + π cos ωout t − φ + π (4.2)
3 3
and, taking into account also equation (2.1), the DC Component of the DC-Link
current can be computed:

3 V̂LL ˆ
Id = ILL cos (φ) (4.3)
2 Vd

where V̂LL is the line voltage amplitude and IˆLL is the line current amplitude. If a
Space-Vector modulation strategy is applied to the inverter, the DC bus voltage Vd
and the line voltage are related by means of the relation (2.24), so equation (4.3)
becomes: √
3ˆ
Id = ILL ma cos (φ) (4.4)
2
Equation (4.4) shows that the DC Component of the DC-Link current is time
invariant and it changes just in function of the modulation index ma and of the
power factor cos (φ).
When equation (4.2) has been obtained, only mean values have been considered:
the AC behaviour of the current is lost and so only the DC-Link current has be
computed. Now, starting again from equation (4.1), the aim is to evaluate the
ripple current that a possible harmonic filtering system should sink. In Chapter 3,
the outputs of the SIMULINK models show that the line voltage of the inverter is
a square wave composed of variable width pulses (Figure 3.4, 3.11). The spectrum
of these type of waveforms is full of harmonics (Figure 2.5) and they affect also the
DC-side of the inverter in the form of a polluted current. This AC ripple current
can be evaluated in time domain with the switching function approach [16], [29],
[40], [39].
Without the use of mean values in equation (4.1), the DC-link current in time
domain is:
vAN (t) vBN (t) vCN (t)
Id (t) = iA (t) + iB (t) + (t) iC (t) (4.5)
Vd (t) Vd (t) Vd (t)
The ratio on the right side between phase voltages and the DC-link voltage is called
the switching function sx (t)
vxN (t)
= sx (t) (4.6)
Vd
48
 4.1 – Calculation of DC and AC components of the DC-Link Current

from which an alternative expression for equation (4.5) can be derived:

Id (t) = sA (t) iA (t) + sB (t) iB (t) + sC (t) iC (t) (4.7)

Figure 4.1 can be taken as reference in order to have a clearer vision of the switching
function concept: a switching function is a logic signal with state 0 or 1 and the
transition between these states happens simultaneously with the transition of the
PWM control signal of each leg (Figure 4.1.b).

Figure 4.1. Construction of the DC-link current by means of switching func-

tions: (a)(i) inverter leg voltage, (a)(ii)fundamental component of leg voltage,
(a)(iii)sinusoidal current; (b) switching function; (c),(d),(e) DC-link current of the
three legs; (f) total DC-link current. [16]

The DC-link current of Figure 4.1.c is constructed by multiplying the sinusoidal

current of Figure 4.1.a with the switching function of Figure 4.1.b. The currents
49
 4 – Analysis of the DC-link Current

of Figure 4.1.d and Figure 4.1.e are the DC-link currents of the other two legs and
summed up with the one of Figure 4.1.c give rise to the total DC-link current of a
three-phase inverter.
Since switching functions are strictly related to the PWM technique implemented
for the inverter, for the choice made in Chapter 3, the switching functions of the
symmetric Space-Vector PWM must be found. Following the construction steps
of Figure 4.1 and taking into account equation 4.6, the switching functions of the
symmetric PWM are computed in the following way:
1. takes the phase leg reference voltages at the commutation poles of Figure 3.8;
2. compare each reference signal with a triangular carrier waveform;
3. each switching function goes in the high state when the amplitude of the
reference signal of each leg is higher or equal with respect the carrier, while it
goes in the low state in the opposite case.
Figure 4.2 shows an example of this procedure for a carrier frequency fSW = 60kHz
and an output frequency fout = 5kHz.

Figure 4.2. Example of switching function construction for leg A.

Multiplying the output currents with the switching functions, a theoretical eval-
uation of the DC-link current is obtained. Taking into account the specifications of
50
 4.1 – Calculation of DC and AC components of the DC-Link Current

Table 3.1 and imposing cos (φ) = 0.8 the leg A DC-link current for the three-phase
VSI can be evaluated (Figure 4.3) and, summing up the DC-link current of all the
legs (Figure 4.4), the total DC-link current reported in Figure 4.5 is obtained.

Figure 4.3. DC-link current of leg A.

Figure 4.4. DC-link current of the three legs.

51
 4 – Analysis of the DC-link Current

Figure 4.5. Total theoretical DC-link current of the inverter with fSW =
20kHz and fout = 50Hz.

4.2 Selection of the DC-link capacitor

In a three-phase two-level Voltage Source Inverter the input capacitor is used for
different purposes [29]:

• to supply the input pulsed current of the inverter;

• to reduce the spread of current harmonics into the DC source;

• to supply power during transient-peak and to protect the inverter from transient-
peaks of the DC-link voltage.

Important parameters in the selection of a capacitor are the operating voltage

and the working temperature because, as established by the Arrhenius Law, if the
working temperature is reduced the typical working life doubles for every 10◦ below
the rated temperature [55]. The analysis carried out in section 4.1 is sufficient as
first approximation but, in order to choose the right capacitor for the power ratings
of heavy-duty applications, he worst-case evaluation of the root mean square of
ripple DC-link current and a harmonic current evaluation are fundamental aspects.
The problem has been exhaustively resolved in [29] and in this section only the
relevant results for the design purposes of this thesis are reported.
The evaluation of a rms value of the inverter harmonic current depends on the
relationship between the space vectors of Table 2.1 and the segment of output
current used to build the DC-link current: different segments of the output current
correspond to different switching states and so to different sectors. The results are
52
 4.2 – Selection of the DC-link capacitor

obtained assuming a symmetric ideal three-phase voltage system, a balanced load,

a purely sinusoidal shape of the inverter output currents, linear modulation and
neglecting the dead-time. Under these assumptions, the expression of the global
rms value of inverter input current [29]
ó5
ma
6
Idrms = rms
ILN (1 + 4 cos2 (φ)) (4.8)
π
obtained considering only the fundamental components of the output phase current,
is valid in all the sector of the Space-Vector PWM.
As mentioned at the beginning of the Chapter, the inverter input current can
be seen as the superposition of two orthogonal component, the DC one coming
from the DC source and the AC one sink by the harmonic filtering system. In this
project, a capacitor is the selected harmonic filtering system, hence the rms value
of the AC component is the one of interest and it is given by [29]:

1 4 3
ó 5 3 4 6
rms
Id,AC = rms
ILN ma + − ma cos2 (φ) (4.9)
π π 2
In order to size the capacitance, the worst case condition of this current must be
identified; thus, the dependence of the ratio between the ripple DC-link current
and the phase current
rms
Id,AC
rms
ILN
from the power factor cos (φ) and from the modulation index ma is reported in
Figure 4.6 and Figure 4.7.

53
 4 – Analysis of the DC-link Current

Figure 4.6. Variations of ripple component of the DC-link current with respect to ma .

Figure 4.7. Variations of ripple component of the DC-link current

with respect to cos (φ).

54
 4.2 – Selection of the DC-link capacitor

From the analysis of Figure 4.6, the following conclusions can be derived:
• for a modulation index ma = 8/3π Ä 0.85 the dependence between power factor
cos (φ) and rms value vanish;
• the maximum rms value of the ripple DC-link current of Id,AC
rms
= 0.46ILN
rms
is
at ma =Ä 0.53 for cos (φ) = 1 (purely resistive load).

Other interesting considerations can be done taking into account Figure 4.7:

• until the value cos (φ) = 0.43 is reached, the maximum value of the rms ripple
current is obtained with the highest modulation index ma = 1;
• with more resistive load (cos (φ) near to one), the rms value increases and this
id due to the presence of larger harmonics at the load;
• with more inductive load (cos (φ) close to zero), The rms value increases with
the modulation index.
Putting together all the evaluations made in the previous statements, the theoretical
worst case rms value and the theoretical worst case conditions for the ripple DC-link
current is derived:
1. the worst case rms value is Id,AC
rms
= 0.46ILN
rms
= 0.46 · 60A = 27.6A;
2. the worst case modulation conditions are cos (φ) = 1 and ma Ä 0.53.
Theoretical results obtained from equation (4.9) approximate experimental result
with a error lower than 8% for the full range of modulation [29]. A further analysis
with the SIMULINK model of Chapter 3.1 can be helpful to further validate the
above conclusions; the simulation outputs are reported in Figure 4.8 and Figure
4.9, from which the theoretical worst case conditions are widely proven also from
the simulation.

55
 4 – Analysis of the DC-link Current

Figure 4.8. Simulation results of the SIMULINK model for dif-

ferent power factor cos (φ).

Figure 4.9. Simulation results of the SIMULINK model for different

modulation index ma .

56
 4.2 – Selection of the DC-link capacitor

One important step for the choice of a suitable DC-link capacitor is an evalua-
tion of the harmonic content and harmonic characteristics of the DC-link current.
This analysis is performed exploiting the MATLAB algorithm for the Fast Fourier
Transform which is dependent on the time resolution of the simulation and on the
periodicity of the overall waveform [23]. The discrete Fourier Transform code re-
turns a double-sided spectrum, thus the code used in this Thesis, listed in Appendix
A.3, shows how to carry out a single-sided spectrum from a double-sided one.
The DC-link current of the three-phase Voltage Source Inverter is stored into
the workspace during the simulation thanks to the SIMULINK to workspace block,
visible Figure B.13 with the name IDC. It is evaluated with the parameter values
show in Table 4.1, that means taking into account the project specifications (Table
3.1) under worst-case conditions.

Max. DC bus voltage Vd 700V

Max. Output Power Po ut 20kW
Max. DC current Id 29A
Max. Switching Frequency 20kHz
Output Frequency fout 50Hz
Power Factor cos (φ) 1
Max Phase Current 60A
Modulation index ma 0.53
Table 4.1. Parameter values for the evaluation of the DC-link current spectrum.

In Figure 4.10 the total DC-link current is reported while the spectrum of the
ripple current is showed in Figure 4.11.

Figure 4.10. DC-link current waveform of the three-phase VSI under

RMS worst-case conditions.

57
 4 – Analysis of the DC-link Current

Figure 4.11. Spectrum of the three-phase VSI DC-link current under

RMS worst-case conditions.

From Figure 4.11, one of the benefits of the Space-Vector technique is visible:
the first harmonic component of the output and of the carrier are suppressed be-
cause harmonic energy of the DC-link current are translated to higher frequency.
Furthermore, a significant part of this energy is located around the sideband of
second switching frequency harmonic. For the design purposes of this Thesis, the
largest harmonic component has a frequency two times higher than the switching
frequency and its peak amplitude is of 34.75A.
Most of the specifics for the DC-link capacitor has been derived, the last step is
the minimum capacitance and minimum Equivalent Series Resistance (ESR) esti-
mation and it is derived by imposing the maximum tolerable ripple of the DC-link
voltage. Also in this case, the design is assisted by a MATLAB script (Appendix
A.3): it derives the specifications for ESR and capacitance, and furthermore, by set-
ting the variable nCAP it derives the specifications for the combination of different
capacitors when the use of only one is not suitable or advisable.
The steps performed by the script are:

1. simulation of the three-phase VSI;

2. DC-link current estimation with the specifics of Table 4.1;

3. evaluation of DC and AC component of this current at regime;

4. computation of the maximum ripple of AC component of the DC-link current;

58
 4.2 – Selection of the DC-link capacitor

5. capacitance and ESR estimation in function of the ripples.

The outputs of the code execution are reported in Figure 4.12, 4.13 and 4.14.

Figure 4.12. Capacitance value versus the DC-link voltage ripple.

Figure 4.13. ESR value versus the DC-link voltage ripple.

59
 4 – Analysis of the DC-link Current

Figure 4.14. DC-link voltage versus the capacitance value.

The goal imposed for the capacitor selection is to obtain a DC-link voltage ripple
of about 3%-4% of the DC-link voltage, that corresponds to a maximum ripple of
21V. As Figure 4.12 and 4.14 shows, the minimum capacitance must be of about
120µF and the maximum ESR should be of 580mΩ (Figure 4.13).
Since, at least for the moment, the option of custom-made capacitor must be
not taken into account, the capacitor should be selected between the available
ones in the market. A capacitor with high capacitance value suitable for high
voltage application is heavy and expensive, hence a solution of four parallel DC-
link capacitors is adopted and the specifications for each of them are listed in Table
4.2.

Min. Capacitance 30µF

Max. ESR 2.5Ω
Min. Operating Voltage 900V
Min. rms Current 10A
Table 4.2. Constraints for the selection of DC-link capacitors.

After a careful market analysis, the selected capacitor is a EPCOS/TDK

B32778G0406. It is a film capacitor with a dielectric of polypropylene that al-
lows to sink high rms DC-link currents with low self-heating, and it performs well
over the temperature range and frequencies in power electronics applications; fur-
thermore, it is a metallized capacitor, hence its electrode system is composed by
a thin layer of vapour deposited aluminium, zinc or alloy blend (aluminium/zinc)
60
 4.3 – Overview of alternative harmonic filtering solutions

[12]. At the present, film technology is the best passive solution for these types of
applications until ceramic capacitors will improve energy density and capacitance
stability.

4.3 Overview of alternative harmonic filtering so-

lutions
The main problems of a passive harmonic filtering solution, such as film capacitors,
are [12]:

• weight;
• volume;
• lifetime.

The alternative solutions for the filtering problem are active systems or different
modulation techniques.

Active solutions
As mentioned in Chapter 1, for heavy-duty applications, stand-alone (off-the-grid)
converter are needed and this makes unsuitable the use of Active Power Filters
(APF) [41]. Instead, a possible approach to decrease electro-magnetic interference
(EMI) and radio-frequency interference (RFI) noises is the use of soft switching
technique instead of hard switching one. Soft switching techniques consist of circuits
called snubber cells, which allow switching devices to commutate at zero voltage
(ZVS) or zero current (ZCS). An example of these type of techniques is the use of
parallel resonant DC-link (PRDCL) in order to provide soft switching and PWM
operation [44]. The PRDCL circuit is reported in Figure 4.15 and it is composed
by a main switch S1 with an auxiliary transistor T2 , an auxiliary diode D2 and a
resonant tank composed of a centre-tapped inductor Lr and a capacitor Cr . The
working principle of the PRDCL soft switching inverter is fully described in [44],
here only the advantages of this solution are reported: increased efficiency, very
low current stresses on all the circuit components, zero crossing on the dc-link
voltage with PWM capability and soft-switching operation of the inverter and so
the current harmonics through the resonant tank are very limited and pushed to
high frequency, meaning that a capacitor should filter them easier.

61
 4 – Analysis of the DC-link Current

Figure 4.15. PRDCL soft switching inverter. [44]

The recognized drawback of the topology presented in Figure 4.15 is the voltage
stress on the main switch S1 and on the auxiliary transistor T2 : it is twice the
voltage of the DC source and this can be a big issue in automotive or heavy-duty
applications.
Another alternative circuit topology consists of a shunt-connected converter to
provide a current compensation in order to reduce the current passing through
the capacitor. The active filter implemented in [8] behaves as a current-fed con-
verter connected in parallel to the DC-link capacitor which provide a current equal
in magnitude and opposite in phase with the purpose to compensates the ripple
component of DC-link current. This compensating current is constructed with a
time-domain technique that easier to implement with respect a frequency-domain
technique but it leads to an overall attenuation of harmonics rather than to an
individual frequency component attenuation. The simulation results are reported
in [8] but no informations about practical feasibility, power density or costs are
reported [35]. From these results it is evident that this solution comports higher
switching frequency for the active filter and, furthermore, the filter inductor should
sink larger currents.

Modulation solutions
In Chapter 2 has been described as different modulation techniques leads to differ-
ent characteristic of the output spectrum and as a consequence they modify also
the DC-link current spectrum. Furthermore, it was described the degree of freedom
of a Zero Space Vector Placement technique such as the Space-Vector PWM: the
location and duration of the null vectors within one period TSW can be arbitrary
selected. The symmetric SV PWM technique adopted in this project allows ob-
taining a good trade-off between losses and output distortion; in this case, the goal
is to combine the space vectors (Table 2.1) in order to reduce the rms value of
the DC-link current or in order to push the spectrum at higher frequencies. The
62
 4.3 – Overview of alternative harmonic filtering solutions

Extended Double Carrier (EDC) PWM strategy, fully explained in [45], has the
main feature of reducing the harmonic content of the DC-link current.
The pillar of Extended Double Carrier modulation technique is the utilization
reduction of the zero vectors þv7 and þv8 in order to reduce the commutations of the
DC-link current to zero by constructing the modulating vector from non-adjacent
sequences of space vectors and the construction difference with respect the classic
SV PWM is reported in Figure 4.16 while the difference in terms of DC-link current
produced is showed in Figure 4.17.

Figure 4.16. Modulating vector construction: on the left the classic SV PWM
approach, on the right the EDC PWM approach. [45]

Figure 4.17. Variation of inverter input current during a switching period for SV
PWM and EDC PWM. [45]

The modulation sequence of the Extended Double Carrier PWM technique vary-
ing with respect modulation index ma and power factor cos (φ), thus a closed-form
63
 4 – Analysis of the DC-link Current

equation for the rms value of the DC-link current is difficult to derive; however, the
authors of [45] show that EDC modulation provides a 40% reduction of the rms
value with respect of SV PWM when the power factor is close to one (worst case
condition in this project assumptions). The drawback of this modulation technique
lies in an increment of the THD factor (2.6).

64
Chapter 5

Design of the inverter

In this Chapter all the design aspects of the three-phase Voltage Source Inverter
are described, furthermore a discussion and explanation about different decisions
adopted is faced up. Taking into account the fact that the application field of
this inverter is the heavy-duty sector, the only two energy sources available for
the system are a high-voltage battery pack and a low-voltage battery, for instance
the car one. This mean that efficient power supplies are needed in order to drive
the switching devices with the adequate voltage levels. Moreover, the safety aspect
must be considered and so all the components have to guarantee the right insulation
level between high-voltage and low-voltage world in order to obtain a safety system
for the final user.
Since this is the starting point of a long-term project, only new and performant
devices will be used for the design in order to have the certainty to not implement
a system with electronic components obsolete within a few months.

5.1 Selection of the electronics components

Until this point two electric components have been selected, the switching devices
in Chapter 3 and the DC-link capacitor in Chapter 4; they are, respectively, a SiC
module from Cree/Wolfspeed identified as CCS050M12CM2 and the EPCOS/TDK
metallized polypropylene film capacitor B32778G0406.

Gate driver
Feeding the power MOSFET module with the right value of voltage is crucial to
obtain the best performance, hence a gate driving circuit is needed for:
• minimize turn-on and turn-off time, that means reduce the working time in
active region where power dissipation is large;
• interface between the control circuit and the power switches,
65
 5 – Design of the inverter

• supply the right amount of current in order to charge the gate capacitance;

• provide electrical isolation; with the voltage rating of this project reinforced
isolation is needed [28];

• protect the gate from under voltages and over voltages.

The selected gate driver is the Texas Instruments ISO5452-Q1, a reinforced

isolated AEC-Q100 qualified gate driver with split outputs and active protection
features. It has the high Common Mode Transient Immunity (CMTI, i.e. maximum
tolerable rate of rise or fall of the common mode voltage applied between two
isolated circuits) needed from fast switching devices such as GaN or SiC MOSFETs
and its split outputs (Pin 4 and Pin 6 of Figure 5.1) provide a peak source current
of 2.5A and a peak sink current of 5A; the higher sink capability allows to minimize
the turn-off, usually the critical phase for power losses.

Figure 5.1. Pin configuration of the ISO5452-Q1.

Important active protection features are the desaturation and Miller clamp pins
(respectively Pin 2 and Pin 7 in Figure 5.1): the desaturation fault detection recog-
nizes when the transistor is in an over-current condition and starts a soft-turn-off
procedure, while the Miller clamp feature prevents the transistor from uninten-
tionally turning on because of current induced from its collector to its gate due
to Miller effect. Moreover, its reinforced isolation barrier is compliant with the
standards provided in ISO61800-5-1 for variable speed drives. In order to properly
drive the high side transistor, the driving circuit must be applied with reference to
the source of the MOSFET and each source must have a separated and isolated
ground.
66
 5.1 – Selection of the electronics components

Power supply
In order to obtain the best performances from a SiC MOSFET, gate voltage must
be kept as high as possible, within the specified range, in order to operate the
devices at a lower rDS,on , so that the conduction losses can be minimized. Looking
to the data-sheet of CCS050M12CM2, the gate-source voltage levels needed are:
vGS,on = +20V (5.1)
vGS,of f = −5V (5.2)
The ISO5452-Q1 can handle voltages from −17.5V to +35V, but the right values
for the vGS must be derived from the low-voltage battery and, for this project, the
car battery with nominal voltage of 12V is used as reference. The minimum value
considered is of 9V while the maximum one is 24V. Thus, an isolated power supply
must be employed.
Since the aim of the project is to obtain a high power density and high efficient
system, the Texas Instruments LM5180-Q1 is the best choice because it has
an integrated 100-V power MOSFET and internal compensation. In fact, it is a
primary-side regulated (PSR) flyback converter, hence the isolated output voltage
is sampled from the primary-side flyback voltage, eliminating the need for an opto-
coupler, voltage reference or third winding from the transformer for output voltage
regulation. As the ending part of the component names states, the LM5180-Q1 is
AEC-Q100-qualified and this increase its reliability.
In order to properly drive the six gate driving circuits, at least four different
reference voltages must be supplied: one for the low-side driver and three for the
high-side ones, because, as explained in Chapter 2, only the low-side switches are
connected to the same potential and their control signals does not need to be
isolated. There are many isolated DC-DC converters that could be used as power
supply for the gate drive but, in this project, a flyback converter has been chosen
because it allows to obtaining multiple output. The advantage is that only one
converter is sufficient and this allows to further maximize the power density.
The LM5180-Q1 flyback controller works in three different modes depending on
the load:
1. at high loads, it operates in Quasi-Resonant Boundary Conduction Mode
(BCM) with the power MOSFET that turns on when the current in the sec-
ondary winding reaches zero to minimize switch-on losses; as the load is de-
creased, the peak current decreases and the frequency increases to maintain
BCM operation;
2. at medium loads, the LM5180-Q1 operates in Discontinuous Conduction Mode
(DCM), where it clamps the maximum switching frequency to 350kHz;
3. at light loads, the system operates in Frequency Fold-Back Mode (FFM), and
the switching frequency decreases as the load current is reduced.
67
 5 – Design of the inverter

Another feature that makes the LM5180-Q1 a well suited choice is the wide in-
put swing from 4.5V to 65V. In fact, automotive world is moving towards 48-volt
electrical systems, with the 12-volt battery used just for traditional lighting and in-
fotainment while the 48-volt battery supplies more power-hungry components such
as power steering, power brakes, water pump, radiator cooling and the low-voltage
part of the motor driver. If in a further step of the project the FLAG-MS company
will decide to move towards a 48-volt solution, only few passive components will be
changed in the design.

Figure 5.2. Modes of operation for the LM5180-Q1.

Current sense amplifier

Power inverters need high-resolution, accurate, isolated phase current sensing for
control loop because it allows to keep under control the current supplied to the
motor load and so its torque and angular velocity can be estimated and regulated.
Furthermore, the real-time monitoring of the output current allows to prevent fault
or over-current transient which could lead to electrical component breakdowns.
There are different options to measure the output current:

• shunt resistors;

• hall-effect sensors;

• flux-gate sensors;
68
 5.1 – Selection of the electronics components

• current transformers.

The reasons to choose the last three options are the high measurement range and the
intrinsic galvanic isolation. the drawback consists in lower linearity and bandwidth
combined with higher measurement drift with respect a shunt resistor; furthermore,
they are more expensive. Taking into account these features, in this project the
current sensing is made with a shunt resistor connected to a small reinforced isolated
amplifier in order to eliminate the drawback of a resistor-based sensing.
Looking on the available modern products on the market, a precision isolated
amplifier with a capacitive isolation barrier is selected: the Texas Instruments
AMC1302-Q1. Its input are optimized for direct connection to shunt resistors
and its low input voltage range of ±50mV allows to reduce the power dissipation
through the shunt.

Peripheral circuits
The main electric components have been chosen, but other relevant inverter parts
must be analysed because:

1. the low-voltage logic of ISO5452-Q1 circuits work with voltage level from 2.25V
to 5.5V;

2. the swing of the low-voltage supply of the AMC1302-Q1 amplifier is from 3V

to 5.5V;

3. the high-voltage supply of the AMC1302-Q1 must be in a range between 3V

and 5.5V.

For the low-voltage sides, a level of 5V is selected because the system will be
tested in a noisy environment and this voltage level allows a higher immunity.
As for the flyback, the 5V must be generated by the low-voltage battery and, in
order to guarantee a possible future 48 volt compatibility, the Texas Instruments
LM46002-Q1 is used. It is a synchronous buck converter capable of driving up
to 2A of load current with an input voltage range of 3.5V to 60V. This converter
is internally compensated fixed frequency peak current mode control, in order to
ensure a higher integration level in order to achieve a better power density. The
peak current command is adjusted with a voltage feedback loop and the converter
runs with fixed switching frequency in Continuous Conduction Mode (CCM) but,
in the case of lighter load, it can operates with Discontinuous Conduction Mode
(DCM) and Pulse Frequency Modulation (PFM) mode to achieve high efficiency
across all the load ranges [10].
The use of a power converter to step-up a voltage is the best choice from the point
of view of efficiency and voltage stability but the price to pay is a higher space usage.
The use of only one LM46002-Q1 allows to supply the low-voltage side of all the
69
 5 – Design of the inverter

six ISO5452-Q1 and of all the three current sensing circuit, thus the greater surface
used is justified because huge amount of current are sink from all these circuit
together. For what concerns the high-voltage side of AMC1302-Q1, the same buck
converter can’t be used because it is on the opposite side of the barrier; moreover,
since the current need is low, a cheaper and smaller solution should be used. In a
typical traction inverter application, the high-voltage side power supply for these
amplifiers is derived from the floating power supply of the high-side gate driver and
to minimize noises a low-cost low-dropout (LDO) regulator is used. A small device
of this type, capable to handle an input voltage of +20V is the Texas Instruments
TPS7B6950-Q1 because, in a package with sizes of just 2.90mm×1.60mm, it is
capable to integrate short-circuit and over-current protections. Also in this case a
voltage of 5V is selected.

5.2 Sizing of the components

All the electric devices selected in the previous section need external components to
work for proper, such as decoupling capacitors or feedback resistors. All the aspects
concerning the dimensioning of these components are described in this section.

Gate driver
One of the advantages of adopted gate driving circuits is that the input control
is in CMOS technology and, unlike an optocoupler, it can be directly driven by
a microcontroller without external current drivers and biasing circuitry. So, the
design requirements include decoupling capacitors on the input and output supplies,
a pull-up resistor on the common drain FLT and RDY output signals (Figure 5.1),
and a high-voltage protection diode between the MOSFET drain and the DESAT
input.
Starting from the bypass capacitors, the recommended one at input supply VCC1
is of 0.1µF while at output supply it is of 1µF. The open drain outputs FLT
and RDY are passive pulled-up with a 10kΩ resistor. The DESAT pin must be
protected with a 1kΩ resistor because switching inductive loads, such as motors,
generates large instantaneous forward voltage transient leading to large negative
voltage spikes on the DESAT pin which draw significant current out of the device,
hence a resistor is needed to limit this current. A further protection is achieved
with a Schottky diode, that should be properly selected (Figure 5.3) in order to
clamp the DESAT input to the potential of GND2 at low voltage levels.
During the short transition time when the transistor is switching a high voltage
ramp rate occurs across it, leading in a current

dVDS
ICHARGE = CDST (5.3)
dt
70
 5.2 – Sizing of the components

that charges the diode capacitance CDST . In order to avoid false DESAT triggering
a fast switching diode must be used, but its capacitance builds a voltage divider
with the blanking capacitor CBLAN K .

Figure 5.3. Protection of DESAT pin with a resistor RS and a Schottky Diode.

Since that this capacitance is recommended of 220pF, a BAT54W Schottky

Diode with a 30pF is used; hence, the collector voltage transients appear at DESAT
attenuated by
CBLAN K
1+ (5.4)
CDST
Since the voltage at the DESAT pin is the sum of the Schottky diode forward-
voltage VF W and of the MOSFET vDS , the drain-source voltage level which triggers
a fault condition ca be setted by implementing more than one diode DDST :

VDS,f ault = 9V − n · VF W (5.5)

71
 5 – Design of the inverter

where n is the number of DESAT diodes. From the data-sheet of the CCS050M12CM2,
the typical output characteristics can be evaluated (Figure 5.4) and the desatura-
tion voltage level is selected as 1.3V in order to obtain a maximum output current
of 60A (Table 3.1). Thus, taking into account equation (5.5), a SMBJ5341B
Zener diode with a voltage drop of 6.2V is added in series to the diode DDST , that
is one STM STTH112-Y with a maximum forward voltage of 1.6V.

Figure 5.4. Typical output characteristics of the Cree/Wolfspeed

CCS050M12CM2 for TJ = 25◦ .

The crucial part of the gate driver design is the right selection of the gate resistor
RG , and in the ISO5452-Q1 they are two (RGL and RGH in Figure 5.3) because of
the split outputs. An optimum gate resistor selection is key for a high performance
design because [4]:
• small resistor values will result in an overshoot in the gate driving voltage but
also result in faster turn-on speed;
• high resistor values will overdamp the oscillation and extend the switching
times without offering much benefit for the gate drive design.
Looking on the CCS050M12CM2 data-sheet, the recommended value for the gate
resistor is of 20Ω and this means that the source and sink current of the gate driver
must be of
vGS,on
Isource = = 1A (5.6)
RG
vGS,of f
Isink = = 0.25A (5.7)
RG
72
 5.2 – Sizing of the components

and they are inside the current range of the ISO5452-Q1.

At this point, the maximum available dynamic output power POD,max can be
estimated. The maximum allowed total power consumption PD of each gate driver,
reported on the data-sheet, is:
PD = PID + POD + POL = 251mW (5.8)
with
PID = VCC1,max ICC1,max = 5.5V · 4.5mA = 24.75mW (5.9)

POD = (VCC2 − VEE2 ) · ICC1,max

= (vGS,on − vGS,of f ) · ICC1,max (5.10)
= 25V · 6mA = 150mW
hence, the maximum available dynamic output power is:
POD,max = PD − PID − POD = 76.25mW (5.11)
while, the actual dynamic output power under worst case condition is:
A B
ron,max rof f,max
POL,wc = 0.5fSW QG · (vGS,on − vGS,of f ) · +
ron,max + RG rof f,max + RG (5.12)
= 12.5mW
where fSW is the maximum switching frequency of Table 3.1, ron,max = 4Ω is the
worst case output resistance in the on-state, rof f,max = 2.5Ω is the worst case
output resistance in the off-state.

Figure 5.5. Typical gate charge characteristics of the Cree/Wolfspeed

CCS050M12CM2.

73
 5 – Design of the inverter

The term QG is the power device gate charge, equal to 180nC, derived from the
data-sheet gate charge curve (Figure 5.5): it represent the charge from the origin
to the point on the curve at which the driving voltage vV GS equals the desired gate
voltage of the device; it is a key parameter to evaluate the time needed to reach
the actual gate voltage.

Flyback power supply

The LM5180-Q1 requires only a few external components to convert from a 12-
volt battery to more isolated output rails (Figure 5.6): a resistor RF B connected
between the SW and FB pins set the fixed output voltage, the input voltage turn-
on and turn-off thresholds are established by RU V 1 and RU V 2 and a transformer is
needed to generate the multiple output rails.

Figure 5.6. Schematic of the power supply circuit. [52]

The EN/UVLO input of the LM5180-Q1 device is enabled when the input rising
voltage is higher than 1.5V with a hysteresis of 50mV (Figure 5.7). Imposing to
turn-on the device when the rising input voltage reaches VIN,ON = 9V and to turn-
off when the falling input voltage reaches VIN,OF F = 7.5V , the resistance value can
be computed:
VU V LO2
VIN,ON · − VIN OF F 9V · 1.45V
RU V 1 = VU V LO1
= 1.5V
= 260kΩ (5.13)
IU V LO 5µA
VU V LO1
RU V 2 = RU V 1 = 20kΩ (5.14)
VIN,ON − VU V LO1

The component that influences the most the next design steps is the transformer,
because find it available on the market with four outputs winding, with the right
74
 5.2 – Sizing of the components

value of primary inductance and compliant with the required insulation standards
has resulted to be difficult. Fortunately, Wurth Elektronik has on the catalogue
the 750343953, a custom-made transformer for Texas Instruments that can be
ordered from anyone; its main characteristics are reported in Table 5.1.

Primary inductance LP RI 47µH ± 10%

Primary DC resistance 0.08Ω
Saturation current 1.6A
Primary-to-secondary turn ratio NP S 1
Table 5.1. Wurth Elektronik 750343953 characteristics.

The primary inductance of the transformer determines the modes of operation

of the converter; taking into account that the LM5180-Q1 has a minimum off- time
TOF F,min of 500ns, the magnetizing current should not decrease to zero in minor
time periods, hence:

(VOU T + VF ) · TOF F,min · NP2 S

LP RI ≥ Ä 46µH (5.15)
ISW,P Kmin · NP S

where VOU T = 25V is the sum of the on-state and off-state gate voltages, VF is the
forward voltage of the output rail diode and ISW,P Kmin = 0.27A is the minimum
peak primary current of the LM5180-Q1. Thus, the primary inductance of the
750343953 is sufficient for this application.

Figure 5.7. Programmable input voltage UVLO with hysteresis of the LM5180-Q1.

The duty cycle in BCM is given by:

(VO + VF ) · NP S
D= = 0.68 (5.16)
(VO + VF ) · NP S + VIN
75
 5 – Design of the inverter

The maximum peak current on the integrated MOSFET allowed is 1.45A, while
the actual value will be:
2 · IOU T,tot · VOU T 2 · 6 · 0.025A · 25V
ISW,P K = = = 1.081A < 1.45A (5.17)
VIN · D · η 12V · 0.68 · 0.85
where VIN is the typical 12V-battery voltage, η Ä 85% is the estimated efficiency for
a flyback converter with multiple outputs and IOU T,T OT is the total output current.
The value of IOU T,T OT is selected considering the power to supply to each gate
driver:
PG = VCC QG fSW + (QG · fSW · ÑVG ) + (Cgs · fSW · ÑVG2 )
= 250mW + (180nC · 20kHz · 25) + (8nF · 20kHz · 252 ) (5.18)
= 440mW
where ÑVG = 20V − (−5V) = 25V and Cgs = 8nF is the MOSFET capacitance
between gate and source evaluated from the data-sheet. Considering a safety margin
value, the value of PG selected is of 625mA, hence the output current provided to
each gate driver is:
PG 625mA
IOU T = = = 25mA (5.19)
ÑVG 20V
and the total output current IOU T,T OT will be six times the current of each gate
driving circuit IOU T .
The built-in MOSFET is rated at 100 V; in the off cycle, when the diode of the
output rail is on, the actual voltage vDS across it is:
VDS,max = VIN,max + VREF + Vring = 24V + 25.5V + 25V = 74.5V < 100V (5.20)
where VIN,max = 24V , Vring = 25V is the spike in voltage due to resonance and
VREF is the primary voltage reflected across the transformer:
VREF = NP S · (VOU T + VF ) Ä 25.5V (5.21)
When the integrated MOSFET is on, the voltage across the output rail diode must
be taken into account:
VIN,max
Vdiode = VOU T + + VD,spike = 25V + 24V + 25V = 74V (5.22)
NP S
The output voltage is determined by the ratio between RF B and RST ; hence, fixing
RST = 12.1kΩ:
(VOU T + VF ) · NP S
RF B = = 257kΩ (5.23)
0.1mA
The LM5180-Q1 device has a thermal-compensation circuit in order to adjust the
feedback with respect the thermal coefficient of the flyback diode. Selecting a
B2100A-13-F as flyback diode:
RF B 3mV ◦C−1 257kΩ 3mV ◦C−1
RT C = = = 771kΩ (5.24)
NP S TCdiode 1 1mV ◦C−1
76
 5.2 – Sizing of the components

Important electric components for switching devices are the capacitors. In order to
keep under control the input voltage ripple, the following relation must hold:
1 22
ISW,P K D · 1 − D
2
CIN ≥ =Ä 2µF (5.25)
2fSW ÑVIN
where the imposed ÑVIN is the 5% of VIN . Such as for the inverter, in order to
select the input capacitor the rms current must be computed (Chapter 4):
ó
DISW,P K 4
rms
IIN = − 1 Ä 0.45A (5.26)
2 3D
For what concerns the output voltage ripple and to limit it to the 1% of the output
voltage, the right output capacitance must be evaluated:
IOU T LP RI ISW,P K
COU T ≥ =Ä 60µF (5.27)
ÑVOU T VIN
furthermore, the capacitor must be selected with a rms current higher than:

2NP S ISW,P K
ó
rms
IOU = IOU T − 1 Ä 0.16A (5.28)
T
3IOU T
The 25V generated at the four output rails must be split into a positive voltage
of 20V and a negative one of −5V. This can be done in several ways but the one
adopted in this project is to use only one winding and to divide the voltage with a
Zener polarized by a resistor (Figure 5.6), because the use of two winding for each
rail is unfeasible because of the usage of space, considering also the requirements
of high-voltage insulation spacing. The less critical bias with respect the accuracy
level is the negative voltage one because its role is only to prevent false switch turn-
on during high-voltage transient. Since the positive bias is important to turn-on
faster the SiC MOSFET, the Zener diode is used to set the 20V while the resistor
with a voltage drop of 5V is used to polarize the diode; selecting a Zener with a
knee-current of 50µA:
5V
R= = 100kΩ (5.29)
50µA
Lower knee-currents mean higher resistance leading to lower power losses across it.

Current sense amplifier

The first component to choose is the shunt resistor to sense the output phase
current; using the Ohm’s law:
VSHU N T 50mV
RSHU N T = = Ä 0.8mΩ (5.30)
ILN 60A
77
 5 – Design of the inverter

and the power dissipated through it is:

2
VSHU
PSHU N T = NT
= 3.125W (5.31)
RSHU N T
Thus, the Isabellenhutte BVS-M-R0007 is selected as shunt resistor. It has a
resistance of 0.7mΩ with a maximum allowed power dissipation at 100◦ of 5W.
The recommended decoupling capacitors for both the high-voltage and low-
voltage sides are:
• A 0.1µF capacitor placed as close as possible to the VDD pins.
• An additional capacitor from 1µF to 10µF for filtering lower-frequency noise.
In this project a 2.2µF capacitor is employed.
Furthermore, an input RC filter is recommended in order to minimize the noise.
The cut-off frequency of this differential fil-
ter is:
1
fc (Hz) = (5.32)
2π 2 R CDIF F
thus, selecting R = 50Ω and CDIF F = 0.1µF, a
differential cut-off frequency fC Ä 30kHz is ob-
tained. For what concerns the common-mode
capacitance:
CDIF F
CCM Ä = 0.01µF (5.33)
10
hence, CCM = 0.022µF is selected.
These passive components must be carefully
chosen because their tolerance values change
the Common Mode Rejection (CCM) of the fil-
ter according to the following relation:
RT OL (%) + CT OL (%)
CM R(dB) = 20 log10 ( )
100
f
Figure 5.8. RC filter. + 20 log10 ( )
fC
(5.34)

12V-to-5V step-down converter

The switching frequency of LM46002-Q1 device can be setted by means of the
resistor RT (Figure 5.9); selecting a switching frequency fSW of 500kHz:
40200 40200
RT (kΩ) = − 0.6 = = 83.2kΩ (5.35)
fSW 500kHz
78
 5.2 – Sizing of the components

Once that the switching frequency is fixed, the buck converter inductance can be
computed:
(VIN,max − VOU T ) · D (VIN,max − VOU T ) · D
≤ Lmin ≤ (5.36)
0.4 · fSW · IOU T 0.2 · fSW · IOU T
10µH ≤ Lmin ≤ 20µH (5.37)
where:
VOU T 5V
D= = = 0.21 (5.38)
VIN,max 24V
IOU T = 2A (5.39)
A higher inductance value gives lower ripple current and so lower output voltage
ripple with the same output capacitors; the drawback is the higher size of the
inductor. With the purpose to minimize the ripples, an inductance value of L =
18µH is adopted in this Thesis.

Figure 5.9. Schematic of the LM46002-Q1.

Another important parameter in the selection of the inductor is the rated satu-
ration current:
(VIN − VOU T ) · D
Iripple = Ä 500mA (5.40)
L · fSW
Iripple
IL,P K = IOU T + = 2.25A (5.41)
2
79
 5 – Design of the inverter

It is advised to select an inductor with a larger core saturation margin and prefer-
ably a softer roll off of the inductance value over load current. Thus, a well suited
inductor for the application is the Coilcraft MSS1278T-183ML.
In order to choose the output capacitor, the output voltage ripple must be
analysed and it is composed of two parts, one caused by the inductor current ripple
through the ESR of the output capacitors and the other by the inductor current
ripple charging and discharging the output capacitors:

ÑVOU T,ESR = ÑIL ESR (5.42)

ÑIL
ÑVOU T,ESR = (5.43)
8 fSW COU T
Thus, the minimum value for the output capacitance and the maximum value for
the ESR are given by:
1
CA B D
r2
COU T ≥ D + (1 − D) · (1 + r) Ä 20µF (5.44)
fSW · r · ÑVOU T,ESR /IOU T 12

1−D 1
3 4
ESR ≤ + 0.5 Ä 0.25Ω (5.45)
fSW COU T r
where:
ÑIL
r= (5.46)
IOU T
Furthermore, looking on the data-sheet, the recommended output capacitance
should be higher from the value obtained from equation (5.44) and smaller than
1mF, in order to limit potential potential output voltage overshoots as the input
voltage falls below the device normal operating range. Thus, two capacitor of 22µF
connected in parallel are adopted.
Another capacitor to select is the feed-forward one. The LM46002-Q1 is inter-
nally compensated but to improve the phase margin the capacitor CF F is used,
added in parallel with RF BT (Figure 5.9):

1 1
ó
CF F = = 100pF (5.47)
2πfx RF BT (RF BT /RF BB )
where the recommended RF BB is 250kΩ; RF BT is chosen of 1MΩ to minimize losses
and because
VF B
RF BB = RF BT (5.48)
VOU T − VF B
Instead, the term fx is equal to:
4.35
fx = = 17.5kHz (5.49)
VOU T COU T
80
 5.3 – Estimation of the efficiency

Every LM46002-Q1 design requires a bootstrap capacitor and the recommended

one is CBOOT = 0.47µF and it should be a high-quality ceramic type with X7R
or X5R grade dielectric for temperature stability. Moreover, the VCC pin is the
output of an internal LDO and to ensure its stability a capacitor of at least 2.2µF
must be connected close to it. The input of this LDO is the BIAS pin and a ceramic
capacitor of 4.7µF is connected close to it to work as input LDO capacitor.
The VIN pin requires high-frequency input high-quality ceramic capacitor with
dielectric of type X5R or X7R, and the recommended value for the total capacitance
is from 4.7µF to 10µF. Furthermore, a resistor of 10kΩ between this pin and the EN
one must be placed, with the purpose to obtain the recommended rising threshold
of 2.1V.
Since the input voltage can be higher than 12V, the PGOOD pin should be left
floating. For what concerns the pin SS/TRK, if it is floating a soft-start time of
4.1ms is used; instead, in this project, it is loaded with a capacitance of 0.044µF
because:
CSS 0.044µF
tSS = = = 20ms (5.50)
ISS 2.2µA

20V-to-5V LDO
The only two components to size for this small LDO are the input and output ca-
pacitors. The output capacitor should be ceramic with a capacitance value between
2.2mF and 100mF with a ESR value between 1mΩ and 2mΩ. The selected one is
a ceramic capacitor of 3.3µF with a ESR of 1.3mΩ. For what concerns the input
capacitor, a minimum value of 0.1µF must be implemented to better the transient
performance; hence, a capacitor of 10µF is selected for this LDO.
The maximum power dissipation of this device is:

PLDO = IOU T,max · (VIN − VOU T ) = 0.150A · (20V − 5V) = 2.25W (5.51)

5.3 Estimation of the efficiency

Once that all design steps have been performed, a first overestimation (some aspects
are neglected, such as the power dissipation due to the ESR of the capacitors) of
the inverter efficiency can be done.
The power dissipated in one of the six transistors and in each diode of the module
is reported in Table 3.5, thus:

PD,module = 6 · (51.4272W + 24.6259W) Ä 456.4W (5.52)

It can be noticed that the maximum power dissipated from MOSFETs only is:

PD,M OS = 6 · 51.4272W Ä 309W (5.53)

81
 5 – Design of the inverter

and it is the same of the one declared on the data-sheet, hence a further proof for
the validity of the MATLAB/SIMULINK model is found.
The power dissipation due to the LM46002-Q1 buck converter, considering an
achievable efficiency of the 90%, is:
IOU T · VOU T 2A · 5V
PD,buck = = Ä 11.2W (5.54)
0.9 0.9
For what concerns the flyback converter, having already considered an achievable
efficiency of the 85%:
IOU T,T OT · VOU T 625mW
PD,f lyback = = Ä 800mW (5.55)
0.85 0.85
Instead, the current sense amplifier has a very low total power dissipation PD,sense
of 98.45mW, but the power dissipated of 3.125W through the shunt is much higher
and not negligible.

Figure 5.10. Maximum power dissipation for the MOSFETs of the Cree/Wolf-
speed CCS050M12CM2 with respect case temperature.

Finally, the overestimated total power losses of the system are:

POU T PIN − PD,T OT
η= 100 = 100
PIN PIN
PIN − (PD,module + PD,buck + PD,f lyback + PLDO + PSHU N T + PD,sense )
= 100
PIN
20kW − (456.4W + 11.2W + 800mW + 2.25W + 3.125W + 98.45mW)
= 100
20kW
Ä 96%
(5.56)

82
Chapter 6

Prototype
In this Chapter, the circuits designed as described in Chapter 5 are implemented
in a prototype with the aim to validate the design steps, so the next step is to
verify if these components can be implemented in the high-power system of this
application. The best way to proceed in this primordial phase of the three-years
project is step-by-step, which are:
1. verify the correct design of the flyback power supply;
2. verify the correct design of the gate driving and peripheral circuits;
3. verify the correct design of the current sensing circuit;
4. verify that the selected capacitor is able to filter the current harmonics;
5. verify that the selected SiC module is capable to handle the specifications of
Table 3.1;
6. verify that the complete system is suitable to drive a motor load;
7. verify that the performances and efficiency are comparable with the ones esti-
mate in Chapter 3 and 5.3.
The first four steps are the ones performed in this Thesis. In fact, before to test
the SiC module, all the other electric circuits of the system must work as designed
and it is better to test them separately in order to avoid generation of irreparable
damages in the expensive CCS050M12CM2 device.
The prototype is composed of two different PCBs to be connect one to the other:
one for the power circuits needed to supply the low-voltage ancillary circuits and
one for the inverter including also the gate drivers, current sense amplifier and the
peripheral circuits. All the aspects concerning the creation of this prototype are
described in this Chapter and the environment used to develop the boards is the
open source EDA (Electronic Design Automation) software called KiCad.
83
 6 – Prototype

6.1 Design of the Printed Circuit Board

Since no motor loads are available in FLAG-MS company, considering also that
there is no optimized cooling systems because the thermal design is not faced in this
prototyping step, it is sufficient to implement only one leg of the inverter in order
to test the validity of the electric design. Instead of the expensive CCS050M12CM2
SiC module, the transistors used to test the gate drivers are two Cree C3M0120090J
already available in the company; they are two 900V SiC MOSFET with a max-
imum continuous drain current of 22A and a maximum pulsed current of 50A.
Furthermore, in order to reduce the implementation costs of this prototype, the
DC-link capacitor available in the warehouse and implemented in tested system
is a EPCOS/TDK Z905352661, with an operating voltage of 630V and a ca-
pacitance of 50µF (1/3 of the capacitance selected for the complete three-phase
system).

6.1.1 Electric schematic

The design of Chapter 5 must be changed to be compliant with the new specifics
of the C3M0120090J. This SiC MOSFET needs recommended gate-source voltages
of:

vGS,on = +15V (6.1)

vGS,of f = −4V (6.2)

and the maximum positive voltage allowed is vGS,M AX = +18V. Hence, the flyback
converter must be redesigned in order to supply a maximum output voltage VOU T =
20V and each output rail should be split in a positive voltage of 15V and a negative
one of -5V. The output voltage is dependent on the ratio between RF B and RST
and without varying RST = 12.1kΩ:

(VOU T + VF ) · NP S
RF B = = 210kΩ (6.3)
0.1mA
Also the thermal compensation must be recomputed:

RF B 3mV ◦C−1 210kΩ 3mV ◦C−1

RT C = = = 665kΩ (6.4)
NP S TCdiode 1 1mV ◦C−1

The other components are fully compliant with the specifics, a part from the output
rail that must be redesigned to supply the required positive and negative voltage.
Since this is a prototype, the output rails have been designed with the aim to try
different possible configurations and, how it is visible in Appendix C.1, two diodes
and their two polarization resistors are planned in the electric schematic. By testing
the board the best configuration will be selected between the following ones:
84
 6.1 – Design of the Printed Circuit Board

1. the 15V Zener diode SMBJ5352B with its polarization resistor of 330Ω;
2. the 5V Zener diode SMBJ5338B with its polarization resistor of 1kΩ;
3. both the 15V and the 5V Zener diodes.
The polarization resistors are chosen in order to guarantee the right bias current
to the diodes:
15V 5V
Iz = = = 15mA (6.5)
1kΩ 330Ω
These Zener diodes are used because already available in the warehouse of the com-
pany; their drawback is the high knee-current that leads to higher power dissipation
also through the resistor:

PR1 = 1kΩ · 15mA2 = 225mW (6.6)

PR2 = 330Ω · 15mA = 75mW
2
(6.7)
PDIODE1 = 5V · 15mA = 75mW (6.8)
PDIODE2 = 15V · 15mA = 225mW (6.9)

Thus, the efficiency of this flyback will be lower than the one computed in Chapter
5, but the determination of the efficiency of the inverter is non a relevant aspect of
this prototyping part.
Since two discrete SiC MOSFETs are adopted, they are implemented on the same
board of the gate driving circuits, as reported in Appendix C.3, in order to reduce
the parasitic inductances between the DC-link capacitors and the transistors. In
fact, these components combined with the stray inductance present between the
module and the capacitor create a resonant circuits, and the consequence is a
voltage overshoot when one MOSFET is turned on, while the other MOSFET is
carrying freewheeling current. Furthermore, also the distance between the gate
drivers and the transistors must be minimized because another resonant circuit is
present due to the MOSFET capacitances and the parasitic inductances. The gate
resistors are crucial to reduce the Q-factor of this input resonator and so it design
must be optimized. The recommended gate resistance value for the C3M0120090J
is 2.5Ω but it is better to choose an higher value because the Q-factor is inversely
proportional to it:
ωLs
Q= (6.10)
RG
where LS is the source inductance. Thus, selecting RGH = 8Ω, RGL = 5Ω and
taking into account the split output of the ISO5452-Q1:
vGS,on
Isource = = 1.875A (6.11)
RG
vGS,of f
Isink = = 1A (6.12)
RG
85
 6 – Prototype

that can be easily supplied by the driving circuit. Since these resistors must be
highly reliable and they have to dissipate high power, MELF (Metal Electrode
Leadless Face) resistors are implemented because they are able to provide higher
levels of performance in terms of long term stability, moisture resistance, reliability.
The gate of a MOSFET must be protected from possible overvoltages, so Schot-
tky two diodes are used to clamp them and a resistor of 10Ω is added between
gate and source in the eventuality that the gate driver breaks down. A resistance
of 1MΩ is added also in parallel to the DC-link capacitor, in order to discharge it
with a long time constant if a fault occurs in the inverter circuit.
All the circuit schematics are reported in Appendix C while the Bill of Materials
(BOM) are reported in Table 6.1 and 6.2. Each BOM shows also the part number
of the components and, where it is not present, it means that the device is already
in the warehouse of the company.

86
 6.1 – Design of the Printed Circuit Board

Designator Designation Ref

C1,C2,C4,C6,C7,C17,C18 4.7uF 963-HMJ325KC7475KMHP
C12,C13,C14,C15,C23,C24,C25,C26 0.1uF 80-C0805C104K1REAUTO
C3 10uF 661-EMVA500ADA100ME5
C5,C16 220pF 810-CGA2B2C0G2A221J0
C8,C10,C19,C21 10uF 810-CGA6P1X7R1N106K2
C9,C11,C20,C22 22uF 810-CGA6P3X7R1E226M2
D2 SMBJ5373B-TP
D6,D7,D10,D11 SMBJ18A-TR
D9,D1,D3,D4,D5,D8 B2100-13-F 621-B2100-F
L1 22uH
P1 12V
P2 TOP A
P3 TOP B
P4 TOP C
P5 BOTTOM
R1 261k
R10,R12,R13,R15 330
R2 20k
R3 665k
R4 12.1k
R5,R6 100 603-RC0805FR-13100RL
R8 210k
R9,R11,R7,R14 1k 603-RC0805JR-131KL
T1 750343953
U1 LM5180 595-LM5180QNGUTQ1
Z1,Z2,Z5,Z6 SMBJ5338B
Z3,Z4,Z7,Z8 SMBJ5352B

Table 6.1. BOM of the flyback board.

87
 6 – Prototype

Designator Designation Ref

C1,C2 22uF 810-CGA6P3X7R1E226M2
C10 100pF
C11,C12,C17,C33,C34,C43,C44 10uF 810-CGA6P1X7R1N106K2
C21 3.3uF 80-T494B335K020
C26 50uF
C27,C28 220pF 80-C0805X221J5HAUTO
C29,C8,C15,C19,C23,C24,C30,C39,C40,C37,C38 0.1uF 80-C0805C104K1REAUTO
C3,C31,C32,C45,C46 1uF 963-UMF212B7105KGHT
C35 Cb LS
C36 Cb HS
C4,C5,C14,C16,C18,C20 0.022uF 80-C0805C223K5R
C41 Ca LS
C42 Ca HS
C6,C22,C25 2.2uF 810-C1608X5R1V225KE
C7 0.47uF 80-C0805C474K5RECTU
C9,C13 4.7uF 963-HMJ325KC7475KMHP
D1,D2 STTH112-Y
D3,D4,D5,D6 B2100-13-F 621-B2100-F
D7,D8 BAT54W 621-BAT54W-F
H1 BOTTOM
H2 TOP
H3 PHASE A
IC1 LM46002AQPWPRQ1 595-LM46002AQPWPRQ1
L1 MSS1260-183MLB 994-MSS1260-183MLB
P1 PWR1
P2 PWR2
P3 12V
P4 CON 1X10
Q1,Q2 C3M0120090J
R1 82.5k 660-RK73H2ATTD8252F
R11,R13 8 594-MMB02070C8208FB2
R12,R14 5 594-MMB02070C5108FB2
R15,R16 1k 603-RC0805JR-131KL
R17,R18 10 660-RK73H2ATTD10R0F
R2 1M 660-RK73H2ATTD1004F
R3,R9,R10,R19,R20,R21,R22 10k 660-RK73H2ATTD1002F
R4 255k 660-RK73H2ATTD2553F
R5 BVS-M-R0007 660-PSJ2NTEBL500F
R6,R7 49.9 71-CRCW080549R9FKEAC
R8 1M 279-CRGCQ2512F1M0
U1 TPS7B6950-Q1 595-TPS7B6950QDBVRQ1
U2 AMC1302-Q1 595-AMC1302QDWVRQ1
U3,U4 ISO5452-Q1 595-ISO5452QDWRQ1
Z1,Z2 SMBJ5341B

Table 6.2. BOM of the gate driver board.

6.1.2 Layout of the PCB

In order to allow a fast manufacturing and low costs, the layout is designed on a
two-layer PCB with sizes lower than 10cm x 10cm. Furthermore, to ensure the
compliance with the IEC-60664, the minimum creepage distances of 4mm must be
respected (Figure 6.1).
88
 6.1 – Design of the Printed Circuit Board

Figure 6.1. Creepage distances to avoid failure due to tracking. [25]

Flyback board
In this section, the layout and the final PCB of the flyback board are reported.
It measure 8.5cm x 7.5cm. The output connector with the label BOTTOM must
supply the required voltages to the low-side gate driver; it is sufficient only one
isolated output because the low-side transistors are all referred to the same potential
and the transformers is designed to distribute in this rail three-times of the power
of the other ones. The drawback of this transformer is that the creepage distances
of 4mm are not respected between the secondary windings, this is the reason why
three holes are provided in the PCB.

89
 6 – Prototype

Figure 6.2. Layout of the top side of the flyback board.

Figure 6.3. Top side of the flyback PCB.

90
 6.1 – Design of the Printed Circuit Board

Figure 6.4. Layout of the bottom side of the flyback board.

Figure 6.5. Bottom side of the flyback PCB.

91
 6 – Prototype

Gate driving board

In this section, the layout and the final PCB of the gate driving board are reported.
It measure 10cm x 7.5cm.

Figure 6.6. Layout of the top side of the gate driving board.

Figure 6.7. Top side of the gate driving PCB.

92
 6.1 – Design of the Printed Circuit Board

Figure 6.8. Layout of the bottom side of the gate driving board.

Figure 6.9. Bottom side of the gate driving PCB.

93
 6 – Prototype

6.2 Experimental results

The instruments and tools of the FLAG-MS company used for the test are listed
here:

EA-PSB 9750-60 3U Slave 15000W

Manufacter: Elektro-Automatil
Product Type: Bi-directional Power-Supply
Voltage Range: 0 ÷ 750V
Current Range: 0 ÷ 60A
Power Rating: 15 000W

Hercules TMS570LS12x Development Kit

Manufacter: Texas Instruments
Product Type: Embedded development hardware board
Main board elements: T M S570LS1224, XDS110 Class Debug Probe

Fluke 62 MAX+
Manufacter: Fluke
Product Type: Infrared thermometer
Temperature Range: −30◦C ÷ 500◦C
Spectral Response: 8 µm ÷ 14 µm
Optical Resolution: 12 : 1

AC/DC Adapter
Input Voltage Range: 100 ÷ 240V
Input Current: 1.6A
Input Frequency: 50 − 60Hz
Output Voltage: 12V
Output Current: 5A

Fluke 1507
Manufacter: Fluke
Product Type: Isolation Resistance Tester
Measurement range: 0.01MΩ ÷ 10GΩ
Test Voltage: 50V, 100V, 250V, 500V, 1000V
94
 6.2 – Experimental results

E3N
Manufacter: Chauvin Arnoux
Product Type: Hall-effect clamp
Rated current: 100A DC or peak
Output signal: DC and AC voltage
Output/input ratio: 100 mA
mV
, 10 mV
A

SI-9002
Manufacter: TiePie
Product Type: Differential probe
Bandwidth: DC to 25MHz (3dB)
Attenuation ratio: 1/20 or 1/200

DP832
Manufacter: Rigol
Product Type: Programmable DC Power Sypply
Output: 30V/3A 30V/3A, 5V/3A
Total Power: up to 195W

Wavesurfer 3024
Manufacter:Teledyne LeCroy
Product Type: Oscilloscope
Bandwidth (at 50Hz): 50Hz
Input Impedance: 50Ω ± 2%, 1MΩ ± 2%; 16pF
Sample Rate (Single Shot): 2GS/s

Flyback board
The first board under test is the flyback one. The configuration chosen for the
output rail is the one designed in Chapter 5.2: only one Zener diode for stabilizing
the 15V, biased from its resistor of 330Ω. In order to verify the behaviour of
flyback converter, it is connected to the DP832 and the outputs are loaded with two
resistors: a 330Ω resistor is connected between VCC and REF and a 330Ω between
VEE and REF, in such a way to obtain the total output power of 20V 2 /660 =
610mW, near to the maximum designed one of 625mW (Chapter 5). When the
Rigol power supply is turned on, a delivered power of around 1.9W can be noticed:
the reason is due to the high power dissipation of the output rails. Taking into
account equations (6.9), the output rails sink 1.2W of the delivered power dropping
the efficiency. Anyway, connecting the output pins to the oscilloscope and setting
95
 6 – Prototype

the input voltage equal to the nominal one of 12V, Figure 6.10 shows that the
output voltage between VCC and VEE is around 20.15V with a ripple of 356mV.

Figure 6.10. Output voltage of the flyback converter with a zoom of its ripple.

Then, the input voltage is sweep from the minimum one of 9V to the maximum
one of 24V, and in Figure 6.11 and 6.12 it is visible the good stability and line
regulation of the converter.

Figure 6.11. Output voltage of the flyback converter with an input voltage of 9V.

96
 6.2 – Experimental results

Figure 6.12. Output voltage of the flyback converter with an input voltage of 24V.

The converter is able to supply both 15V and -5V also when the load is changed
with two resistors of 4.7kΩ and the power absorbed from the amplifier is reduced
because this load sink less current and so less power must be delivered.

Figure 6.13. The 15V and -5V voltages supplied by the flyback.

As illustrated in Chapter 5, the LM5180-Q1 can operates in BCM, FFM or DCM

and it is expected that:

• At full load with low input voltages it should works in BCM.

• At full load with high input voltages it should works in DCM.

97
 6 – Prototype

Thus, connecting a probe to the pin SW of the device, the converter is supplied
with the nominal voltage of 12V, the minimum voltage of 9V and the maximum
one of 24V and it can be seen that with 9V and 12V it works in BCM while with
24V it works in DCM; Figure 6.15, 6.14 and 6.16 confirm the theory assumptions
and validate the design.

Figure 6.14. Pin SW with respect ground when the nominal voltage is applied.

Figure 6.15. Pin SW with respect ground when the minimum voltage is applied.

98
 6.2 – Experimental results

Figure 6.16. Pin SW with respect ground when the maximum voltage is applied.

Gate driving board

The first test to perform on this PCB is to verify the absence of short-circuits, thus
VCC, REF and VEE pins of both the high and low-side drivers are connected to
the Rigol DP832 while the DC-bus is not connected to any supply or battery. The
logic of the ISO5452-Q1 is connected to the Hercules TMS570LS12x Development
Kit, where InSight, a software developed by the members of the FLAG-MS, runs.
Thanks to its GUI (Graphical User Interface), reported in Figure, it is possible to
set and manage all the parameters needed to perform the tests (Figure 6.17):

• Frequency, death-time and duty-cycle of the PWM.

• Period and number of pulses to generate.
• Management of the RESET and FAULT pins of the gate driver.

99
 6 – Prototype

Figure 6.17. Example of an InSight GUI.

By controlling the gate drivers with pulses with different duty-cycles and differ-
ent death-times, the supply voltages are correctly delivered to the gate pin of both
high and low-side transistors (Figure 6.18).

Figure 6.18. Example of the gate drivers controlled by PWM.

100
 6.2 – Experimental results

Thus, connecting the DC-bus to the Rigol DP832 and supplying the board with
32V and 3.3A, the gate driving board shows the expected behaviour (Figure 6.19).

Figure 6.19. Gate of the low-side transistor (red wave) and phase
voltage (yellow wave).

Test of the prototype

Since the test performed until now shows that the gate drivers, the buck converter
and the flyback power supply behaves in the designed way, the complete prototype
can be tested. Before to connect it to the EA-PSB 9750-60, an insulation test must
be performed in order to ensure the right safety level during the measurements.
The insulation is evaluated using the Fluke 1507, and a resistance of 11GΩ is
measured between all the low-voltage pins and all high-voltage ones, meaning that
the insulation level for the application is respected.

Figure 6.20. Experimental test setup.

101
 6 – Prototype

The test concerns to drive the gate drivers with waveforms composed of one or
two or three pulses, whose duration and distance among each other is setted by the
InSight interface. The first transistor under test is the low-side one and the load
consists of a hand-made inductor of about 30µH. The results are reported below.

Figure 6.21. Prototype connected to a DC-bus of 100V and driven with two
pulses of 20µs distanced by 50µs. The waveform reported are: gate of the low-side
transistor (yellow), phase voltage (blue), output current (red).

Figure 6.22. Prototype connected to a DC-bus of 200V and driven with two
pulses of 10µs distanced by 50µs. The waveform reported are: gate of the low-side
transistor (yellow), phase voltage (blue), output current (red).

102
 6.2 – Experimental results

Figure 6.23. Prototype connected to a DC-bus of 200V and driven with two pulses
of 10µs distanced by 50µs. Zoom of the start-up with zero output current.

Figure 6.24. Prototype connected to a DC-bus of 200V and driven with

two pulses of 10µs distanced by 50µs. Zoom of the start-up with output
current different from zero.

103
 6 – Prototype

Figure 6.25. Prototype connected to a DC-bus of 550V and driven with one pulse
of 0.5µs. The waveform reported are: gate of the low-side transistor (yellow), phase
voltage (blue), output current (red).

Figure 6.26. Prototype connected to a DC-bus of 550V and driven with one
pulse of 0with two pulses of 0.5µs distanced by 6µs. Zoom of the start-up with
output current different from zero.

104
 6.2 – Experimental results

Once that the low-side transistor has been tested, also the behaviour of the high-
side one can be evaluated. In this case, instead of monitoring the phase voltage,
the differential probe SI-9002 is connected between gate and source of the low-side
transistor in order to verify that it is not turned on by the Miller current. The
results are reported below.

Figure 6.27. Prototype connected to a DC-bus of 350V and driven with two
pulses of 0.5µs distanced by 6µs. The waveform reported are: gate of the low-side
transistor (yellow), gate of the high-side transistor (blue), output current (red).

Figure 6.28. Prototype connected to a DC-bus of 350V and driven with two pulses
of 0.5µs distanced by 6µs. Zoom of the waveforms.

105
 6 – Prototype

Figure 6.29. Prototype connected to a DC-bus of 400V and driven with two
pulses of 0.5µs distanced by 6µs. The waveform reported are: gate of the low-side
transistor (yellow), gate of the high-side transistor (blue), output current (red).

Figure 6.30. Prototype connected to a DC-bus of 500V and driven with two
pulses of 0.5µs distanced by 6µs. The waveform reported are: gate of the low-side
transistor (yellow), gate of the high-side transistor (blue), output current (red).

The tests show that the Miller clamp feature is able to avoid unwanted turn-on
of the transistors due to Miller current. Another important protection feature is
the DESAT, fully described and designed in Chapter 5; it must be verified because
106
 6.2 – Experimental results

it allows to protect the transistor when the current through it becomes higher than
the maximum one. The drain-source voltage at which the input voltage of the
DESAT pin reaches 9V is around 1.3V , as designed in (5.5), and it corresponds
of a maximum allowed current of around 17A for the transistors of the prototype.
The figures reported below shows the behaviour of the desaturation feature.

Figure 6.31. Prototype connected to a DC-bus of 200V. The wave-

form reported are: gate of the low-side transistor (yellow), DESAT pin
(green), output current (red).

Figure 6.32. Prototype connected to a DC-bus of 550V. The wave-

form reported are: gate of the low-side transistor (yellow), DESAT pin
(blue), output current (red).

107
 6 – Prototype

One component implemented on this prototype has not been used during the
test: the current sense amplifier. Its work will be necessary when the inverter will
be test in a closed loop and with a motor load in order to monitoring the main
parameters of the motor, such as its torque and angular speed. So, it must be
tested and the differential output is reported in the next figure where it is visible
that the voltage across the shunt perfectly follows the output current.

Figure 6.33. Prototype connected to a DC-bus of 250V. The output current is

reported in red, while the vltage across the shunt is reported in yellow.

108
Chapter 7

Conclusions and future

works
This work presented the design of the prototype of a three-phase two-level voltage
source inverter with the required power level needed from the heavy-duty sector,
along with a systematic design flow. In this context, due to the lack of information
at this very beginning stage of the task about the topology of the electric motor
that will be implemented in the final application, the Thesis described the design
of a general-purpose AC electric drive.
The analysis begun with trends in the transportation sector, focusing on the
heavy-duty vehicles and the need of electric powertrain in this sector.
The working principle of the three-phase VSI has been presented and some of
the most used modulation techniques have been discussed.
The waveforms of the inverter voltages and currents have been derived thanks to
the model developed in a MATLAB/SIMULINK environment in order to estimate
their effects on the design. Furthermore, the model has been used to evaluate
the conduction and switching power losses of the switching transistors and, after
a comparison with the simulation results of SemiSel, the best switch topology has
been chosen; it consists in a SiC module, a choiche that allows to combine high
efficient and high power density.
Thanks to the waveforms derived from the MATLAB/SIMULINK model, and
in-depth view of the DC-link current has been made and the right DC-link capacitor
for minimizing the ripple of the DC-link voltage has been selected. In particular, it
is a metallized polypropylene film capacitor because it can sink high rms DC-link
currents with low self-heating.
The selection of the power switches and the DC-link capacitors was the pillar
for the successive steps, mainly related to the design of the ancillary circuits of the
inverter: the gate drivers for the power switches and their power supply, the cur-
rent sense amplifier and the peripheral circuits needed to supply all the integrated

109
 7 – Conclusions and future works

circuits of the system. Also a first estimation of the system has been computed,
but it considered only the power drop over the switches and the ancillary circuits.
A more precise estimation can be done when the type of motor that the inverter
has to drive will be defined.
At the end of this design procedure, a prototype has been developed for vali-
dation purposes; it is composed of two different PCBs connected one to the other:
one for the power circuits needed to supply the low-voltage ancillary circuits and
one for the inverter including also the gate drivers, current sense amplifier and the
peripheral circuits. The low-power supply and the inverter boards have been tested
to verify the absence of short-circuits, the correctness of the electrical connections
between parts and that all the voltage levels are correctly delivered as required to
the different circuits. Tests also include verification of the galvanic insulation. Ex-
perimental tests have been carried out to verify that the required output voltages
and output currents are supplied and that they are capable to work properly under
all the possible different configurations.
The tests have been performed by loading the inverter with different inductive
loads and, by driving it with different pulses. The system has been tested until a
DC input voltage of 550V because the DC-link capacitor is rated for an operating
voltage of 630V. The experimental tests have shown the correct switching behaviour
of the transistors, the correct behaviour of all the protection features of the chip, the
reliability of current sensing, the absence of false turn-on of the MOSFET during
the high voltage transient.
From the tests on this prototype it can be inferred that all the selected and
designed components are suitable to be implemented in a further final release of
the inverter. The members of the FLAG-MS company can use this design as starting
point for its long-term project and they will implement an improved version of the
prototype. The critical aspects highlighted from the tests are the worsted efficiency
with respect the designed one of the flyback and the ringing of the output current
with high input voltage. The efficiency of the flyback can be increased by simply
changing the Zener diodes of the output rails, while the ringing of the currents are
related only to the low inductance of the load; in fact, the gate voltages are stable
also in the presence of high current ringing.
An important aspect not analysed in this Thesis is the one concerning the electro-
magnetic compatibility (EMC) because the company has not the right environment
to perform this type of test and the booking of anechoic chamber was unfeasible
within the developing time of the Thesis. Furthermore, a thermal analysis of the
system should be faced in the near future to ensure that the system can be used
outside and under the stressing conditions of a heavy-duty application.

110
Appendix A

MATLAB codes

A.1 Scripts for inverter model simulation

A.1.1 Sinusoidal PWM
inverter_parameter
clear all ;
clc ;

%% DC l i n k
P = 20 e 3 ; % a c t i v e power
Vdc = 7 0 0 ; % DC−l i n k v o l t a g e
I d c = P/Vdc ; % DC c u r r e n t
Ipk_max = 2∗ I d c ; % max p h a s e c u r r e n t

%% l o a d
Vrms = 3 2 0 ; % n o m i n a l phase−to−p h a s e rms v o l t a g e
cos_phi = 0 . 8 ; % power f a c t o r
phi = acos ( cos_phi ) ;
Q = P∗ s i n ( p h i ) / c o s ( p h i ) ; % inductive r e a c t i v e power

%% PWM
f s w = 15 e 3 ; % switching frequency
Fs = 1 e 3 ; % control signal frequency
Ts = 1/ Fs ;
shift = 0; % p h a s e s h i f t i n g c o n t r o l wave
Vt = 1 ; % t r i a n g u l a r amplitude
Vph = Vrms/ s q r t ( 3 ) ; % rms p h a s e v o l t a g e
ma_SPWM = 2∗ s q r t ( 2 ) ∗Vph/Vdc ; % m o d u l a t i o n i n d e x S PWM
V r e f = ma_SPWM∗Vt ; % reference control voltage
d l y = 1 e −7; % death time

%% s i m u l a t i o n p a r a m e t e r s
Tsamp = 2 e −6; % sampling time ( Nyquist h o l d s )
Tsim = 20/ Fs ; % s i m u l a t i o n time

%% power
I l _ r m s = P/ ( s q r t ( 3 ) ∗Vrms∗ c o s _ p h i ) ; % line c u r r e n t rms
I = Il_rms ∗ s q r t ( 2 ) ; % line c u r r e n t peak

A.1.2 Space-Vector PWM

inverter_parameter
clear all ;
clc ;

%% DC l i n k
P = 20 e 3 ; % a c t i v e power

111
 A – MATLAB codes

Vdc = 7 0 0 ; % DC−l i n k v o l t a g e
I d c = P/Vdc ; % DC c u r r e n t
Ipk_max = 2∗ I d c ; % max p h a s e c u r r e n t

%% l o a d
Vrms = 3 2 0 ; % n o m i n a l phase−to−p h a s e rms v o l t a g e
cos_phi = 0 . 8 ; % power f a c t o r
phi = acos ( cos_phi ) ;
Q = P∗ s i n ( p h i ) / c o s ( p h i ) ; % inductive r e a c t i v e power

%% PWM
f s w = 15 e 3 ; % switching frequency
Fs = 1 e 3 ; % control signal frequency
Ts = 1/ Fs ;
shift = 0; % p h a s e s h i f t i n g c o n t r o l wave
Vt = 1 ; % t r i a n g u l a r amplitude
Vph = Vrms/ s q r t ( 3 ) ; % rms p h a s e v o l t a g e
ma = s q r t ( 2 ) ∗Vrms/Vdc ; % m o d u l a t i o n i n d e x SV PWM
d l y = 1 e −7; % death time

%% s i m u l a t i o n p a r a m e t e r s
Tsamp = 2 e −6; % sampling time ( Nyquist holds )
Tsim = 20/ Fs ; % s i m u l a t i o n time

%% power
I l _ r m s = P/ ( s q r t ( 3 ) ∗Vrms∗ c o s _ p h i ) ; % l i n e c u r r e n t rms
I = Il_rms ∗ s q r t ( 2 ) ; % line c u r r e n t peak

A.2 Script for losses evaluation

A.2.1 IGBT losses
%% CM100TX(P) −24T
% V_ce0 = 1 . 1 ;
% r_ce = 0 . 0 0 9 5 ;
% V_d0 = 1 . 3 ;
% r_d = 0 . 0 0 6 2 5 ;
% t o f f = 400 e −9;
% t o n = 70 e −9;
% t r r = 18 e −9;
% l o a d ( ’ CM100TXP_24T_Eoff . mat ’ ) ; %l o a d E o f f g r a p h
% l o a d ( ’ CM100TXP_24T_Eon . mat ’ ) ; %l o a d Eon g r a p h
% l o a d ( ’ CM100TXP_24T_Err . mat ’ ) ; %l o a d E r r g r a p h
% Eoff_IGBT = m a t f i l e ( ’ CM100TXP_24T_Eoff . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Eon_IGBT = m a t f i l e ( ’ CM100TXP_24T_Eon . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Err_IGBT = m a t f i l e ( ’ CM100TXP_24T_Err . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% x _ o f f = Eoff_IGBT . CM100TXP_24T_Eoff ( : , 1 ) ; %x−a x i s v a l u e E o f f
% y _ o f f = Eoff_IGBT . CM100TXP_24T_Eoff ( : , 2 ) ; %y−a x i s v a l u e E o f f
% x_on = Eon_IGBT . CM100TXP_24T_Eon ( : , 1 ) ; %x−a x i s v a l u e Eon
% y_on = Eon_IGBT . CM100TXP_24T_Eon ( : , 2 ) ; %y−a x i s Value Eon
% x_rr = Err_IGBT . CM100TXP_24T_Err ( : , 1 ) ; %x−a x i s v a l u e E r r
% y_rr = Err_IGBT . CM100TXP_24T_Err ( : , 2 ) ; %y−a x i s v a l u e E r r

%% SEMiX101GD12E4s
% V_ce0 = 0 . 8 ;
% r_ce = 0 . 0 1 6 ;
% V_d0 = 1 . 1 ;
% r_d = 0 . 0 1 3 7 ;
% t o f f = 500 e −9;
% t o n = 110 e −9;
% t r r = 25 e −9;
% l o a d ( ’ SEMiX101GD12E4s_Eoff . mat ’ ) ; %l o a d E o f f g r a p h
% l o a d ( ’ SEMiX101GD12E4s_Eon . mat ’ ) ; %l o a d Eon g r a p h
% l o a d ( ’ SEMiX101GD12E4s_Err . mat ’ ) ; %l o a d E r r g r a p h
% Eoff_IGBT = m a t f i l e ( ’ SEMiX101GD12E4s_Eoff . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Eon_IGBT = m a t f i l e ( ’ SEMiX101GD12E4s_Eon . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Err_IGBT = m a t f i l e ( ’ SEMiX101GD12E4s_Err . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% x _ o f f = Eoff_IGBT . SEMiX101GD12E4s_Eoff ( : , 1 ) ; %x−a x i s v a l u e E o f f
% y _ o f f = Eoff_IGBT . SEMiX101GD12E4s_Eoff ( : , 2 ) ; %y−a x i s v a l u e E o f f
% x_on = Eon_IGBT . SEMiX101GD12E4s_Eon ( : , 1 ) ; %x−a x i s v a l u e Eon
% y_on = Eon_IGBT . SEMiX101GD12E4s_Eon ( : , 2 ) ; %y−a x i s Value Eon
% x_rr = Err_IGBT . SEMiX101GD12E4s_Err ( : , 1 ) ; %x−a x i s v a l u e E r r
% y_rr = Err_IGBT . SEMiX101GD12E4s_Err ( : , 2 ) ; %y−a x i s v a l u e E r r

%% SK100GD12T4T
V_ce0 = 1 . 3 ;
r_ce = 0 . 0 1 2 5 ;
V_d0 = 1 . 5 ;
r_d = 0 . 0 1 4 ;

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 A.2 – Script for losses evaluation

t o f f = 600 e −9;
t o n = 55 e −9;
t r r = 40 e −9;
l o a d ( ’ SK100GD12T4T_Eoff . mat ’ ) ; %l o a d E o f f g r a p h
l o a d ( ’ SK100GD12T4T_Eon . mat ’ ) ; %l o a d Eon g r a p h
l o a d ( ’ SK100GD12T4T_Err . mat ’ ) ; %l o a d E r r g r a p h
Eoff_IGBT = m a t f i l e ( ’ SK100GD12T4T_Eoff . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
Eon_IGBT = m a t f i l e ( ’ SK100GD12T4T_Eon . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
Err_IGBT = m a t f i l e ( ’ SK100GD12T4T_Err . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
x _ o f f = Eoff_IGBT . SK100GD12T4T_Eoff ( : , 1 ) ; %x−a x i s v a l u e E o f f
y _ o f f = Eoff_IGBT . SK100GD12T4T_Eoff ( : , 2 ) ; %y−a x i s v a l u e E o f f
x_on = Eon_IGBT . SK100GD12T4T_Eon ( : , 1 ) ; %x−a x i s v a l u e Eon
y_on = Eon_IGBT . SK100GD12T4T_Eon ( : , 2 ) ; %y−a x i s Value Eon
x_rr = Err_IGBT . SK100GD12T4T_Err ( : , 1 ) ; %x−a x i s v a l u e E r r
y_rr = Err_IGBT . SK100GD12T4T_Err ( : , 2 ) ; %y−a x i s v a l u e E r r

%% SEMiX101GD12Vs
% V_ce0 = 1 . 0 4 ;
% r_ce = 0 . 0 1 5 2 ;
% V_d0 = 1 . 5 ;
% r_d = 0 . 0 1 3 7 ;
% t o f f = 550 e −9;
% t o n = 320 e −9;
% t r r = 35 e −9;
% l o a d ( ’ SEMiX101GD12Vs_Eoff . mat ’ ) ; %l o a d E o f f g r a p h
% l o a d ( ’ SEMiX101GD12Vs_Eon . mat ’ ) ; %l o a d Eon g r a p h
% l o a d ( ’ SEMiX101GD12Vs_Err . mat ’ ) ; %l o a d E r r g r a p h
% Eoff_IGBT = m a t f i l e ( ’ SEMiX101GD12Vs_Eoff . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Eon_IGBT = m a t f i l e ( ’ SEMiX101GD12Vs_Eon . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Err_IGBT = m a t f i l e ( ’ SEMiX101GD12Vs_Err . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% x _ o f f = Eoff_IGBT . SEMiX101GD12Vs_Eoff ( : , 1 ) ; %x−a x i s v a l u e E o f f
% y _ o f f = Eoff_IGBT . SEMiX101GD12Vs_Eoff ( : , 2 ) ; %y−a x i s v a l u e E o f f
% x_on = Eon_IGBT . SEMiX101GD12Vs_Eon ( : , 1 ) ; %x−a x i s v a l u e Eon
% y_on = Eon_IGBT . SEMiX101GD12Vs_Eon ( : , 2 ) ; %y−a x i s Value Eon
% x_rr = Err_IGBT . SEMiX101GD12Vs_Err ( : , 1 ) ; %x−a x i s v a l u e E r r
% y_rr = Err_IGBT . SEMiX101GD12Vs_Err ( : , 2 ) ; %y−a x i s v a l u e E r r

%% FS75R12KT4_B15
% V_ce0 = 0 . 9 6 ;
% r_ce = 0 . 0 1 7 ;
% V_d0 = 1 . 2 5 ;
% r_d = 0 . 0 1 1 ;
% t o n = 0 . 1 5 e −6;
% t o f f = 0 . 4 0 e −6;
% t r r = 0 . 0 9 e −6;
% l o a d ( ’ FS75R12KT4_B15_Eoff . mat ’ ) ; %l o a d E o f f g r a p h
% l o a d ( ’ FS75R12KT4_B15_Eon . mat ’ ) ; %l o a d Eon g r a p h
% l o a d ( ’ FS75R12KT4_B15_Err . mat ’ ) ; %l o a d E r r g r a p h
% Eoff_IGBT = m a t f i l e ( ’ FS75R12KT4_B15_Eoff . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Eon_IGBT = m a t f i l e ( ’ FS75R12KT4_B15_Eon . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Err_IGBT = m a t f i l e ( ’ FS75R12KT4_B15_Err . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% x _ o f f = Eoff_IGBT . FS75R12KT4_B15_Eoff ( : , 1 ) ; %x−a x i s v a l u e E o f f
% y _ o f f = Eoff_IGBT . FS75R12KT4_B15_Eoff ( : , 2 ) ; %y−a x i s v a l u e E o f f
% x_on = Eon_IGBT . FS75R12KT4_B15_Eon ( : , 1 ) ; %x−a x i s v a l u e Eon
% y_on = Eon_IGBT . FS75R12KT4_B15_Eon ( : , 2 ) ; %y−a x i s Value Eon
% x_rr = Err_IGBT . FS75R12KT4_B15_Err ( : , 1 ) ; %x−a x i s v a l u e E r r
% y_rr = Err_IGBT . FS75R12KT4_B15_Err ( : , 2 ) ; %y−a x i s v a l u e E r r

%% IRGPS60B120KDP
% V_ce0 = 1 . 5 ;
% r_ce = 0 . 0 2 2 ;
% V_d0 = 1 . 2 5 ;
% r_d = 0 . 0 1 5 ;
% t o n = 60 e −9;
% t o f f = 130 e −9;
% t r r = 32 e −9;
% l o a d ( ’ IRGPS60B120KDP_Eoff . mat ’ ) ; %l o a d E o f f g r a p h
% l o a d ( ’ IRGPS60B120KDP_Eon . mat ’ ) ; %l o a d Eon g r a p h
% l o a d ( ’ IRGPS60B120KDP_Err . mat ’ ) ; %l o a d E r r g r a p h
% Eoff_IGBT = m a t f i l e ( ’ IRGPS60B120KDP_Eoff . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Eon_IGBT = m a t f i l e ( ’ IRGPS60B120KDP_Eon . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Err_IGBT = m a t f i l e ( ’ IRGPS60B120KDP_Err . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% x _ o f f = Eoff_IGBT . IRGPS60B120KDP_Eoff ( : , 1 ) ; %x−a x i s v a l u e E o f f
% y _ o f f = Eoff_IGBT . IRGPS60B120KDP_Eoff ( : , 2 ) ; %y−a x i s v a l u e E o f f
% x_on = Eon_IGBT . IRGPS60B120KDP_Eon ( : , 1 ) ; %x−a x i s v a l u e Eon
% y_on = Eon_IGBT . IRGPS60B120KDP_Eon ( : , 2 ) ; %y−a x i s Value Eon
% x_rr = Err_IGBT . IRGPS60B120KDP_Err ( : , 1 ) ; %x−a x i s v a l u e E r r
% y_rr = Err_IGBT . IRGPS60B120KDP_Err ( : , 2 ) ; %y−a x i s v a l u e E r r

%% t r i g g e r
c u r r e n t _ i n d e x = f i n d ( o u t . IGBT_current . Data ) ; % i n d e x w i t h non z e r o c u r r e n t
i_IGBT = o u t . IGBT_current . Data ( c u r r e n t _ i n d e x ) ; % non z e r o c u r r e n t v a l u e s
t_IGBT = o u t . IGBT_current . Time ( c u r r e n t _ i n d e x ) ; % t i m e o f non z e r o c u r r e n t v a l u e s

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 A – MATLAB codes

t i m e _ i n d e x = f i n d ( ( t_IGBT >= 4 . 5 ∗ Ts ) & ( t_IGBT <= ( Tsim − 2∗ Ts ) ) ) ; % t i m e v a l u e s a t r e g i m e

current_IGBT = i_IGBT ( t i m e _ i n d e x ) ; % non z e r o c u r r e n t v a l u e s a t r e g i m e
p o s i t i v e _ i n d e x = f i n d ( current_IGBT > 0 ) ; % index with p o s i t i v e c u r r e n t at regime
p o s i t i v e _ c u r r e n t = current_IGBT ( p o s i t i v e _ i n d e x ) ; % p o s i t i v e current values at regime
t r i g g e r = f i n d ( o u t . IGBT_current . Data == min ( p o s i t i v e _ c u r r e n t ) ) ; % i n d e x w i t h s m a l l e s t v a l u e o f
positive current
s t a r t _ p o i n t = o u t . IGBT_current . Time ( t r i g g e r ) ; % s t a r t p o i n t = t i m e v a l u e w i t h s m a l l e s t c u r r e n t
e n d _ p o i n t = s t a r t _ p o i n t ( 1 ) + Ts ; % end p o i n t a f t e r one c o n t r o l s i g n a l p e r i o d
T_IGBT = g e t s a m p l e u s i n g t i m e ( o u t . IGBT_current , s t a r t _ p o i n t ( 1 ) , e n d _ p o i n t ) ; % one p e r i o d o f c u r r e n t
at regime
xIGBT = 0 : ( Ts / ( l e n g t h (T_IGBT . Data ) −1) ) : Ts ; % x−a x i s v a l u e s f o r p l o t
%p l o t ( xIGBT , T_IGBT . Data ) ;

%% e d g e d e t e c t i o n
index_nz_IGBT = f i n d (T_IGBT . Data ) ; % i n d e x o f non z e r o c u r r e n t o v e r t h e s e l e c t e d p e r i o d
index_z_IGBT = f i n d ( ~T_IGBT . Data ) ; % index of zero current over the s e l e c t e d period
r i s i n g _ e d g e s = f i n d ( ismember ( ( index_nz_IGBT ) , ( index_z_IGBT+1) ) ) ; % s e a r c h i n g f o r on e d g e s
p o s i t i v e _ p e a k = index_nz_IGBT ( r i s i n g _ e d g e s ) ; % on e d g e s i n d e x
on_peak = T_IGBT . Data ( u n i o n ( p o s i t i v e _ p e a k , index_z_IGBT ) ) ; % r i s i n g edges current values
x_on_peak = xIGBT ( u n i o n ( p o s i t i v e _ p e a k , index_z_IGBT ) ) ; % r i s i n g edge time v a l u e s
%p l o t ( x_on_peak , on_peak , ’ b . ’ , xIGBT , T_IGBT . Data ) ;
f a l l i n g _ e d g e s = f i n d ( ismember ( ( index_nz_IGBT ) , ( index_z_IGBT −1) ) ) ; % s e a r c h i n g f o r o f f e d g e s
n e g a t i v e _ p e a k = index_nz_IGBT ( f a l l i n g _ e d g e s ) ; % o f f edges index
o f f _ p e a k = T_IGBT . Data ( u n i o n ( n e g a t i v e _ p e a k , index_z_IGBT ) ) ; % f a l l i n g edges current
values
x_off_peak = xIGBT ( u n i o n ( n e g a t i v e _ p e a k , index_z_IGBT ) ) ; % f a l l i n g edges time v a l u e s
%p l o t ( x_off_peak , o f f _ p e a k , ’ b . ’ , xIGBT , T_IGBT . Data ) ;
%p l o t ( xIGBT , T_IGBT . Data , ’ g ’ , x_off_peak ( o f f _ p e a k ~=0) , o f f _ p e a k ( o f f _ p e a k ~=0) , ’ b ∗ ’ , x_on_peak (
on_peak ~=0) , on_peak ( on_peak ~=0) , ’ r . ’ ) ;
t o n _ i n d e x = f i n d ( on_peak >= 0 ) ; % index o f a l l t r a n s i s t o r ton
t o f f _ i n d e x = f i n d ( o f f _ p e a k >= 0 ) ; % index of a l l t r a n s i s t o r t o f f
t r r _ i n d e x = f i n d ( on_peak <= 0 ) ; % i n d e x o f a l l d i o d e t o n ( d i o d e t o f f can be n e g l e c t e d )
i_on = round ( on_peak ( t o n _ i n d e x ) , 4 ) . ’ ; % t r a n s i s t o r c u r r e n t on t o n
x_i_on = x_on_peak ( t o n _ i n d e x ) ; % t i m e v a l u e s o f i_on
i _ o f f = round ( o f f _ p e a k ( t o f f _ i n d e x ) , 4 ) . ’ ; % t r a n s i s t o r c u r r e n t on t o f f
x _ i _ o f f = x_off_peak ( t o f f _ i n d e x ) ; % time v a l u e s o f i _ o f f
i _ r r = round ( on_peak ( t r r _ i n d e x ) , 4 ) . ’ ; % d i o d e c u r r e n t on t o n
x_i_rr = x_on_peak ( t r r _ i n d e x ) ; % time v a l u e s o f i _r r

%% c o n d u c t i o n l o s s e s
p c t _ i n d e x = f i n d (T_IGBT . Data >= 0 ) ; % t r a n s i s t o r i n d e x , t r a n s i s t o r i s on d u r i n g t h e p o s i t i v e
part
p_ct = a b s (T_IGBT . Data ( p c t _ i n d e x ) ) . ∗ V_ce0 + (T_IGBT . Data ( p c t _ i n d e x ) . ^ 2 ) . ∗ r_ce ;
pcd_index = f i n d (T_IGBT . Data <= 0 ) ; % d i o d e i n d e x , d i o d e i s on d u r i n g t h e n e g a t i v e p a r t
p_cd = a b s (T_IGBT . Data ( pcd_index ) ) . ∗ V_d0 + (T_IGBT . Data ( pcd_index ) . ^ 2 ) . ∗ r_d ;
x_ct = xIGBT ( p c t _ i n d e x ) ;
x_cd = xIGBT ( pcd_index ) ;
Pcd = t r a p z ( x_cd , p_cd ) /Ts ;
Pct = t r a p z ( x_ct , p_ct ) /Ts ;
%p l o t ( x_cd , p_cd , x_ct , p_ct ) ;

%% s w i t c h i n g l o s s e s
xq = round ( ( 0 : 0 . 0 0 0 1 : 2 0 0 ) , 4 ) ; % g e n e r a t e a l l t h e c u r r e n t v a l u e s o f E o f f , Eon , E r r
E o f f _ d a t a = i n t e r p 1 ( x _ o f f , y _ o f f , xq , ’ p c h i p ’ ) ; % i n t e r p o l a t e datasheet curve
Eon_data = i n t e r p 1 ( x_on , y_on , xq , ’ p c h i p ’ ) ; % i n t e r p o l a t e datasheet curve
Err_data = i n t e r p 1 ( x_rr , y_rr , xq , ’ p c h i p ’ ) ; % i n t e r p o l a t e datasheet curve
e_on = z e r o s ( 1 , l e n g t h ( i_on ) ) ; % pre−a l l o c a t i o n
e _ o f f = z e r o s ( 1 , l e n g t h ( i_on ) ) ; % pre−a l l o c a t i o n
e_rr = z e r o s (1 , l e n g t h ( i _ r r ) ) ; % pre−a l l o c a t i o n
e_on ( i_on == 0 ) = 0 ;
f o r i = f i n d ( i_on )
on_index = f i n d ( ismember ( xq , i_on ( i ) ) ) ; % f i n d t h e i n d e x o f t h e t o n t r a n s i s t o r c u r r e n t
i n t h e Eon g r a p h
e_on ( i ) = Eon_data ( on_index ) ; % t o n s w i t c h i n g power
end
e _ o f f ( i _ o f f == 0 ) = 0 ;
for i = find ( i_off )
o f f _ i n d e x = f i n d ( ismember ( xq , i _ o f f ( i ) ) ) ; % f i n d t h e i n d e x o f t h e t o f f t r a n s i s t o r
c u r r e n t i n the E o f f graph
e_off ( i ) = Eoff_data ( off_index ) ; % t o f f s w i t c h i n g power
end
e _ r r ( i _ r r == 0 ) = 0 ;
for i = find ( i_rr )
r r _ i n d e x = f i n d ( ismember ( xq , a b s ( i _ r r ( i ) ) ) ) ; % f i n d t h e i n d e x o f t h e t r r d i o d e c u r r e n t
i n the Err graph
e _ r r ( i ) = Err_data ( r r _ i n d e x ) ; % t r r s w i t c h i n g power
end
P_on = sum ( e_on , ’ a l l ’ ) /Ts ;
P_off = sum ( e _ o f f , ’ a l l ’ ) /Ts ;
P_rr = sum ( e _ r r , ’ a l l ’ ) /Ts ;
%p l o t ( x_i_rr , e _ r r ) ;
%p l o t ( x _ i _ o f f , e _ o f f ) ;
%p l o t ( x_i_on , e_on ) ;

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 A.2 – Script for losses evaluation

%p l o t ( x_i_rr , e_rr , ’ r ’ , x _ i _ o f f , e _ o f f , ’ k ’ , x_i_on , e_on , ’ b ’ ) ;

A.2.2 MOSFET losses

%% APTMC120TAM33CTPAG
% r_ds = 0 . 0 7 ;
% V_d0 = 2 . 8 ;
% r_d = 0 . 0 1 4 ;
% l o a d ( ’ APTMC120TAM33CTPAG_Eoff . mat ’ ) ; %l o a d E o f f g r a p h
% l o a d ( ’APTMC120TAM33CTPAG_Eon . mat ’ ) ; %l o a d Eon g r a p h
% Eoff_IGBT = m a t f i l e ( ’ APTMC120TAM33CTPAG_Eoff . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% Eon_IGBT = m a t f i l e ( ’APTMC120TAM33CTPAG_Eon . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
% x _ o f f = Eoff_IGBT . APTMC120TAM33CTPAG_Eoff ( : , 1 ) ; %x−a x i s v a l u e E o f f
% y _ o f f = Eoff_IGBT . APTMC120TAM33CTPAG_Eoff ( : , 2 ) ; %y−a x i s v a l u e E o f f
% x_on = Eon_IGBT . APTMC120TAM33CTPAG_Eon ( : , 1 ) ; %x−a x i s v a l u e Eon
% y_on = Eon_IGBT . APTMC120TAM33CTPAG_Eon ( : , 2 ) ; %y−a x i s Value Eon

%% CCS050M12CM2
r_ds = 0 . 0 6 3 ;
V_d0 = 1 . 8 ;
r_d = 0 . 0 2 ;
l o a d ( ’ CCS050M12CM2_Eoff . mat ’ ) ; %l o a d E o f f g r a p h
l o a d ( ’ CCS050M12CM2_Eon . mat ’ ) ; %l o a d Eon g r a p h
Eoff_IGBT = m a t f i l e ( ’ CCS050M12CM2_Eoff . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
Eon_IGBT = m a t f i l e ( ’ CCS050M12CM2_Eon . mat ’ ) ; %c o n v e r s i o n t o m a t r i x of double
x _ o f f = Eoff_IGBT . CCS050M12CM2_Eoff ( : , 1 ) ; %x−a x i s v a l u e E o f f
y _ o f f = Eoff_IGBT . CCS050M12CM2_Eoff ( : , 2 ) ; %y−a x i s v a l u e E o f f
x_on = Eon_IGBT . CCS050M12CM2_Eon ( : , 1 ) ; %x−a x i s v a l u e Eon
y_on = Eon_IGBT . CCS050M12CM2_Eon ( : , 2 ) ; %y−a x i s Value Eon

%% t r i g g e r
c u r r e n t _ i n d e x = f i n d ( o u t . MOS_current . Data ) ; %i n d e x w i t h non z e r o c u r r e n t
i_MOS = o u t . MOS_current . Data ( c u r r e n t _ i n d e x ) ; %non z e r o c u r r e n t v a l u e s
t_MOS = o u t . MOS_current . Time ( c u r r e n t _ i n d e x ) ; %t i m e o f non z e r o c u r r e n t v a l u e s
t i m e _ i n d e x = f i n d ( (t_MOS >= 4 . 5 ∗ Ts ) & (t_MOS <= ( Tsim − 2∗ Ts ) ) ) ; %t i m e i n d e x a t r e g i m e
current_MOS = i_MOS( t i m e _ i n d e x ) ; %non z e r o c u r r e n t v a l u e s a t r e g i m e
p o s i t i v e _ i n d e x = f i n d ( current_MOS > 0 ) ; %i n d e x w i t h p o s i t i v e c u r r e n t a t r e g i m e
p o s i t i v e _ c u r r e n t = current_MOS ( p o s i t i v e _ i n d e x ) ; %p o s i t i v e c u r r e n t v a l u e s a t r e g i m e
t r i g g e r = f i n d ( o u t . MOS_current . Data == min ( p o s i t i v e _ c u r r e n t ) ) ; %i n d e x w i t h s m a l l e s t v a l u e o f
positive current
s t a r t _ p o i n t = o u t . MOS_current . Time ( t r i g g e r ) ; %s t a r t p o i n t = t i m e v a l u e w i t h s m a l l e s t c u r r e n t
e n d _ p o i n t = s t a r t _ p o i n t ( 1 ) + Ts ; %end p o i n t a f t e r one c o n t r o l s i g n a l p e r i o d
T_MOS = g e t s a m p l e u s i n g t i m e ( o u t . MOS_current , s t a r t _ p o i n t ( 1 ) , e n d _ p o i n t ) ; %one p e r i o d o f c u r r e n t
xMOS = 0 : ( Ts / ( l e n g t h (T_MOS. Data ) −1) ) : Ts ; %x−a x i s v a l u e s f o r p l o t
%p l o t (xMOS , T_MOS. Data ) ;

%% e d g e d e t e c t i o n
index_nz_MOS = f i n d (T_MOS. Data ) ; %i n d e x o f non z e r o c u r r e n t o v e r t h e s e l e c t e d p e r i o d
index_z_MOS = f i n d ( ~T_MOS. Data ) ; %i n d e x o f z e r o c u r r e n t o v e r t h e s e l e c t e d p e r i o d
r i s i n g _ e d g e s = f i n d ( ismember ( ( index_nz_MOS ) , ( index_z_MOS+1) ) ) ; %s e a r c h i n g f o r on e d g e s
p o s i t i v e _ p e a k = index_nz_MOS ( r i s i n g _ e d g e s ) ; %on e d g e s i n d e x
on_peak = T_MOS. Data ( u n i o n ( p o s i t i v e _ p e a k , index_z_MOS ) ) ; %r i s i n g e d g e s c u r r e n t v a l u e s
x_on_peak = xMOS( u n i o n ( p o s i t i v e _ p e a k , index_z_MOS ) ) ; %r i s i n g e d g e t i m e v a l u e s
%p l o t ( x_on_peak , on_peak , ’ b . ’ , xMOS,T_MOS. Data ) ;
f a l l i n g _ e d g e s = f i n d ( ismember ( ( index_nz_MOS ) , ( index_z_MOS−1) ) ) ; %s e a r c h i n g f o r o f f e d g e s
n e g a t i v e _ p e a k = index_nz_MOS ( f a l l i n g _ e d g e s ) ; %o f f e d g e s i n d e x
o f f _ p e a k = T_MOS. Data ( u n i o n ( n e g a t i v e _ p e a k , index_z_MOS ) ) ; %f a l l i n g e d g e s c u r r e n t v a l u e s
x_off_peak = xMOS( u n i o n ( n e g a t i v e _ p e a k , index_z_MOS ) ) ; %f a l l i n g e d g e s t i m e v a l u e s
%p l o t ( x_off_peak , o f f _ p e a k , ’ b . ’ , xMOS,T_MOS. Data ) ;
%p l o t (xMOS,T_MOS. Data , ’ g ’ , x_off_peak ( o f f _ p e a k ~=0) , o f f _ p e a k ( o f f _ p e a k ~=0) , ’ b ∗ ’ , x_on_peak (
on_peak ~=0) , on_peak ( on_peak ~=0) , ’ r . ’ )
t o n _ i n d e x = f i n d ( on_peak >= 0 ) ; %i n d e x o f a l l t r a n s i s t o r t o n
t o f f _ i n d e x = f i n d ( o f f _ p e a k >= 0 ) ; %i n d e x o f a l l t r a n s i s t o r t o f f
t r r _ i n d e x = f i n d ( on_peak <= 0 ) ; %i n d e x o f a l l d i o d e t o n ( d i o d e t o f f can be n e g l e c t e d )
i_on = round ( on_peak ( t o n _ i n d e x ) , 4 ) . ’ ; %t r a n s i s t o r c u r r e n t on t o n
x_i_on = x_on_peak ( t o n _ i n d e x ) ; %t i m e v a l u e s o f i_on
i _ o f f = round ( o f f _ p e a k ( t o f f _ i n d e x ) , 4 ) . ’ ; %t r a n s i s t o r c u r r e n t on t o f f
x _ i _ o f f = x_off_peak ( t o f f _ i n d e x ) ; %t i m e v a l u e s o f i _ o f f
i _ r r = round ( on_peak ( t r r _ i n d e x ) , 4 ) . ’ ; %d i o d e c u r r e n t on t o n
x_i_rr = x_on_peak ( t r r _ i n d e x ) ; %t i m e v a l u e s o f i _ r r

%% c o n d u c t i o n l o s s e s
pcm_index = f i n d (T_MOS. Data >= 0 ) ; %t r a n s i s t o r i n d e x , t r a n s i s t o r i s on d u r i n g t h e p o s i t i v e
part
p_cm = (T_MOS. Data ( pcm_index ) . ^ 2 ) . ∗ r_ds ;
pcd_index = f i n d (T_MOS. Data <= 0 ) ; %d i o d e i n d e x , d i o d e i s on d u r i n g t h e n e g a t i v e p a r t

115
 A – MATLAB codes

p_cd = a b s (T_MOS. Data ( pcd_index ) ) . ∗ V_d0 + (T_MOS. Data ( pcd_index ) . ^ 2 ) . ∗ r_d ;

x_cm = xMOS( pcm_index ) ;
x_cd = xMOS( pcd_index ) ;
Pcd = t r a p z ( x_cd , p_cd ) /Ts ;
% Pct = t r a p z (x_cm , p_cm) /Ts ;
% Pct = ( max (T_MOS. Data ( pcm_index ) ) . ^ 2 ) . ∗ ( ( 1 / 8 + (ma_SPWM∗ c o s _ p h i ) / ( 3 ∗ p i ) ) ∗ r_ds ) ;
Pcd = max ( a b s (T_MOS. Data ( pcd_index ) ) ) . ∗ ( V_d0 ∗ ( 1 / ( 2 ∗ p i ) − (ma_SPWM∗ c o s _ p h i ) / 8 ) ) + ( max ( a b s (T_MOS.
Data ( pcd_index ) ) ) . ^ 2 ) . ∗ ( ( 1 / 8 − (ma_SPWM∗ c o s _ p h i ) / ( 3 ∗ p i ) ) ∗r_d ) ;
%p l o t ( x_cd , p_cd , x_cm , p_cm) ;

%% s w i t c h i n g l o s s e s
xq = round ( ( 0 : 0 . 0 0 0 1 : 2 0 0 ) , 4 ) ; %g e n e r a t e a l l t h e c u r r e n t v a l u e s o f E o f f , Eon , E r r
E o f f _ d a t a = i n t e r p 1 ( x _ o f f , y _ o f f , xq , ’ p c h i p ’ ) ; %i n t e r p o l a t e d a t a s h e e t c u r v e
Eon_data = i n t e r p 1 ( x_on , y_on , xq , ’ p c h i p ’ ) ; %i n t e r p o l a t e d a t a s h e e t c u r v e
Err_data = i n t e r p 1 ( x_on , y_on , xq , ’ p c h i p ’ ) ; %i n t e r p o l a t e d a t a s h e e t c u r v e
p_on = z e r o s ( 1 , l e n g t h ( i_on ) ) ; %pre−a l l o c a t i o n
p _ o f f = z e r o s ( 1 , l e n g t h ( i_on ) ) ; %pre−a l l o c a t i o n
p_rr = z e r o s ( 1 , l e n g t h ( i _ r r ) ) ; %pre−a l l o c a t i o n
p_on ( i_on == 0 ) = 0 ;
f o r i = f i n d ( i_on )
on_index = f i n d ( ismember ( xq , i_on ( i ) ) ) ; %f i n d t h e i n d e x o f t h e t o n t r a n s i s t o r c u r r e n t i n t h e
Eon g r a p h
p_on ( i ) = Eon_data ( on_index ) ; %t o n s w i t c h i n g power
end
p _ o f f ( i _ o f f == 0 ) = 0 ;
for i = find ( i_off )
o f f _ i n d e x = f i n d ( ismember ( xq , i _ o f f ( i ) ) ) ; %f i n d t h e i n d e x o f t h e t o f f t r a n s i s t o r c u r r e n t i n t h e
E o f f graph
p_off ( i ) = Eoff_data ( off_index ) ; %t o f f s w i t c h i n g power
end
p_rr ( i _ r r == 0 ) = 0 ;
for i = find ( i_rr )
r r _ i n d e x = f i n d ( ismember ( xq , a b s ( i _ r r ( i ) ) ) ) ; %f i n d t h e i n d e x o f t h e t r r d i o d e c u r r e n t i n
the Err graph
p_rr ( i ) = Err_data ( r r _ i n d e x ) ; %t r r s w i t c h i n g power
end
%p l o t ( x_i_rr , p_rr ) ;
%p l o t ( x _ i _ o f f , p _ o f f ) ;
%p l o t ( x_i_on , p_on ) ;
P_on = sum ( p_on , ’ a l l ’ ) /Ts ;
P_off = sum ( p _ o f f , ’ a l l ’ ) /Ts ;
P_rr = sum ( p_rr , ’ a l l ’ ) /Ts ;

A.3 Scripts for capacitance evaluation

Spectrum of the DC-link current

%% i n p u t c u r r e n t
DC = mean ( o u t . IDC . Data ) ;
AC = o u t . IDC . Data − DC;
Ic_rms = rms (AC) ;
Pdc = Vdc∗DC;

%% FFT
d t = o u t . IDC . Time ( 2 ) − o u t . IDC . Time ( 1 ) ; % resolution
Dec_factor = 1 ; % decimation factor
C u r r e n t = repmat ( downsample (AC , D e c _ f a c t o r ) , 1 , 1 0 ) ;
t_s = o u t . IDC . Time ; % sampling period
N = l e n g t h ( Current ) ; % signal length
t = 0 : d t ∗ D e c _ f a c t o r : ( N−1)∗ d t ∗ D e c _ f a c t o r ; % time v e c t o r
I a c = AC( t > 0 . 8 ∗ t ( end ) ) ; % current at regime
N_fft = l e n g t h ( I a c ) ;
f _ f f t = 0 . 5 / ( d t ∗ D e c _ f a c t o r ) ∗ l i n s p a c e ( 0 , 1 , N _ f f t /2+1) ;
Iac_FFT = f f t ( I a c ) / N _ f f t ; % single s i d e d FFT

%% p l o t s i n g l e −s i d e d a m p l i t u d e s p e c t r u m .
figure ;
s e m i l o g x ( f _ f f t , 2∗ a b s ( Iac_FFT ( 1 : N _ f f t /2+1) ) , ’ linewidth ’ , 2) ;
t i t l e ( ’ S i n g l e −S i d e d Amplitude Spectrum ’ ) ;
x l a b e l ( ’ F r e q u e n c y ( Hz ) ’ ) ;
ylabel ( ’| I ( f ) | ’) ;
g r i d on ;

116
 A.3 – Scripts for capacitance evaluation

Capacitance value
clear all ;
clc ;

%% DC l i n k
P = 20 e 3 ; % a c t i v e power
Vdc = 7 0 0 ;
I d c = P/Vdc ;
Ipk_max = 2∗ I d c ;

%% PWM
Fs = 5 0 ; % control signal frequency
Ts = 1/ Fs ;
f s w = 20 e 3 ; % switching frequency
ma = 0 . 5 3 ; % worst case modulation index
d l y = 1 e −9; % blank time

%% l o a d
Vrms = Vdc∗ma/ s q r t ( 2 ) ; % worst case l i n e rms v o l t a g e
cos_phi = 1 ; % worst case
phi = acos ( cos_phi ) ;
Q = P∗ s i n ( p h i ) / c o s ( p h i ) ; % inductive r e a c t i v e power

%% s i m u l a t i o n p a r a m e t e r s
Tsamp = 2 e −6; % sampling time ( Nyquist h o l d s )
Tsim = 20/ Fs ; % s i m u l a t i o n time

%% s i m u l i n k
svm = sim ( ’MOS_svpwm’ ) ;
IDC = svm . IDC . Data ;
xIDC = svm . IDC . Time ;
SOS = f i n d ( xIDC == 15∗ Ts ) ;
DC = mean ( IDC ( SOS : end ) ) ;
AC = IDC ( SOS : end ) − DC;
I r m s = rms (AC) ;
Pdc = Vdc∗DC;
Iph_max = max ( svm . IGBT_current . Data ) ;
min_max_Ic = [ max (AC) a b s ( min (AC) ) ] ;
Ic_max = max ( min_max_Ic ) ;
IC = cumtrapz ( xIDC ( SOS : end ) , AC) ;
% p l o t ( svm . IDC . Time ( SOS : end ) , IC ) ;
I r i p p l e = max ( IC ) − min ( IC ) ;
V r i p p l e = 0 . 0 1 ∗ Vdc : 0 . 0 1 ∗ Vdc : 0 . 2 ∗ Vdc ;
ESR = V r i p p l e /Ic_max ; % max p a r a s i t i c r e s i s t a n c e
C_vpp = ( V r i p p l e . ^ − 1 ) . ∗ I r i p p l e ;
Csweep = 10 e −6:10 e −6:900 e −6;
Vrpp = ( Csweep . ^ − 1 ) . ∗ I r i p p l e ;
figure ;
s e t (0 , ’ DefaultLineLineWidth ’ , 2) ;
p l o t ( V r i p p l e , C_vpp , ’ k ’ ) ;
t i t l e ( ’ Capacitance with r e s p e c t r i p p l e amplitude ’ ) ;
x l a b e l ( ’ Voltage [V] ’ ) ;
y l a b e l ( ’ Capacitance [C] ’ ) ;
g r i d on ;
h o l d on ;
figure ;
p l o t ( V r i p p l e , ESR , ’ k ’ ) ;
t i t l e ( ’ ESR w i t h r e s p e c t r i p p l e a m p l i t u d e ’ ) ;
x l a b e l ( ’ Voltage [V] ’ ) ;
y l a b e l ( ’ ESR [ ohm ] ’ ) ;
g r i d on ;
h o l d on ;
figure ;
p l o t ( Csweep , Vrpp , ’ k ’ ) ;
t i t l e ( ’ R i p p l e ampltude w i t h r e s p e c t c a p a c i t a n c e ’ ) ;
x l a b e l ( ’ Capacitance [C] ’ ) ;
y l a b e l ( ’ Voltage [V] ’ ) ;
g r i d on ;
h o l d on ;
C e s t = 118 e −06;
ESRest = 0 . 5 8 ;
nCAP = 4 ; % number o f p a r a l l e l c a p a c i t o r s
nC = C e s t /nCAP ;
nESR = nCAP∗ ESRest ;
nDC = mean ( IDC ( SOS : end ) . ∗ ( nCAP^ −1) ) ;
nAC = ( IDC ( SOS : end ) . ∗ ( nCAP^ −1) ) − nDC ;
nRMS = rms (nAC) ;

117
118
Appendix B

SIMULINK models

B.1 Inverter with IGBT and Sinusoidal PWM

Figure B.1. First section of the SIMULINK model for the evaluation of IGBT
losses with Sinusoidal PWM.

119
 B – SIMULINK models

Figure B.2. Second section of the SIMULINK model for the evaluation of IGBT
losses with Sinusoidal PWM.

120
 B.1 – Inverter with IGBT and Sinusoidal PWM

+
1

s1 s3 s5

g
m

m
E

E
m1 m3 m5

3
A
4
B
5
C

s2 s4 s6
C

g
m

m
E

m2 m4 m6

-
2

Figure B.3. Subsystem "INVERTER" (Figure B.2) of the three-phase in-

verter with IGBT transistors.

121
 B – SIMULINK models

ab

1
bc
V line

ca

1 +
v Vab Van
- ab an
A
AB

2 +
v Vbc Vbn 2
- bc bn
B V phase
BC

3 +
v Vca Vcn
- ca cn
C
CA
V PHASE

Figure B.4. Subsystem "MEASUREMENT" (Figure B.2) for the evaluation

of phase and line voltages.

122
 B.1 – Inverter with IGBT and Sinusoidal PWM

1e-07 s s1

t
<= 0
1e-07 s s2

1e-07 s s3
1
t Q OUT
<= 0
1e-07 s s4

1e-07 s s5

t
<= 0
1e-07 s s6

Figure B.5. Subsystem "S PWM" (Figure B.1) for the generation of
the Sinusoidal PWM.

123
 B – SIMULINK models

Current Control

f u n c t i o n PWR = f c n (Pnom , Imax , cos_phi , V l l )

Iph = Pnom/ ( s q r t ( 3 ) ∗ V l l ∗ cos_phi ) ;

p h i = a c o s ( cos_phi ) ;

i f Iph ∗ s q r t ( 2 ) >= Imax

P = s q r t ( 3 / 2 ) ∗ V l l ∗Imax∗ cos_phi ;
Q = P∗ s i n ( ph i ) / c o s ( ph i ) ;
else
P = Pnom ;
Q = P∗ s i n ( ph i ) / c o s ( ph i ) ;
end

PWR = [ P Q ] ;

V PHASE

f u n c t i o n [ Van , Vbn , Vcn ] = v o l t a g e s ( Vab , Vbc , Vca )

Van=(Vab−Vca ) / 3 ;
Vbn=(Vbc−Vab ) / 3 ;
Vcn=(Vca−Vbc ) / 3 ;

124
 B.2 – Inverter with IGBT and Space-Vector PWM

B.2 Inverter with IGBT and Space-Vector PWM

Figure B.6. First section of the SIMULINK model for the evaluation of IGBT
losses with Space-Vector PWM.

125
 B – SIMULINK models

Figure B.7. Second section of the SIMULINK model for the evaluation of IGBT
losses with Space-Vector PWM.

126
 Figure B.8. Subsystem "SV PWM" (Figure B.6) for the generation of the
B.2 – Inverter with IGBT and Space-Vector PWM

t
U
1e-07 s s1
t
<= 0
1e-07 s s2
12:34 t Voltage_U Voltage_U dutyU V t
sample time 1e-07 s s3
1
m Voltage_V Voltage_V dutyV t Q OUT
<= 0
1e-07 s s4
modulatio index
Fs Voltage_W Voltage_W dutyW t

127
control frequency 1e-07 s s5
CONTROL WAVES Reference voltage
t
<= 0
1e-07 s s6
W

Space-Vector PWM.
 B – SIMULINK models

B.3 Inverter with power MOSFET and Sinusoidal

PWM

Figure B.9. First section of the SIMULINK model for the evaluation of power
MOSFET losses with Sinusoidal PWM.

128
 B.3 – Inverter with power MOSFET and Sinusoidal PWM

Figure B.10. Second section of the SIMULINK model for the evaluation of power
MOSFET losses with Sinusoidal PWM.

129
 B – SIMULINK models

+
1

s1 s3 s5

g
m

m
S

S
m1 m3 m5

3
A
4
B
5
C

s2 s4 s6
D

g
m

m
S

m2 m4 m6

2
-

Figure B.11. Subsystem "INVERTER" (Figure B.10) of the three-phase inverter

with power MOSFET transistors.

130
 B.4 – Inverter with power MOSFET and Space-Vector PWM

B.4 Inverter with power MOSFET and Space-

Vector PWM

Figure B.12. First section of the SIMULINK model for the evaluation of power
MOSFET losses with Space-Vector PWM.

131
 B – SIMULINK models

Figure B.13. Second section of the SIMULINK model for the evaluation of power
MOSFET losses with Space-Vector PWM.

132
Appendix C

Electric schematic of the

prototype

C.1 Flyback power supply

133
 C – Electric schematic of the prototype

C.2 Blocks of the gate driver board

134
 C.3 – Gate driver

C.3 Gate driver

135
 C – Electric schematic of the prototype

C.4 12V-to-5V buck converter

136
 C.5 – Current sense amplifier and LDO

C.5 Current sense amplifier and LDO

137
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