Application Design Guidelines For LM339, LM393, TL331 Family Comparators Including The New B-Versions
Application Design Guidelines For LM339, LM393, TL331 Family Comparators Including The New B-Versions
Application Report
Application Design Guidelines for LM339, LM393, TL331
Family Comparators Including the New B-versions
Paul Grohe Including LM393B, LM2903B, LM139, LM239, LM193, LM293, LM2901, LM2903 and LM397
ABSTRACT
The TL331, LM339, LM393, and the next generation B-versions (LM393B and LM2903B) are a popular and
long-lived family of standard comparators due to their flexibility, availability, and cost-effectiveness. It is important
to understand how these comparators are different than most other comparators before using them in your
design. The information in this application guide will help promote first time design successes.
Table of Contents
1 Devices Covered in Application Note................................................................................................................................... 2
2 Input Considerations..............................................................................................................................................................4
3 Output Stage Considerations.............................................................................................................................................. 10
4 Power Supply Considerations.............................................................................................................................................12
5 General Comparator Usage................................................................................................................................................. 12
6 Conclusion............................................................................................................................................................................ 14
7 Related Documentation........................................................................................................................................................15
8 Revision History................................................................................................................................................................... 15
List of Figures
Figure 2-1. Simplified Input Stage Schematic with All Current Source Connections...................................................................4
Figure 2-2. Headroom Taken Up by VBE's and VSAT of Input Stage......................................................................................... 5
Figure 2-3. Visual Representation of Input Voltage Range With a 5 V Supply............................................................................ 6
Figure 2-4. Input Pin I/V Curve with 5 V Supply.......................................................................................................................... 7
Figure 2-5. Series Resistor And Diode Negative Voltage Protection...........................................................................................8
Figure 2-6. Commonly Used Two-Resistor Voltage Divider with Clamping Diode.......................................................................9
Figure 2-7. Split Voltage Divider Negative Voltage Protection.....................................................................................................9
Figure 3-1. Typical Output Low (Saturation) Voltage vs Output Sinking Current.......................................................................10
Figure 5-1. Best Connections Practices for Single and Dual Supplies...................................................................................... 13
Figure 5-2. Less Than Acceptable Connection Practices for Single and Dual Supplies........................................................... 13
Figure 5-3. Potentially Harmful Connection Practices for Single and Dual Supplies.................................................................13
List of Tables
Table 1-1. Base Part Number, Channel Count, and Temperature Range....................................................................................2
Table 1-2. Maximum Input Offset Error at 25°C for Each Base Part Number with VIO Grade Options........................................3
Trademarks
All trademarks are the property of their respective owners.
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Devices Covered in Application Note www.ti.com
Part numbers in bold have operating temperature regions that match the given temperature range exactly. Part
numbers that are not in bold can operate within and beyond the given temperature range.
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2 Input Considerations
2.1 Input Stage Schematic
The simplified LM339 Family comparator internal schematic is shown in Figure 2-1. Minus a few devices in the
biasing circuitry, the schematic is a fairly true representation of the actual internal circuit.
The input stage consists of the PNP Darlington Input Pairs Q1+Q2, and Q3+Q4, the bias mirror Q10 to provide
the operating tail currents, and the active load of Q5 and Q6. The output stage is comprised of Q7, Q12 and
output transistor Q8. Diodes D1 through D4 protect the input devices when the inputs are taken above V+.
VCC
Internal
Q9 Q10 Q11 Q12
Bias
Itail
D2 D3
D1 D4
Q2 Q3
Output
+ Input - Input
I1 I2
Q1 Q4
Q8
Q7
Q5 Q6
Figure 2-1. Simplified Input Stage Schematic with All Current Source Connections
The schematic also contains additional current source lines (Q9, D2, Q11, and D3) not drawn in the simplified
schematic found in the data sheets. All PNP emitters in the Darlington input stage have current source
connections. These current sources ensure a consistent input bias current that does not vary with the differential
input voltage. This consistent current provides a high effective input to input resistance. Without these secondary
current sources, the input bias current would vary from zero to twice the normal bias current as the differential
input voltage is varied.
2.2 Input Voltage Range
The data sheet specified input voltage range indicates the allowable minimum and maximum voltages to be
applied to the inputs for normal specified operation. When operated outside the specified input range, parametric
changes will occur, particularly offset voltage, bias current and propagation delay.
The specified LM339 Family input voltage range (VICR) is 0 V (relative to the negative supply pin) to VCC – 1.5 V
at room temperature. However, the actual upper input voltage range reduces by -4 mV/°C at cold temperatures.
Therefore the specified LM339 Family full temperature range common mode range is 0 V to VCC – 2 V to
account for this reduction. The VCC – 2 V range is strongly recommended for use in all designs.
2.3 Input Voltage Range vs. Common Mode Voltage Range
The phrases Common Mode Voltage Range and Input Voltage Range tend to be used interchangeably, but
there is an important difference when discussing comparators. The common definition of Common Mode Voltage
(CMVR or CMR) is the average of the inverting (-IN) and non-inverting (+IN) input voltages. This definition
acceptable for operational amplifiers where the inputs are kept to less than a millivolt of each other due to
negative feedback, but comparator inputs are rarely kept at the same potential and can see several volts of
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differential voltage under normal operation. If the average value is used, there can be an instance where one
input voltage slightly exceeds the input range specification, and the average of the two inputs can still reside
within the input range, even though that one input is violating the input range. The average gives a false
impression of meeting the input voltage range requirement.
Note
The input voltage limits must be considered per input and NOT the average of the two input voltages.
If, for example, the calculated input voltage limit is 3.5 V, then neither input can exceed 3.5 V.
5V
Internal
Q9 Q10 Q11 Q12
Bias
Vsat10
Itail
4.7V
D2 D3
Vbe2
D1 D4
Q2 Q3
4.1V 4.1V Output
Vbe1
+ Input - Input
I1 I2
Q1 Q4
3.5V 3.5V
Q8
Q7
Q5 Q6
The DC biasing current flows down from VCC , through the Q10 current source, through the input pair Q2 and
Q1, and out of the input pin towards ground through the input source resistance.
The required headroom can be analyzed by Counting VBE's, starting at the VCC rail and down to the input pin.
Starting at VCC, about 250-300mV is dropped across the current source Q10 collector-emitter junction (VSAT10).
Another 600mV is dropped across each of the Base-Emitter junctions of Q2 (VBE2) and Q1 (VBE1). By adding
all the drops together (VSAT10 + VBE1 + VBE2 ), it can be seen that there needs to be at least a 1.5 V headroom
between the input pin and VCC for the input stage to bias properly.
If an input is brought above the input limit, that input transistor starts to turn off, and the tail current for that
device (I1 or I2) is also cut off.
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Figure 2-3 shows a visual representation of the input voltage range with a single +5 V supply.
Between 0 V and 3 V (VCC - 2V), the device is fully operational and will function per data sheet specifications
over the full specified temperature range. The VCC - 2V limit is the recommended upper input range limit to be
utilized for all designs.
The input range from 0 to 3.5 V (VCC - 1.5V) is valid at 25°C and above. The range between 3 V and 3.5 V
will vary over temperature due to the VBE's of the transistors changing at -2.1mV/°C. This results in the input
voltage range changing at -4.2mV/°C over temperature (note the negative sign!), necessitating the VCC - 2 V
over temperature specification. Using the VCC - 1.5 V limit is the main cause of It worked fine on the bench, but it
fails at cold complaints. Do not make this mistake!
The range between 3.5 V and 4 V is the gray zone, where the device appears to still function at 25°C and above,
but critical specifications are deteriorating, such as offset voltage, bias current and particularly propagation
delay as the input stage is gradually cut off. These effects may not be immediately apparent. Operating at low
temperatures will cause failures. Operation in this zone must be avoided.
Between 4 V and 5 V, and even up to 36 V, the input stage is cut off and input bias current is falls to zero. The
actual cut-off threshold depends on temperature. Comparator operation ceases. DO NOT operate in this area!
2.5 Input Voltage Range Feature
A nice feature of the LM339 family (and ONLY applies to the LM339 family devices listed in Table 1-2) is that
only one input needs to be within the valid input voltage range for a valid output. The other input can be above
the input voltage range or, even above VCC and the output will be in the expected state.
Note
The following feature was originally intended to reassure users of expected behavior during fault
conditions or transient conditions. It is described here only because it has been mentioned in the data
sheets over the years. TI strongly advises to stay within the specified input voltage range limits
and not to rely on the following feature as part of normal operating conditions. The device will
not meet full data sheet specifications in this mode.
This occurs because as long as one of the inputs is still within the valid input voltage range, that input pairs tail
current (I1 or I2) is still flowing, signaling the correct output polarity to the active loads Q5 and Q6.
If both inputs exceed the upper input voltage range, both I1 and I2 are cut off, so Q7 remains off, which allows
the base of Q8 to be pulled-up and saturate, pulling the output low.
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Because the inputs have no internal clamp or ESD diodes to VCC, the input voltage can exceed the VCC voltage
up to a maximum of 36V. If this occurs, the input will block current flow due to a reverse biased diode forming in
the input PNP transistor. Current flow is blocked even if VCC equals 0 V. If either input or both inputs exceed the
maximum 36V VCC rating, junction breakdown can occur. This may lead to permanent device damage per the
table notes in the respective device's data sheet Absolute Maximum Ratings table.
If either input is lower than –0.3 V with respect to the negative supply, excessive input current can flow in the
substrate and the output may display phase reversal, also called inversion. See the Section 2.6 section below for
further information.
While this is a nice feature, it does come at a cost. When operating outside the specified input voltage limits,
performance deteriorates and will no longer meet the data sheet specifications. Critical specifications such as
offset voltage, bias current and propagation delay will be adversely affected. TI still recommends to stay within
the data sheet input voltage range specifications.
2.6 Negative Input Voltages
The LM339 family does not like negative input voltage on any I/O pins, and this is mentioned several times in
the data sheets. The LM339 family is built using a junction-isolated die process, wherein all the individual on-die
devices are electrically separated from the substrate by a reversed PN junction. This can be thought of as a
reversed diode under every circuit node to a common die substrate. These junctions are commonly referred to
as the Body Diode or Substrate Diode. For this junction isolation to function properly, the substrate must be
maintained at the most negative potential. The die substrate is electrically tied to the GND pin, and thus the GND
pin must be at the most negative circuit potential for proper operation.
If any pin is brought more negative than the GND pin (substrate), these various substrate junctions will start to
conduct. Reverse currents now flow in paths that were not designed for current flow and this can cause parasitic
devices to appear, leading to malfunctions, or worse, latch-up if the input current is high enough.
Figure 2-4 shows the input current of the input pin with a +5 V supply, sweeping the input from -1 V to +7 V.
Noticeable nanoamp currents will start to flow when the input is at -0.3 V, and will increase to several tens of
milliamps as the diodes start to conduct.
10 nA
C
0 nA
-10 nA
Input Current
-20 nA B
-30 nA
-40 nA
A
-50 nA
-60 nA
-1 V 0V 1V 2V 3V 4V 5V 6V 7V
Input Voltage
Section A shows the substrate diode knee starting to conduct at -400mV, with the subsequent increase in
reverse current as the negative input voltage is increased.
Section B shows the normal operating Input Bias Current from 0 V up to 3.5 V. The gray zone can be seen as
the current heads up towards zero after 4 V.
Section C shows the near zero (picoamp) bias currents as the input devices are reversed and cut off and no
base current flows.
When the LM339 Family was originally designed in the early 70's, Electrostatic Discharge (ESD) damage was
not as prevalent due to the high breakdown voltages of these older processes, so dedicated ESD protection
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structures were not included in the LM339 family. Without dedicated ESD structures, there is not a defined
current path for reverse currents back to the GND pin.
2.7 Phase Reversal
Under certain conditions, the polarity of the output can become incorrect. This scenario, called phase reversal,
occurs when the input of the comparator violates the negative common-mode voltage range. As explained
above, exceeding the positive common mode range tends to result in predictable behavior. But a negative input
voltage, relative to the GND pin, may come from unexpected sources, such as switching noise or ground bounce
from DC to DC converters. Negative input voltages can also arise from AC cap coupled inputs that create a
bipolar voltage at the input.
An input voltage of less than –0.3 V can cause parasitic diode conduction (Figure 2-4, point A) that results
in incorrect output behavior. Operation in this region is not defined in the data sheet as it violates the -0.3V
absolute maximum specification for input voltage. The input current turns on internal parasitic NPN transistors
that steal current from other internal nodes causing output phase reversal.
Do not try to determine phase reversal performance empirically as different units may have different
performance. Negative input voltages must be avoided, assuming a single supply configuration, unless the
application can accept either the VOL or VOH level during the duration of the negative input.
2.8 Output to Input Cross-Talk
To prevent oscillations and false-triggering, the output and input traces need to be kept separated when the
source impedance is greater than 25kΩ, The fast output edge rates (< 200ns) can couple through the stray
capacitance back into the high-impedance input, particularly at high output voltage swings (>10 V). This is
important for the dual LMx93 where the inverting input is next to the output pin. The input and output traces must
be run at right angles to each-other and never in parallel.
2.9 Protecting Inputs from Negative Voltages
2.9.1 Simple Resistor and Diode Clamp
In cases where a negative input voltage cannot be avoided, such as ringing from inductive sources of bipolar
outputs or from direct coupled sensors, a current limiting resistor in series with the input can limit the current to a
safe level, as shown in Figure 2-5. The diode must be a Schottky type for lowest forward voltage.
The resistor must be calculated to limit the current to 1mA or less at the highest expected voltage. A rule of
thumb is 1kΩ per volt of expected over-voltage. So if the maximum expected negative voltage is -5V, the resistor
must be at least 5kΩ or greater. This resistance can be part of the divider or other resistive input network. A
similar resistance can be added to the other input for bias current cancellation. The size of the resistor is a
compromise between minimum clamp current, bias current error and minimum added delay for AC signals.
VCC
RI
+
±VAC ±
D1
VREF
If the resistor value is too high, interaction with the comparator input bias current and leakage currents of the
diode can cause shifts in the threshold points. High resistor values can also cause delays in AC signals due to
the time constant of the input and stray capacitance and the resistor.
If the resistor value is too low, the forward voltage of the diode will increase due to the higher clamp current, as
well as load-down the source while clamping. Lower values are better for AC signals due to the lower delay.
The disadvantage of this simple clamp approach is that the forward voltage of the diode can exceed the -300mV
input limit, even when using low forward voltage Schottky type diode.
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If large negative input voltages are expected, such as zero crossing detectors or input signals with inductive
ringing, which require clamping the negative portion of the input signal, then a low ratio voltage divider must then
be used. See Section 2.9.2.1.
2.9.2 Voltage Divider with Clamp
A very common circuit to measure a bipolar high voltage is a resistor divider with a clamping diode is shown
in Figure 2-6. The problem is that the diode does not start clamping the negative until -600mV, well past the
-300mV negative input voltage limit.
R1
±10V +1V to -0.6V
+
90 NŸ
R2 ±
D1
10 NŸ VREF
Figure 2-6. Commonly Used Two-Resistor Voltage Divider with Clamping Diode
The upper common voltage divider resistor R1 is split into two resistors, R1A and R1B, providing a higher
voltage tap sample point for the clamp diode. The clamp diode ensures that the tap voltage does not exceed
-600mV as the input voltage moves further negative.
With a positive input voltage, the diode is reverse biased and does not conduct, effectively removing it from the
circuit (except for some small leakage current). The voltage divider R1A + R1B combine create the upper R1
voltage divider resistor against R2.
When the input voltage is negative, the diode clamps the node between R1A and R1B to -600mV. R1B and R2
then create a 3x voltage divider, which results in a safer -200mV on the input. Note that R1A will then have the
full input voltage across it and needs to be sized appropriately.
The design procedure is fairly simple. The full divider is calculated as a normal two resistor voltage divider,
deriving the needed R1 and R2 values. The desired secondary negative R1B divider is then calculated from the
existing R2 and required portion of R1.
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10
VO – Saturation Voltage – V
1
TA = 125°C
TA = 25°C
0.1
TA = –55°C
0.01
0.001
0.01 0.1 1 10 100
Figure 3-1. Typical Output Low (Saturation) Voltage vs Output Sinking Current
The graph also shows the current limit, where the output voltage sharply inflects upwards in the 10-20mA region.
This region must be avoided as the specified minimum short circuit current is only 6mA (typically 12-16mA) and
can vary across devices, lots and temperature. TI recommends sinking currents of less than 5mA.
This graph must also be used to determine the pull-up resistor value needed for a desired output low voltage.
For example, if a 3.3kΩ resistor is used on a 3.3 V pull-up voltage, the resulting current is 1mA when sinking.
From the graph, 1mA will result in a worst-case (125°C) VOL voltage of 90mV. However, if a 330 ohm pull-up
resistor is used, the output low voltage is now 350mV, and is also uncomfortably close to the current limit.
3.2 Pull-Up Resistor Selection
An open collector output requires a pull-up resistor for the output to go High. An often overlooked design item
is the pull-up resistor value. If the pull-up resistor value is too low, the low pull-up current is too high, which
results in the output low voltage (VOL) increasing, causing excessive output power dissipation and increased
overall system supply currents. What is suitable for a 3.3 V pull-up voltage may not be suitable for a 24 V pull-up
voltage!
If the pull-up resistor value is too high, this will result in a larger risetime. The risetime will vary with capacitive
load as the risetime is dependant on the time constant of the pull-up resistor and the load capacitance.
The result is an exponential risetime instead of a square edge and can effect the overall propagation delay.
Falltime is not dependant on the pull-up resistor as the output transistor immediately shorts the output, quickly
discharging the load capacitance through a low impedance.
If risetime is not critical, a higher resistor value can be used to further save system power.
TI recommends a pull-up resistor low current in the range of 100uA to 1mA for the best compromise of output
swing and risetime. For example, With a 5 V pull-up voltage and 1mA current, the resistor value would be
VPULL-UP / 1mA = 5kΩ. A 4.7k or 5.1k resistor would suffice, as the exact value is not critical. The proper
pull-up resistor can be derived from the output saturation curve shown in Figure 3-1 above. With multiple
channel devices, be sure to include the power dissipation of each channel in the total package power dissipation
calculation.
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Ok: VOL Full VID (VCC < 32 V) Ok: VOL (IIB Biased)
10k
+ +
VCC 10k
+ +
VCC
10k 10 Meg
VCC ± ± ± ±
GND GND
GND GND
Ok: VOL Half VID Ok: VOL Half VID Ok: VOL (IIB Biased)
Figure 5-1. Best Connections Practices for Single and Dual Supplies
Increasing the input resistor to 10 MΩ would ensure linear operation as the input bias current (Ib), which flows
out of the input pin towards ground, would raise the non-inverting input voltage beyond the input offset voltage
range. VOL Full VID is better suited for lower voltage applications as there is no reason to apply a large input
voltage difference even though the comparator allows it. The VOL (IIB Biased) method uses the input bias current
to raise the voltage on the inverting input. If used, place the 10-MΩ resistor close to the inverting input pin to
reduce noise pickup. No inputs may be connected directly to low impedance nodes such as ground, VCC or VEE.
VOH alternatives are also acceptable; just swap the input pins.
The next set of connections in Figure 5-2 is not recommended, but these configurations are not considered
harmful methods of terminating unused channels. The VOH alternatives that swap the inputs are also not
recommended methods of terminating unused channels.
Poor: VOL (Open Input) Poor: VOL Full VID (VCC > 32 V) Poor: VOL (Open Input) Poor: VOL Full VID (VCC > 32 V)
Figure 5-2. Less Than Acceptable Connection Practices for Single and Dual Supplies
The last set of connections, shown in Figure 5-3, demonstrates improper setups that could cause output noise
chatter or device damage if the GND pin were to ever become positive relative to the input pin.
Wrong: No Input Difference
Wrong: No Resistors Wrong: No Resistors
Wrong: No Resistors
VCC VCC
+ +
VCC + + + +
± ± ± ± ± ±
GND GND
GND GND VEE
VCC
+ +
VCC + +
± ± ± ±
GND
VEE VEE
GND
Figure 5-3. Potentially Harmful Connection Practices for Single and Dual Supplies
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7 Related Documentation
7.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
• LMx39 (TI version) Core Data Sheet
• LMx39-N (National version) Core Data Sheet
• LMx93 Data Sheet (TI Version) Core Data Sheet
• LMx93-N (National Version) Core Data Sheet
• TL331 Core Data Sheet
• LM397 Data Sheet
• AN-74 – A Quad of Independently Functioning Comparators Application Note
• TI Precision Labs – Op Amps: Comparator Applications (Comparators section)
• Analog Engineers Circuit Cookbook: Amplifiers (Comparators Applications section)
8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2020) to Revision B (August 2021) Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................2
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