Logic Double Patterning at Pitches Below 80 nm

Sokudo Lithography Forum

Semicon West 2009

Tom Wallow
 Logic Pathfinding Complexity Below 80 nm

ƒ Lithography challenges
ƒ too many to mention

ƒ Design challenges
ƒ living with simpler geometries

ƒ Process challenges
ƒ cost-effective double patterning

ƒ Materials challenges
ƒ for resists, size matters as much as wavelength

ƒ Æ Why does all this matter for tracks?

7/15/2009 2
 The Low-k1 Lithographic Resolution Regime

Low k1: 0.5 > k1> k1 <

p λ
= k1
2 NA
NA(max) = 1.35
k1(min) ~ 0.28

Æ p(min) ~ 80 nm

Only 2 diffracted orders Only 1 diffracted order

form image at wafer plane captured
No modulation at wafer
plane

7/15/2009 3
 ITRS Lithography Roadmap 2007

Logic
nodes
32 nm

22 nm
15 nm 80 nm pitch

ƒ Logic pitch is relaxed vs. DRAM, but will transition

below 80 nm for 15 nm node.
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 Patterning and k1 Factor

Process
Improvement
RB OPC

k1 > 0.6

7/15/2009 5
 Patterning and k1 Factor
Including process
Print Image at bestvariation
focus
Process
Improvement
RB OPC

Problems everywhere!

k1 Æ 0.35

7/15/2009 6
 Patterning and k1 Factor

Process
Improvement
RB OPC

It’s not enough MB OPC

OAI

k1 ~ 0.35

7/15/2009 7
 Patterning and k1 Factor

Process
Improvement
RB OPC

MB OPC
OAI

RDR
DFM

k1 = 0.35
7/15/2009 8
 Patterning and k1 Factor

Process
Improvement
RB OPC

MB OPC
OAI

RDR
DFM

k1 ~ 0.3
7/15/2009 9
 Patterning and k1 Factor

Process
Improvement
RB OPC

MB OPC
OAI

RDR
DFM

DDL (DE)
Single
Orientation
Cut Masks
(LELE)

k1 ~ 0.28

7/15/2009 10
 Transition at 80 nm Pitch for Logic

ƒ 80 nm pitch is ultra-low k1 factor

ƒ Unidirectional control only
ƒ Requires double patterning already, but not necessarily pitch-split

ƒ Solutions at 80 nm must address:

ƒ Both 1D at 2D layout
ƒ Both brightfield and darkfield
ƒ (pitch splitting is not fundamentally required for 193i)

ƒ Solutions below 80 nm must address:

ƒ Same issues as >80 nm, but with minimal increased mask count
ƒ (pitch splitting is fundamentally required for 193i)

ƒ Æ Solutions for device and gate will not be same as solutions for
contacts, metals, and vias

7/15/2009 11
 Options Below 80 nm

ƒ Option 1: Pitch split double patterning

ƒ Litho-Etch-Litho-Etch (LELE)
ƒ Spacer patterning (SADP)
ƒ Litho-Freeze-Litho-Etch (LFLE)

ƒ Option 2: EUV
ƒ Option 3: Next generation lithography
ƒ NIL
ƒ DW EB
ƒ New technologies

7/15/2009 12
 Effective k1 Below 0.25: Pitch Splitting

k1 at 2x half-pitch single pattern k1

64 nm HP
k1 ~ 0.45

k1 (@1.35 NA)
45 nm HP
k1 ~ 0.32
44 nm HP
k1 ~ 0.31

double patterning
effective k1
ƒ 32 nm HP k1(effective) ~0.224

ƒ 64 nm HP k1 ~0.45 Half-pitch (nm)

7/15/2009 13
 Double Patterning Options
ƒAdditional dimensions:
ƒDevelopment maturity
Spacer SIT ƒEDA implementation
ƒProjected cost per wafer level
Process Complexity

LELE ƒThroughput
ƒetc.
Ion-beam,
e-beam, Image
plasma... LFLE Reversal

Coating
Dual-tone,
UV, VUV multi-solvent
Vapor Freeze ‘Double Exposure’

Thermal Cure Nonlinear Resists

Dual-develop Memoryless Resists
DDL SIT etc.

Patterning Materials Complexity

ƒ Many process options are under development
7/15/2009 14
 LFLE Processes

Ion-beam,
Dual-tone, Image
Thermal Cure Coating UV, VUV Vapor Freeze e-beam,
multi-solvent Reversal
plasma...

ƒ Many outstanding materials and process innovations

ƒ (Too many examples to include in .pdf version)

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 LFLE Interest

LFLE Publications by year

30
SPIE
25 Photopolymers
ƒ Engagement by:
Other
20 ƒ All resist suppliers
Total
ƒ Major tool suppliers
15 ƒ Consortia
10 ƒ Semi Manufacturer R&D
ƒ EDA vendors
5

0
05

06

07

08

09
20

20

20

20
20

7/15/2009 16
 Steps Toward LFLE Maturity and Production Use

ƒ Clear level targets for LFLE implementation

ƒ FEOL vs. BEOL

ƒ Decomposition-friendly design; mature EDA tools

ƒ Superior process and device performance
ƒ Minimal CDU contributions from additional LFLE process steps
ƒ Competitive defectivity and yield

ƒ Throughput advantages
ƒ Cost advantages

7/15/2009 17
 Where Does LFLE Fit?

ƒ Brightfield: relatively straightforward examples

ƒ Gate level patterning with LFLE vs. incumbent methods

ƒ Darkfield examples:
ƒ contacts
ƒ BEOL- trenches and vias

ƒ Æ Fundamentally different implementations

ƒ ‘Decomposition-friendly’ design

7/15/2009 18
 Examples of Contact/Via Double Patterning

Checkerboard LELE Cross-Grid LFLE

k1(contacts) = *k1(lines)
-Burkhardt and Colburn, JVSTB 2009 (in press) k1 ~ 0.28
-many reports starting 2005

ƒ Decomposition-friendly design is key

ƒ How will these accommodate gate pitch <80nm?

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 LFLE Trench Pitch Splitting
LELE LFLE
Mask 1 Mask 2 Mask 1 Mask 2

No opening!

Resist 2 Resist 2
Hard Mask Frozen Resist 1

First pattern Second pattern LELE decomposition

doesn’t work for LFLE

7/15/2009 20
 LFLE Trench Decomposition

Mask 1 Mask 2

+ =

Resist
Frozen Resist

First pattern Second pattern

7/15/2009 21
 What else may we need from Tracks
for Double Patterning?
ƒ Patterning at 1:3 duty cycle is harder...
ƒ Lines: Is trim etch enough?
ƒ Trenches and contacts: is taper etch enough?
ƒ Ancillaries
ƒ Track based vs. etch based 0.13
0.12
ƒ Cost of ownership
0.11
0.1
0.09 Target CD
0.08
0.07
0.06 Isofocal
0.05
0.04
-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60

ƒ Æ Additional modules, additional reagents, additional process steps

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 Other Resist Performance Limits Below 80 nm

ƒ Fundamental materials properties scaling in ultrathin films

ƒ Materials strength scaling- pattern collapse

ƒ Resist structure homogeneity

ƒ component segregation
ƒ interfacial confinement

ƒ Why discuss this in the context of track processing?

ƒ Resists become ‘stacks’

ƒ Ancillary processing gains in importance

ƒ More process steps, more coats, more reagents

7/15/2009 23
 Pattern Collapse

c) d)

-Cao et al., JVSTB 2000

-Yoshimoto et al. J. Appl. Phys. 2004

ƒ Critical height for collapse (Hc) does not scale with CD for any current model
ƒ Deviation from linear scaling becomes more severe as modulus decreases
7/15/2009 24
 Scaling of Materials Properties

Glassy core;
softened exterior

σ (MD segment size; σ ~1.5 nm)

-Van Workum and de Pablo -Yoshimoto et al.
Phys. Rev. Lett. 2003 J. Chem. Phys. 2005

Independent simulation methods Softened shell grows vs.

predict nonlinear modulus decrease glassy core below 40 nm CD
below 40 nm CD

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 Process Improvement
with Development Modifications
Surfactant Rinse No Surfactant Rinse

72
Pitch (nm)

Baseline Process
LER = 4.3 +/- 0.4 nm

64

Pattern Collapse Suppression

-Sugiyama, M. et. al., Proc. SPIE 2007 Surface Conditioner Process
-Jouve, A. et al., Proc. SPIE 2006 LER = 3.2 +/- 0.4 nm
-Wallow, T. et al, Proc. SPIE 2008
LER Reduction

7/15/2009 26
 Substrate Confinement Effects
-Naulleau, P. et al., JVSTB 2008
-Singh, L. et al., Proc. SPIE 2006
78 nm

3σ LER (nm)
Underlayer A

220 nm Underlayer B

ƒ Reflectivity control is no longer enough

ƒ Interfacial engineering
ƒ Resist/interface matching- resist
becomes a ‘stack’ Defocus (nm)
7/15/2009 27
 Conclusions

ƒ Regardless of which lithographic technologies win

below 80 nm pitch, patterning processes will become
more complex.

ƒ Double patterning: LFLE will require greater track flexibility and

configurability vs. LELE

ƒ Double patterning: any method is likely to require more

complex process flows to compensate for 1:3 duty cycle

ƒ Fundamental scaling: resist structures will be smaller, weaker,

and more sensitive to stack and process. ‘Nice to have’
ancillary track processes are likely to become a necessity

7/15/2009 28
 Acknowledgments

ƒ Yunfei Deng
ƒ Ryoung-han Kim
ƒ Oleg Kritsun
ƒ Jongwook Kye
ƒ Bruno La Fontaine
ƒ Harry Levinson
ƒ Yuansheng Ma
ƒ Uzo Okoroanyanwu
ƒ Kenji Yoshimoto
ƒ Equipment and Materials Suppliers

7/15/2009 29