MOUNT ZION COLLEGE OF

ENGINEERING AND TECHNOLOGY

Lab manual

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

EC8361 - analog AND DIGITAL

LABORATORY

1
 EC8361 - ANALOG AND DIGITAL CIRCUITS LABORATORY

LIST OF ANALOG EXPERIMENTS:

1. Design of Regulated Power supplies.
2. Frequency Response of CE, CB, CC and CS amplifiers
3. Darlington Amplifier
4. Differential Amplifiers - Transfer characteristics, CMRR Measurement
5. Cascode and Cascade amplifiers
6. Determination of bandwidth of single stage and multistage amplifiers
7. Analysis of BJT with Fixed bias and Voltage divider bias using Spice
8. Analysis of FET, MOSFET with fixed bias, self-bias and voltage divider bias using simulation
software like Spice
9. Analysis of Cascode and Cascade amplifiers using Spice
10. Analysis of Frequency Response of BJT and FET using Spice

LIST OFLIST OF DIGITAL EXPERIMENTS

11. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa
(ii) Binary to gray and vice-versa
12. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
13. Design and implementation of Multiplexer and De-multiplexer using logic gates
14. Design and implementation of encoder and decoder using logic gates
15. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
16. Design and implementation of 3-bit synchronous up/down counter
17. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops

TOTAL: 60 PERIODS

2
BC 107 – SYMBOL PIN DIAGRAM

CIRCUIT DAIGRAM OF CE AMPLIFER WITH SELF BIAS:

Without Bypass Capacitor:

With Bypass
Capacitor

3
Exp.No: 1(a)
FREQUENCY RESPONSE OF CE AMPLIFIER
Date :

AIM:
Design and construct BJT Common emitter amplifier using voltage divider bias (Self
bias) with and without bypassed emitter resistor.
 Measurement of gain.
 Plot the frequency response & Determination of Gain Bandwidth Product.
APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Transistor BC 107 1
2. RPS (0-30)V 1
3. Signal generator (0-5)MHz 1
4. CRO (0-30)MHz 1
5. Bread board - 1
6. Resistor
7. Capacitor
8. Single strand wires - -
9. CRO Probes - 3

THEORY:
In communication, amplifiers are the important circuits for boost up weak information
signals. Whenever signal is concern frequency of that signal is also involving. So our designed
amplifier should give better performance in that frequency range. So finding the frequency
response of an amplifier circuit is very important.
Transistor can be used to design amplifier circuit. All the three configurations of
transistor will give amplification but CE configuration will give both voltage and current gain.
Therefore total power gain is increased. Along with CE configuration

4
 DESIGN PROCEDURE:

VCC =15V VBE = 0.7V VCE =5V IC =0.8mA β = 260 R1 = 10KΩ R2 = 1KΩ RL = 1KΩ

i) To find β and IE:

Applying KVL to base loop

IB = Ic/β = 0.8 x 10-3/ 260 = 3.076 x 10-6 = 3.076µA

IE = IB + IC = 3.076 x 10-6 + 0.8 x 10-3 = 0.803mA

ii) To find Emitter Resistance RE:

Apply voltage divider rule across R2

VT or V2 =VCC X R2 / (R1+R2) = 15 X 1K / (10K+1K) = 1.36 Volts

Apply KVL to base loop

VT = VBE + IERE

RE = VT - VBE / IE = (1.36 – 0.7)/0.803 x 10-3 = 821.9 Ω ≈ 1 K Ω

iii)To find Base Resistance RC:

Apply KVL to collector loop

VCC = ICRC + VCE

RC = (VCC – VCE) / IC = (15-5)/0.8 x 10-3 = 12500 Ω = 12.5 KΩ ≈ 12 KΩ

iv) To find input Capacitance C1:

F = 1 /(2πhieC1)

Take F =1 KHz and hie = 1.6 KΩ

C1 = 1 / (2π x 1K x 1.6 K) = 0.099x10-6 = 0.1µF

v) Bandwidth:
BW = fH - fL

5
fixed bias circuit is used to provide stability. By pass capacitors and coupling capacitors are used
to improve the gain of that amplifier circuit.

Whenever there is rise in output current drop across the RE will increase. Due to that in
the input circuit VBB gets decreased and input current also decreased. By the relation Ic = β Ib
output current Ic also decreased. Therefore always there is a control on output current. Better
stability will be provided and the operating point is very stable.

Coupling capacitors are used to block DC signals and allow only AC signals. Therefore biasing
setup & operating point is not changed. By pass capacitor is giving low resistance path to AC
signals, so that there is no voltage drop across RE resistor due to AC signals.

MODEL GRAPH:

6
 Tabulation:
Input Signal Output Signal
S.No Condition
Amplitude Frequency Amplitude Frequency
Without Bypassed
1 Emitter Resistor

With Bypassed
2 Emitter

Tabulation for Frequency Response:

Vin : ……..Volts
Frequency Gain =20 Log(VO/Vin ) in
S.NO VO in Volts Gain =(VO/Vin )
in Hz db

7
PROCEDURE:
 Circuit connections are given as per the diagram.
 Selection of capacitors and resistors are as per the design.
 Verify the operating point.
 Give the AC input voltage to the circuit Vin =……..Volts. Keeping input voltage constant and
note the output at CRO.
 Change the frequency of the input signal from (0-5) MHz, and note the corresponding output
voltages.
 Calculate the gain using Av=20log{Vo/Vin}dB
 Then the frequency responses of common emitter amplifier can be plotted by taking frequency
along X axis & Gain in dB along Y axis.

TO PLOT THE FREQUENCY RESPONSE

 The frequency response curve is plotted on a semi-log scale.
 The mid frequency voltage gain is divided by√2 and these points are marked in the frequency
response curve.
 The high frequency point is called the upper 3dB point.
 The lower frequency point is called the lower 3dB point.
 The difference between the upper 3dB point and the lower 3dB point in the frequency scale gives
the bandwidth of the amplifier.
 From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH - fL

RESULT:
Thus the amplifier circuit is designed and its frequency response is calculate and
plotted in the graph.
Operating Point(VCE,IC ) =
Voltage Gain (AV) =
Highest frequency =
Lowest frequency =
Band Width =
Gain Bandwidth Product =

8
BC 107 – SYMBOL PIN DIAGRAM

CIRCUIT DAIGRAM OF CC AMPLIFER WITH SELF BIAS:

MODEL GRAPH:

9
Exp.No: 1(b)
FREQUENCY RESPONSE OF CC AMPLIFIER
Date :

AIM:
Design and construct BJT Common Collector amplifier using voltage divider bias (Self
bias) with and without bypassed emitter resistor
 Measurement of gain.
 Plot the frequency response & Determination of Gain Bandwidth Product.
APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Transistor BC 107 1
2. RPS (0-30)V 1
3. Signal generator (0-5)MHz 1
4. CRO (0-30)MHz 1
5. Bread board - 1
6. Resistor
7. Capacitor
8. Single strand wires - -
9. CRO Probes - 3

THEORY:
The common-collector (CC) amplifier, or the emitter-follower as it is sometimes called,
is a unity voltage gain, high current gain amplifier. The input resistance for this type of amp is
usually 1KΩ to 100KΩ. Because the amplifier has a voltage gain of one, it is useful as a buffer
amplifier, providing isolation between two circuits while providing driving capability for low
resistance loads.
The dc biasing is provided by R1, R2 and Re. The load resistance is capacitor coupled to
the emitter terminal of the transistor. When a signal is applied via to the base of the transistor, Vb
is increased and decreased as the signal goes positive and

10
 DESIGN PROCEDURE:

VCC =15V VBE = 0.7V VCE =5V IC =0.8mA β = 260 R1 = 10KΩ R2 = 1KΩ RL = 1KΩ

i) To find β and IE:

Applying KVL to base loop

IB = Ic/β = 0.8 x 10-3/ 260 = 3.076 x 10-6 = 3.076µA
IE = IB + IC = 3.076 x 10-6 + 0.8 x 10-3 = 0.803mA
ii) To find Emitter Resistance RE:

Apply voltage divider rule across R2

VT or V2 =VCC X R2 / (R1+R2) = 15 X 1K / (10K+1K) = 1.36 Volts
Apply KVL to base loop
VT = IBRB +VBE + IERE
RE = (VT - VBE - IBRB) / IE = (1.36 – 0.7-3.076 x 10-6x1K)/0.803 x 10-3
= 826.4 Ω ≈ 1 K Ω
iii)To find Base Resistance RC:

Apply KVL to collector loop

VCC = ICRC + VCE + IERE
RC = (VCC – VCE - IERE ) / IC = (15-5-0.803 x 10-3 x 103 )/0.8 x 10-3
= 11496Ω ≈ 12 KΩ
iv) To find input Capacitance C1:

F = 1 /(2πhieC1)
Take F =1 KHz and hie = 1.6 KΩ
C1 = 1 / (2π x 1K x 1.6 K) = 0.099x10-6 = 0.1µF

iv) Bandwidth:
BW = fH - fL

11
negative, respectively. Ve = Vb – Vbe. Considering Vbe fairly constant, we say that variation in
the Vb appears at emitter and emitter voltage Ve will vary same as base voltage Vb. Since the
emitter is output terminal, it can be noted that the output voltage from a common collector circuit
is the same as its input voltage. In other words, we can say that in common collector circuit
emitter terminal follows the signal voltage applied to the base. Hence the common collector
circuit is also known as an emitter follower.

PROCEDURE:
 Circuit connections are given as per the diagram.
 Selection of capacitors and resistors are as per the design.
 Verify the operating point.
 Give the AC input voltage to the circuit Vin =……..Volts. Keeping input voltage constant and
note the output at CRO.
 Change the frequency of the input signal from (0-5) MHz, and note the corresponding output
voltages.
 Calculate the gain using Av=20log{Vo/Vin}dB
 Then the frequency responses of common emitter amplifier can be plotted by taking frequency
along X axis & Gain in dB along Y axis.

TO PLOT THE FREQUENCY RESPONSE

 The frequency response curve is plotted on a semi-log scale.
 The mid frequency voltage gain is divided by√2 and these points are marked in the frequency
response curve.
 The high frequency point is called the upper 3dB point.
 The lower frequency point is called the lower 3dB point.
 The difference between the upper 3dB point and the lower 3dB point in the frequency scale gives
the bandwidth of the amplifier.
 From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH - fL

12
 Tabulation for Frequency Response:
Vin : ……..Volts
Frequency Gain =20 Log(VO/Vin ) in
S.NO VO in Volts Gain =(VO/Vin )
in Hz db

13
RESULT:
Thus the amplifier circuit is designed and its frequency response is calculate and
plotted in the graph.
Operating Point(VCE,IC ) =
Voltage Gain (AV) =
Highest frequency =
Lowest frequency =
Band Width =
Gain Bandwidth Product =

14
CIRCUIT DIAGRAM

MODEL GRAPH

15
Exp.No:1(c)
FREQUENCY RESPONSE OF CB AMPLIFIER
Date :

AIM:
Design and construct BJT Common Collector amplifier using voltage divider bias (Self
bias) with and without bypassed emitter resistor
 Measurement of gain.
 Plot the frequency response & Determination of Gain Bandwidth Product.
APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Transistor BC 107 1
2. RPS (0-30)V 1
3. Signal generator (0-5)MHz 1
4. CRO (0-30)MHz 1
5. Bread board - 1
6. Resistor
7. Capacitor 68KΩ,47KΩ,4.7KΩ,2.2KΩ,50KΩ,10KΩ, Each 1
8. Single strand wires - -
9. CRO Probes - 3

THEORY:

A common base amplifier is type of BJT amplifier which increases the voltage level of
the
applied input signal Vin at output of collector. The Common base amplifier typically has good
voltage gain and relatively high output impedance. But the Common base amplifier unlike CE
amplifier has very low input impedance which makes it unsuitable for most voltage amplifier. It
is typically used used as an active load for a cascode amplifier and also as a current follower
circuit.

16
DESIGN PROCEDURE:

Given Transistor specifications:

hie = 2.1kΩ ; hfe = 75 ; hfb =0.987

i) To find Device input impedance :

hib = ( hie / (1+ hfe))

hib = ____

ii) To find Circuit input impedance (Zi) :

Zi = hib || Re ,Where Re= 2.2 kΩ

Zi = _____

iii) To find Circuit output impedance (Zo) :

Zo = Rc ; where Rc = 4.7 kΩ

iv) To find Voltage Gain (Av) :

Av = [ hfb (Rc || RL) / hib ]

Where RL= 10kΩ

Av = _____

17
Circuit Operation:

A positive-going signal voltage at the input of a CB pushes the transistor emitter in a

positive direction while the base voltage remains fixed, hence Vbe reduces. The reduction in
VBE results in reduction in VRC, consequently VCE increases. The rise in collector voltage
effectively rises the output voltage. The positive going pulse at the input produces a positive-
going output, hence the there is no phase shift from input to output in CB circuit. In the same
way the negative-going input produces a negative-going output.
PROCEDURE:
 Circuit connections are given as per the diagram.
 Selection of capacitors and resistors are as per the design.
 Verify the operating point.
 Give the AC input voltage to the circuit Vin =……..Volts. Keeping input voltage
constant and note the output at CRO.
 Change the frequency of the input signal from (0-5) MHz, and note the corresponding
output voltages.
 Calculate the gain using Av=20log{Vo/Vin}dB
 Then the frequency responses of common emitter amplifier can be plotted by taking
frequency along X axis & Gain in dB along Y axis.

TO PLOT THE FREQUENCY RESPONSE

 The frequency response curve is plotted on a semi-log scale.
 The mid frequency voltage gain is divided by√2 and these points are marked in the
frequency response curve.
 The high frequency point is called the upper 3dB point.
 The lower frequency point is called the lower 3dB point.
 The difference between the upper 3dB point and the lower 3dB point in the frequency
scale gives the bandwidth of the amplifier.
 From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH - fL

18
 Tabulation for Frequency Response:
Vin : ……..Volts
Frequency Gain =20 Log(VO/Vin )
S.NO VO in Volts Gain =(VO/Vin )
in Hz in db

19
RESULT:
Thus the amplifier circuit is designed and its frequency response is calculate and
plotted in the graph.

Operating Point(VCE,IC ) =
Voltage Gain (AV) =
Highest frequency =
Lowest frequency =
Band Width =
Gain Bandwidth Product =

20
BFW10-SYMBOL PIN DIAGRAM

CIRCUIT DIAGRAM OF SOURCE FOLLOWER:

MODEL GRAPH

21
Exp.No: 2
FREQUENCY RESPONSE OF CS AMPLIFIER
Date :

AIM:
To Construct a Source Follower with Bootstrapped Gate resistance amplifier circuit using
FET and calculate its gain.

APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Signal generator (0-30)V 1
2. Capacitor 0.01uF 2
3. FET BFW10 1
4. DC Ammeter (0-10)mA 1
5. DC Voltmeter (0-10)V 1
6. Bread board - 1
1 M ohm,
7. Resistor 1
2.2 K ohm
8. CRO (0-30)MHz 1

THEORY:
The JFET equivalent of the BJT emitter follower configuration is the source follower or
common drain configuration. Output is taken from the source terminal and is the AC equivalent
circuit the drain appears to be grounded, therefore, the name common drain configuration. Self
biasing circuit is employed for the CD amplifier. The input signal is applied at the gate of the CD
amplifier. In the AC equivalent circuit, the drain (which is connected to Vcc) gets connected to
ground. So it becomes a common point between the input and output and this configuration is
called common drain configuration. From the input and output wave forms, we can observe that
output voltage is equal to the input voltage and the phase difference between them is zero. As the
source voltage follows the input voltage. This circuit is called as source follower.

22
TABULATION

Vin(V) VO(V) Time Period (mS) Gain = (VO/Vin )

Tabulation for Frequency Response:

Vin : ……..Volts
Frequency in VS IS RG RO = VS / IS Gain =
S.NO
Hz (V) (mA) (Ω) (Ω) (VO/Vin )

Calculation :
Calculation of gmo = 1 / Ro =

23
PROCEDURE:
 Circuit connections are given as per the diagram.
 Selection of capacitors and resistors are as per the design.
 Give the AC input voltage to the circuit Vin =……..Volts. Keeping input voltage constant
and note the output at CRO.
 At a given frequency, the corresponding input and output voltages are measured.
 The source current and source voltages are noted from corresponding meters.
 The above procedure is repeated by connecting boot strapped resistance.

TO PLOT THE FREQUENCY RESPONSE

 The frequency response curve is plotted on a semi-log scale.
 The mid frequency voltage gain is divided by√2 and these points are marked in the
frequency response curve.
 The high frequency point is called the upper 3dB point.
 The lower frequency point is called the lower 3dB point.
 The difference between the upper 3dB point and the lower 3dB point in the frequency
scale gives the bandwidth of the amplifier.
 From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH - fL

RESULT:
Thus the source follower using boot strapped gate resistance circuit was verified.

24
BC 107 – SYMBOL PIN DIAGRAM

CIRCUIT DAIGRAM OF DARLINGTON AMPLIFIER:

25
Exp.No: 03
DARLINGTON AMPLIFIER USING BJT
Date :

AIM:
Construct a Darlington amplifier circuit using BJT
 Measurement of gain
 Plot the frequency response & Determination of Gain Bandwidth Product.
APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Transistor BC 107 2
2. RPS (0-30)V 1
3. Signal generator (0-5)MHz 1
4. CRO (0-30)MHz 1
5. Bread board - 1
6. Resistor
7. Capacitor
8. Single strand wires - -
9. CRO Probes - 3

THEORY:

The Darlington transistor (often called a Darlington pair) is a semiconductor

device which combines two bipolar transistors in a single device so that the current amplified by
the first is amplified further by the second. This configuration gives a high current gain (written
β, hfe, or hFE) and unity voltage gain and can take less space than two separate transistors
because the two transistors can use a shared collector. A Darlington pair behaves like a single
transistor with a high current gain (the product of the gains of the two transistors):

βDarlington = β1 * β2 .

Bandwidth BW = fH - fL

26
MODEL GRAPH:

27
 A typical modern device has a current gain of 1000 or more, so that only a tiny base
current is needed to make the pair switch on. Integrated devices have three leads (B, C and E),
broadly equivalent to those of a standard transistor. The base-emitter voltage is also higher. It is
the sum of both base-emitter voltages:

VBE = VBE1 + VBE2

Thus, for Si based technology, there must be about 0.7 V across both base-emitter
junctions (connected in series in the device), so that we need about 1.4 V in total to turn on the
device. The saturation voltage of a Darlington pair is about 0.7 V, which can cause substantial
power dissipation. Another drawback is a reduction in switching speed, because the first
transistor cannot actively inhibit the base current of the second, which makes the device slow to
switch off. To alleviate this, the second transistor often has a base resistor of a few hundred
ohms. The Darlington has more phase shift at high frequencies than a single transistor and hence
can more easily become unstable with negative feedback (i.e., systems that use this configuration
can have poor phase margin due to the extra transistor delay).

PROCEDURE:
 Circuit connections are given as per the diagram.
 Selection of capacitors and resistors are as per the design.
 Verify the operating point.
 Give the AC input voltage to the circuit Vin =……..Volts. Keeping input voltage
constant and note the output at CRO.
 Change the frequency of the input signal from (0-5) MHz, and note the corresponding
output voltages.
 Calculate the gain using Av=20log{Vo/Vin}dB
 Then the frequency responses of common emitter amplifier can be plotted by taking
frequency along X axis & Gain in dB along Y axis.

28
 Tabulation for Frequency Response:
Vin : ……..Volts
Frequency in
S.NO VO in Volts Gain = VO / Vin Gain =20 Log(VO/Vin ) in db
Hz

29
TO PLOT THE FREQUENCY RESPONSE
 The frequency response curve is plotted on a semi-log scale.
 The mid frequency voltage gain is divided by√2 and these points are marked in the
frequency response curve.
 The high frequency point is called the upper 3dB point.
 The lower frequency point is called the lower 3dB point.
 The difference between the upper 3dB point and the lower 3dB point in the frequency
scale gives the bandwidth of the amplifier.
 From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH - fL

RESULT:
Thus the Darlington current amplifier was constructed and the frequency response
curve is plotted.
Gain =
Highest frequency =
Lowest frequency =
Bandwidth =
Gain Bandwidth product =

30
BC547 – SYMBOL PIN DIAGRAM

CIRCUIT DAIGRAM : Common Mode operation:

Differential Mode operation:

31
Exp.No: 04
DIFFERENTIAL AMPLIFIER USING BJT
Date :

AIM:
To construct a differential amplifier circuit using BJT
 Measure its Common Mode Rejection Ratio (CMRR).
APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

(0-30)V, 2
1. Regulated power supply
(0-12)V 1
2. Transistor BC 547 2
3. Multi meter 1
4. Resistor 1KOhm 3
5. Cathode ray oscilloscope 20MHz 1
6. Bread board 1

THEORY:
 The differential amplifier amplifies the difference between two input voltage signals.
 The output voltage is proportional to the difference between the two input signals. VO = a
(V1-V2)
 The differential amplifier is a versatile circuit which serves as the input stage to most op
amps and used as comparator and emitter biased circuits which are identical in
characteristics.
 There are two modes of operation namely, differential and common mode operation.
 Differential mode operation – The two input signals are different from each other.
Signals have same magnitude but 180 degree out of phase. Hence the difference output VO
is twice as large as the signal voltage from either collector to ground.
 Common mode operation – signals at the base are derived from the same source.
Signals are equal in magnitude as well as in phase. Difference output VO is almost zero,
negligibly small. Ideally it should be zero.

32
 TABULATION

VD = (Vi- V2) VC = (V1+V2)/2 AD= VO/VD AC= VO/VC CMRR =

S.No V1 (Volts) V2 (Volts) V0 (Volts)
(Volts) (Volts) AD/AC

33
Mean:
  CMRR – when the same voltage is applied to both the inputs, the differential amplifier is
said to operate in a common mode configuration.
 Many disturbance signals appear as a common input signal to both the input terminals of
the differential amplifier.
 The ability of a differential amplifier to reject a common mode signal is expressed by a
ratio called Common Mode Rejection Ratio denoted as CMRR.
 It is defined as the ration of the differential voltage gain Ad to common mode voltage gain
Ac.
CMRR = AD/AC
Ad = differential gain of amplifier. Ac = common mode gain of amplifier.
AD= VO/VD
VO= measured output voltage in volts
VD = difference in input voltage in differential mode
AC= VO/VC
i. Common Mode
Output voltage VO = (VO1+VO2)/2
Input voltage VC = (Vi1+Vi2)/2
ii. Difference Mode
Output voltage VO = (VO1+VO2)/2
Input voltage VD = (Vi1- Vi2)
PROCEDURE:
 Connections are given as per the circuit diagram.
 To determine the common mode gain, we set input signal with voltage Vin=2V and
determine V0 at the collector terminals.
 Calculate common mode gain, Ac=Vo/Vin.
 To determine the differential mode gain, we set input signals with voltages V1 and V2.
Compute Vin=V1-V2 and find V0 at the collector terminals. Calculate differential mode gain
Ad =Vo/Vin·
 Calculate the CMRR=Ad/Ac.
 Measure the de collector current for the individual transistors. A graph is plotted between
frequency and gain

34
Tabulation

Input Signal Output Signal

S.No Condition
Gain = Vo / Vin
Amplitude Frequency Amplitude Frequency
(Volts) (Hz) (Volts) (Hz)

Common
1
Mode

Differential
2
Mode

35
RESULT:
Thus the differential amplifier was constructed and the CMRR was determined.

CMRR=

36
BC 107 – SYMBOL PIN DIAGRAM

CASCODE AMPLIFIER:
18 V

6.8kΩ 1.8kΩ

5µF

10µF
BC107BP
5.6kΩ CRO
f2

5µF
BC107BP
Vi
4.7kΩ
1.1kΩ 20µF

37
Exp.No: 05 (a)
CASCODE AMPLIFIER USING BJT
Date :

AIM:
To construct and design a cascode amplifier circuit using BJT
 Measure its frequency response characteristics.

APPARATUS REQUIRED:

S.No. Name Range Quantity

1. Transistor BC107 2
6.8kΩ,1.8kΩ,4.7kΩ,5.6kΩ,
2. Resistor 1,1,1,1,2,1
1.1 kΩ,25 kΩ
3. Regulated power supply (0-30)V 1
4. Signal Generator (0-3)MHz 1
5. CRO 30 MHz 1
6. Bread Board 1
7. Capacitor 20µF,10 µF,5 µF 1

THEORY:
 A cascode amplifier consists of a common emitter amplifier stage in series
with a common base amplifier stage.
 Transistor Q1 and its associated components operate as a common emitter
amplifier, while the circuit of Q2 functions as a common base output stage.
 The cascade amplifier gives the high input impedance of a common emitter
amplifier, as well as the good voltage gain and frequency performance of a
common base circuit.

PROCEDURE:

 Connections are made as per the circuit diagram.

 The waveforms at the input and output are observed for cascode operations by
varying the input frequency.
 The biasing resistances needed to locate the Q-point are determined.
 Set the input voltage as 1V and by varying the frequency, note the output voltage.
 Calculate gain=20 log (Vo / Vin.)

38
  A graph is plotted between frequency and gain.

MODEL GRAPH

f1 f2 f (Hz)

TABULATION:

FREQUENCY RESPONSE OF CASCODE AMPLIFIER

Keep the input voltage constant (Vin) =

Frequency (in Output Voltage (in Gain = 20 log (Vo / Vin) (in
Hz) volts) dB)

39
RESULT:
Thus the Cascode amplifier was constructed and the gain was determined.

40
BC 107 – SYMBOL PIN DIAGRAM

41
Exp.No: 05(b)
CASCADE AMPLIFIER USING BJT
Date :

AIM:
To construct a cascade amplifier circuit using BJT
 Measure its frequency response characteristics.

APPARATUS REQUIRED:

S.No. Name Range Quantity

1. Transistor BC107 1
22kΩ,6 kΩ,700 Ω,470Ω
16 kΩ,6.2 kΩ,3.3 kΩ 1,1,1,1,
2. Resistor 1.1 kΩ 1,1,1,
1
1.2 kΩ
3. Regulated power supply (0-30)V 1
4. Signal Generator (0-3)MHz 1
5. CRO 30 MHz 1
6. Bread Board 1
7. Capacitor 0.01µF 5

THEORY:

 A cascade amplifier has many of the same benefits as a cascode.

 A cascade is basically a differential amplifier with one input grounded and the

side with the real input has no load.

 It can also be seen as a common collector (emitter follower) followed by a

common base.

 By cascading a CE stage followed by an emitter-follower (CC) stage, a good

voltage amplifier results. The CE input resistance is high and CC output

resistance is low.

42
 MODEL GRAPH

f1 f2 f (Hz)

TABULATION:

FREQUENCY RESPONSE OF CASCODE AMPLIFIER

Keep the input voltage constant (Vin) =

Frequency (in Output Voltage (in Gain = 20 log (Vo / Vin) (in
Hz) volts) dB)

43
PROCEDURE:
 Connections are made as per the circuit diagram.
 The waveforms at the input and output are observed for cascade operations by
varying the input frequency.
 The biasing resistances needed to locate the Q-point are determined.
 Set the input voltage as 1V and by varying the frequency, note the output voltage.
 Calculate gain=20 log (Vo / Vin.)
 A graph is plotted between frequency and gain.
 The CC contributes no increase in voltage gain but provides a near voltage-source
(low resistance) output so that the gain is nearly independent of load resistance.
 The high input resistance of the CE stage makes the input voltage nearly
independent of input-source resistance.
 Multiple CE stages can be cascaded and CC stages inserted between them to
reduce attenuation due to inter-stage loading.

RESULT:
Thus the Cascade amplifier was constructed and the gain was determined.

44
SL100 – SYMBOL PIN DIAGRAM

CIRCUIT DAIGRAM

45
Exp.No: 6(a)
CLASS A POWER AMPLIFIER
Date :

AIM:
To construct a Class A Power Amplifier
 Observation of Input and output waveform.
 Measurement of maximum power output.
 Determination of efficiency.
APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Transistor SL100 1
2. RPS (0-30)V 1
3. Signal generator (0-30)MHz 1
4. CRO - 1
5. Bread Board
6. Resistor
7. Capacitor
8. Single strand wires - -
9. CRO Probes - 3

THEORY:
The power amplifier is said to be class A amplifier if the Q point and the input signal are
selected such that the output signal is obtained for a full input cycle.
For all the values of input signal, the transistor remains in the active region and never
enters into cut-off or saturation region. When an a.c. input signal is applied, the collector voltage
varies sinusoid ally hence the collector current also varies sinusoid ally. The collector current
flow for 360 degree (full cycle) of the input signal. In other words, the angle of the collector
current flow is 360 degree i.e. one full cycle. For full input cycle, a full output cycle is obtained.
Here signal is faithfully reproduced, at the output, without any distortion. This is an important
feature of a class A operation. The efficiency of class A operation is very small.

46
 In a Class A circuit, the amplifying element is biased so the device is always conducting
to some extent, and is operated over the most linear portion of its characteristic curve. Because
the device is always conducting, even if there is no input at all, power is drawn from the power
supply. This is the chief reason for its inefficiency.

If high output powers are needed from a Class A circuit, the power waste (and the
accompanying heat) will become significant. For every watt delivered to the load, the amplifier
itself will, at best, dissipate another watt. For large powers this means very large and expensive
power supplies and heat sinking. Class A designs have largely been superseded for audio
amplifier, though some audiophiles believe that Class A gives the best sound quality, due to it
being operated in as linear a manner as possible which provides a small market for expensive
high fidelity Class A amps. Many recording studios use equipment such as preamplifier that are
considered Class A designs.

TABULATION:

Input Waveform (VIN) Output Waveform (VO)

Amplitude(V) Time Period (ms) Amplitude(V) Time Period (ms)

47
MODEL GRAPH FOR CLASS A AMPLIFIER:

CALCULATION:
For maximum power output,
In d.c power output PDC = VCCIC
In a.c power output PAC = (VM) 2 /2RL
= (VCC) 2 /2RL

PROCEDURE:
 Connect the circuit diagram as per the circuit diagram.
 Set VI= 50mV, using the signal generator.
 Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular
steps and note down the corresponding output voltage.
 Plot the graph : Gain (dB) Vs frequency (Hz)
 Find the input and output impedance.
 Calculate the bandwidth from the graph.
 Note down the phase angle, bandwidth, input and output impedance.
 Calculate the efficiency = (PO/Pin).

48
RESULT:
Thus the class A amplifier is designed and frequency response of the amplifier is drawn.

Maximum power output =

Efficiency =

49
 SL100 – SYMBOL SK100-SYMBOL PIN DIAGRAM

CIRCUIT DAIGRAM FOR CLASS B AMPLIFIER

MODEL GRAPH FOR CLASS B AMPLIFIER WITH CROSSOVER DISTORTION:

50
Exp.No: 6(b)
CLASS B COMPLEMENTARY SYMMETRY POWER AMPLIFIER
Date :

AIM:
To construct a Class B Complementary symmetry power amplifier
 Observation of the output waveform with crossover Distortion.
 Modification of the circuit to avoid crossover distortion.
 Measurement of maximum power output.
 Determination of efficiency.
APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Transistor SK100,SL100 1
2. RPS (0-30)V 1
3. Signal generator (0-30)MHz 1
4. CRO - 1
5. Bread Board
6. Resistor
7. Capacitor
8. Single strand wires - -
9. CRO Probes - 3

THEORY:
CLASS B PUSH PULL POWER AMPLIFIER OUTPUT STAGE:
The two transistors are configured as emitter follower amplifiers therefore the maximum
voltage gain Av is 1. The push pull output stage of the class B amplifier has a quiescent bias
current of zero. When the input signal is zero then no current will flow in the output transistors.
We use a NPN and PNP transistor such that the NPN will conduct on the positive half cycle of
the input signal and PNP will conduct on the negative half cycle. Output transistors will not
begin to conduct until input signal reaches a level to eliminate cross over distortion:

51
CIRCUIT DAIGRAM FOR CLASS B AMPLIFIER TO OVERCOME DISTORTION

52
Operating point for NPN transistor is at near to cutoff point therefore only positive half can be
amplified and for negative half cycle it remains in off condition. Operating point for PNP
transistor is at near to Saturation point therefore only negative half can be amplified and for
positive half cycle it remains in off condition.

PROCEDURE:
 Connect the circuit diagram as per the circuit diagram.
 Set VI= 50mV, using the signal generator.
 Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular
steps and note down the corresponding output voltage.
 Plot the graph : Gain (dB) VS frequency (Hz)
 Find the input and output impedance.
 Calculate the bandwidth from the graph.
 Note down the phase angle, bandwidth, input and output impedance.
 Calculate the efficiency = (PO/PIN).

53
 TABULATION:

Input Waveform (Vin) Output Waveform (VO)

Condition Time Period (ms)

Time Period
Amplitude(V) Amplitude(V)
(ms)
TON TOFF

With Cross over

distortion
Overcome Cross
over distortion

Calculation:
For maximum power output,
In d.c power output PDC = (2VCCIM)/П (IM=VCC/RL)
In a.c power output PAC = (VM IM)/2
= (VM) 2 /2RL

54
RESULT:

Thus the class B amplifier is designed, cross over distortion is verified and frequency
response of the amplifier is drawn.
Maximum power output =
Efficiency =

55
CIRCUIT DIAGRAM

OUTPUT WAVEFORM

56
Exp.No:7(a)
SPICE SIMULATION OF COMMON SOURCE AMPLIFIER
Date :

AIM:
To verify the characteristics of CS Amplifier Using Pspice

SOFTWARE USED:

Orcad Pspice Software

Theory:
The CS amplifier is a small signal amplifier. For good bias stability, the source
resistor voltage drop should be as large as possible. Where the supply voltage is small, Vs
may be reduced to a minimum to allow for the minimum level of Vds.R2 is usually selected
as 1MΏor less as for BJT capacitor coupled circuit, coupling and bypass capacitors should
be selected to have the smallest possible capacitance values. The largest capacitor in the
circuit sets the circuit low 3dB frequency (capacitor C2). Generally to have high input
impedance FET is used. As in BJT circuit RL is usually much larger than Zo and Zi is often
much larger than Rs.

PROCEDURE:
1. Construct circuit in Pspice and store the file.
2. Create new simulation profile.
3. Simulate the circuit
4. Note the output voltage of the waveform.
5. Verify the input and output waveform

57
RESULT:
Thus the characteristic of CS Amplifier was simulated and verified.

CIRCUIT DIAGRAM:

OUTPUT WAVEFORM

58
Exp.No: 7(b)
SPICE SIMULATION OF COMMON EMITTER AMPLIFIER
Date :

AIM:
To verify the characteristics of CE Amplifier Using Pspice

SOFWARE USED:

Orcad Pspice Software

THEORY:

This type of biasing is otherwise called Emitter Biasing. The necessary biasing is
provided using 3 resistors: R1, R2 and Re. The resistors R1 and R2 act as a potential divider and
give a fixed voltage to the base. If the collector current increases due to change in temperature or
change in β, the emitter current Ie also increases and the voltage drop across Re increases,
reducing the voltage difference between the base and the emitter. Due to reduction in V be, base
current Ib and hence collector current Ic also reduces. This reduction in Vbe, base current Ib and
hence collector current Ic also reduces. This reduction in the collector current compensates for
the original change in Ic.
The stability factor S= (1+β) * ((1/ (1+β)). To have better stability, we must keep R b/Re
as small as possible. Hence the value of R1 R2 must be small. If the ratio R b/Re is kept fixed, S
increases with β.

PROCEDURE:
6. Construct circuit in Pspice and store the file.
7. Create new simulation profile.
8. Simulate the circuit
9. Note the output voltage of the waveform.
10. Verify the input and output waveform

RESULT:
Thus the characteristic of CS Amplifier was simulated and verified.

59
Exp.No:
DESIGN OF REGULATED POWER SUPPLIES
Date :

Aim:
Design of Regulated Power supply for fixed voltage using IC 7805 & 7812

APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Diode IN4007 2
2. Step down transformer 12V-0-12V 1
3. 7805,7812 - 1
4. CRO (0-30)MHz 1
5. Bread Board -
6. Resistor 1KΩ 1
7. Capacitor 100µf 1
8. Single strand wires - -
9. CRO Probes - 1

Theory: Write Specifications & applications of IC 7805.

Transformer :
Selecting a suitable transformer is of great importance. The current rating and the
secondary voltage of the transformer is a crucial factor.
 The current rating of the transformer depends upon the current required for the load to be
driven.
 The input voltage to the 7805 IC should be at least 2V greater than the required output,
therefore it requires an input voltage at least close to 7V.
 So chose a 6-0-6 transformer with current rating 500mA (Since 6*√2 = 8.4V).

60
IC7805 PIN DIAGRAM:

CIRCUIT DIAGRAM:

MODEL GRAPH:

61
PROCEDURE:
Without filter:
 Connecting the circuit on bread board as per the circuit diagram.
 Connect the primary of the transformer to main supply i.e. 230V, 50Hz.
 Note down the peak value VM of the signal observed on the CRO.
 Switch the CRO into DC mode and observe the waveform.
 Connect load resistance at 1K and connect Channel – II of CRO at output terminals
and CH – I of CRO at Secondary Input terminals observe and note down the Input
and Output Wave form on Graph Sheet.
With filter:
1. Connecting the circuit as per the circuit Diagram and repeat the above procedure.

TABULATION:

Signals Amplitude Time period (sec) IC7805

(volt)
Output Voltage

Input signal

Output signal

Without filter

With filter

RESULT:
Thus the AC signal is rectified in full wave rectifier with and without capacitor filter and
the input and output signals are plotted in graph.

62
Exp.No:
DESIGN OF VARIABLE REGULATED POWER SUPPLIES
Date :

Aim:
Design of Regulated Power supply for fixed voltage using IC 7805 & 7812

APPARATUS REQUIRED:

S.NO. ITEM RANGE QUANTITY

1. Diode IN4007 2
2. Step down transformer 12V-0-12V 1
3. LM317 - 1
4. CRO (0-30)MHz 1
5. Bread Board -
6. Resistor 1KΩ 1
7. Capacitor 100µf 1
8. Single strand wires - -
9. CRO Probes - 1

Theory: Write Specifications & applications of IC 7805.

Transformer :
Selecting a suitable transformer is of great importance. The current rating and the
secondary voltage of the transformer is a crucial factor.
 The current rating of the transformer depends upon the current required for the load to be
driven.
 The input voltage to the LM317 IC should be at least 2V greater than the required output,
therefore it requires an input voltage at least close to 7V.
 So chose a 6-0-6 transformer with current rating 500mA (Since 6*√2 = 8.4V).

63
CIRCUIT DIAGRAM:

64
PROCEDURE:
 Connecting the circuit on bread board as per the circuit diagram.
 Connect the primary of the transformer to main supply i.e. 230V, 50Hz.
 Note down the peak value VM of the signal observed on the CRO.
 Switch the CRO into DC mode and observe the waveform.
 Connect load resistance at 1K and connect Channel – II of CRO at output terminals
and CH – I of CRO at Secondary Input terminals observe and note down the Input
and Output Wave form on Graph Sheet.
2. Connecting the circuit as per the circuit Diagram and repeat the above procedure.

TABULATION:

Signals
Amplitude Time period LM317
Resistor value
(volt) (sec) Output Voltage

Input signal

Output signal

Without filter

With filter

RESULT:
Thus the AC signal is rectified in full wave rectifier with and without capacitor filter and
the input and output signals are plotted in graph.

65
 EC8361
ANALOG AND
DIGITAL CIRCUITS
LABORATORY

1
 LIST OF EXPERIMENTS

EXPT.NO NAME OF THE EXPERIMENT PAGE.NO

1 Design and implementation of code converters using logic gates. 27
Design and implementation of 4-bit binary adder/subtractor and BCD adder
2 49
using IC 7483.
Design and implementation of multiplexer and demultiplexer using logic
3 58
gates
4 Design and implementation of encoder and decoder using logic gates 64
Construction and verification of 4-bit ripple counter and Mod-10/Mod-12
5 67
ripple counter.
6 Design and implementation of 3-bit synchronous up/down counter. 71
Appendix 1 – Exercise 89
Appendix 2 – Viva voice questions 92
Appendix 3 – Cross section view of bread board 94

2
 1. DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR Gate IC 7486 1
2. AND Gate IC 7408 1
3. OR Gate IC 7432 1
4. NOT Gate IC 7404 1
5. IC Trainer Kit - 1
6. Patch Cords - 35

THEORY:
Code Converter:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for
same information. Thus, the code converter is a circuit that changes data presented
in one type of binary code to another type of binary code.
Gray Code:
The Gray code is an unweighted and is not an arithmetic code: that is, there are
no specific weights assigned to the bit positions. The important feature of the Gray
Code is that it exhibits a single bit change from one code word to the next in sequence.
This property is important in many applications, such as shaft position encoders, where
error susceptibility increases with the number of bit changes between adjacent numbers
in a sequence.
The Gray code is an useful code used in digital systems. It is used primarily for
indicating the angular position of a shaft on rotating machinery such as automated
lathes and drill presses. This code is like binary in that it can have as many bits as

3
necessary and the more bits, the more possible combinations of output codes ( number
of combinations = 2 N) are also available.
Excess -3 Code:

Excess-3 binary-coded decimal or Stibitz code, also called biased representation

or Excess-N, is a complementary BCD code and numeral system. It was used on some
older computers with a pre-specified number N as a biasing value. It is a way to
represent values with a balanced number of positive and negative numbers. It is a non-
weighted code. In XS-3, numbers are represented as decimal digits, and each digit is
represented by four bits as the BCD value plus 3 (the "excess" amount):

 The smallest binary number represents the smallest value. (i.e.

0 − Excess Value)
 The greatest binary number represents the largest value. (i.e.
2 N+1 − Excess Value − 1)

The primary advantage of XS-3 coding over BCD coding is that a decimal
number can be nines’ complemented (for subtraction) as easily as a binary number can
be ones’ complemented; just invert all bits. In addition, when the sum of two XS-3
digits is greater than 9, the carry bit of a four bit adder will be set high. This works
because, when adding two numbers that are greater or equal to zero, an "excess" value
of six results in the sum. Since a four bit integer can only hold values 0 to 15, an excess
of six means that any sum over nine will overflow.

Adding Excess-3 works on a different algorithm than BCD coding or regular

binary numbers. When you add two XS-3 numbers together, the result is not an XS-3
number. For instance, when you add 1 and 0 in XS-3 the answer seems to be 4 instead
of 1. In order to correct this problem, when you are finished adding each digit, you have
to subtract 3 (binary 11) if the digit is less than decimal 10 and add three if the number
is greater than or equal to decimal 10 (thus causing the number to wrap).

Binary to Gray Code Converter:

To convert a binary number to a Gray code number, the following rules apply:

1. The most significant digit (Left Most Bit) in the Gray Code is the
same as the corresponding digit in the binary number.
4
 2. Going from left to right, add each adjacent pair of binary digits to get
the next Gray code digit, regardless carries.

Any Binary no. converted into Gray code using following method.

For example: -

Step 1: 10 0 1Binary

1 Gray

Step 2: 1 0 0 1

1 1

Step 3: 1 0 0 1

1 1 0

Step 4 1 0 0 1

1 (Binary) 1001 = (Gray) 1101

. Gray to Binary Code Converter: To convert a Gray code number to a binary number,
the following rules apply:

(i) The first binary bit (MSB) is the same as that of the first Gray
code bit.
(ii) If the second Gray bit is 0, the second binary bit is the same as
that of the first binary; if the second Gray bit is 1, the second
binary bit is the inverse of its first binary bit.
(iii) Step (ii) is repeated for each successive bit.

Any Gray code will be into Binary number using following method.

Step 1: write the first binary bit 1 which is the MSB of the Gray Code.

1 1 0 1 Gray

1 Binary

5
 Step 2: The second bit of the Gray code is 1 and therefore the second bit of the
binary is 0, i.e. inverse of the first binary bit ‘1’

1 1 0 1

1 0

Step 3: The third bit of the Gray Code is 0 and therefore the third bit of the
binary is 0, i.e. same as the second binary bit ‘0’

1 1 0 1

1 0 0

Step 4: 1 1 0 1

1 0 0 1

1101(Gray) = 1001(Binary)

BCD to excess-3 code converter:

An excess-3 code is obtained by adding 3 to a decimal number. For example, to

encode the decimal number 6 into an excess-3 code, we must first add 3 in order to
obtain 9. The 9 is then encoded in its equivalent 4-bit binary code 1001. The excess-3
code is a self-complementing code, and this helps in performing subtraction operations
in digital computers, especially in the earlier models. The excess-3 code is also a
reflective code.

Example -The BCD number will be converted in to excess-3 code by following

method:

0010 BCD number

+
0011 3

0101 Excess-3 Code

6
Excess-3 code to BCD converter:
A BCD code is obtained by subtracting 0011 from a Excess-3 code. The
following example shows that the process of excess-3 code to BCD number.

Example – The excess – 3 code will be converted in to BCD number by

following method:

0101 Excess-3 Code

--
0011 3
10 BCD
PROCEDURE:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
BINARY TO GRAY CODE CONVERTOR

4.1.TRUTH TABLE

Binary input Gray code output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

7
DESIGN PROCEDURE:
From the truth table, the logic expressions for the gray code outputs can be
written as:
G3 = ∑m (8, 9, 10, 11, 12, 13, 14, 15)
G2 = ∑m(4, 5, 6, 7, 8, 9, 10, 11)
G1 = ∑m(2, 3, 4, 5, 10, 11, 12, 13)
G0 = ∑m(1,2,5,6,9,10,13,14)
K-MAP SIMPLIFICATION:

K-Map for G3:

K-Map for G2:

8
K-Map for G1:

K-Map for G0:

BOOLEAN EQUATIONS
From the above K-maps,
G3 = B3

DEVICE SELECTION:

X-OR gate – IC 7486

NO OF GATES REQUIRED:

X-OR gate = 3

9
LOGIC DIAGRAM:

PIN DIAGRAM:

10
OUTPUT VERIFICATION TABLE:
Binary input Gray code output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

GRAY CODE TO BINARY CODE

TRUTH TABLE:

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

11
DESIGN PROCEDURE:
From the truth table, the logic expressions for the Binary outputs can be written
as:
B3 = ∑m (8, 9, 10, 11, 12, 13, 14, 15)
B2 = ∑m(4, 5, 6, 7, 8, 9, 10, 11)
B1 = ∑m(2, 3, 4, 5, 8, 9, 14, 15)
B0 = ∑m(1, 2, 4, 7, 8, 11, 13, 14)
K-Map for B3:

B3 = G3
K-Map for B2:

12
K-Map for B1:

K-Map for B0:

BOOLEAN EQUATIONS:

B3 = G3

B1 = G3 G2

13
 BLOCK DIAGRAM:

G3 B3

4 bit Gray Gray to 4 bit

Code input G2 Binary B2 binary
Gray to
Converter output
Binary
Converter
G1 B1

G0 B0
DEVICE SELECTION:
IC 7486 – XOR Gate
NO. OF GATES REQUIRED:
IC 7486 (XOR Gate) - 3
LOGIC DIAGRAM

14
PIN DIAGRAM:

OUTPUT VERIFICATION TABLE:

Gray Code Binary Code
G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0

15
BCD TO EXCESS-3 CODE:
TRUTH TABLE:

BCD input Excess – 3 output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

DESIGN PROCEDURE:

From the truth table, the logic expressions for the Excess-3 code outputs can be written
as:
E3 = ∑m (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
E2 = ∑m(1, 2, 3, 4, 9, 10, 11, 12, 13, 14, 15)
E1 = ∑m(0, 3, 4, 7, 8, 9,11, 12, 13, 14, 15)
E0 = ∑m(0, 2, 4, 6, 8, 11, 12, 13, 14, 15)

16
K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E1:

17
 K-Map for E0:

BOOLEAN EQUATIONS:
E3 = B3 + B2 (B0 + B1)

BLOCK DIAGRAM:

B3 E3

B2 BCD to E2
BCD Excess-3
Excess–3
inputs code
Converter
outputs
B1 E1

B0 E0

DEVICE SELECTION:
OR Gate - IC 7432
AND Gate – IC 7408
NOT Gate – IC 7404
XOR Gate – IC 7486

18
NO. OF GATES REQUIRED:
OR Gate - IC 7432 - 1
AND Gate – IC 7408 - 1
NOT Gate – IC 7404 - 2
XOR Gate – IC 7486 - 2
LOGIC DIAGRAM

PIN DIAGRAM:

19
OUTPUT VERIFICATION TABLE:

BCD input Excess – 3 output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

20
EXCESS – 3 CODE TO BCD CODE

TRUTH TABLE
Excess – 3 Input BCD Output
E3 E2 E1 E0 B3 B2 B1 B0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

DESIGN PROCEDURE:

From the truth table, the logic expressions for the Excess-3 code outputs can be written
as:
B3 = ∑m (11, 12)
B2 = ∑m(7, 8, 9, 10,)
B1 = ∑m(5, 6, 9,10)
B0 = ∑m(4, 6, 8, 10, 12)
K-Map for A:

A = X1 X2 + X3 X4 X1

21
K-Map for B:

K-Map for C:

K-Map for D:

22
BOOLEAN EQUATIONS:
A = X1 X2 + X3 X4 X1

LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

PIN DIAGRAM

23
OUTPUT VERIFICATION TABLE:
Excess – 3 Input BCD Output
E3 E2 E1 E0 B3 B2 B1 B0

0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0

RESULT:
Thus The Binary to gray, Gray to binary, BCD to excess-3,Excess-3 to BCD
code convertor circuits are constructed and their truth tables are verified.

24
 2. DESIGN OF 4-BIT ADDER/SUBTRACTOR AND BCD ADDER
AIM:
To design and implement 4-bit adder/subtractor and BCD adder using IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR Gate IC 7486 1
3. NOT Gate IC 7404 1
3. IC Trainer Kit - 1
4. Patch Cords - 40

THEORY:
4-Bit Binary Adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in chain. The
augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers
from right to left, with subscript 0 denoting the least significant bits. The carries are
connected in chain through the full adder. The input carry to the adder is C0 and it
ripples through the full adder to the output carry C4.
The bits are added with the full adders, starting from the least significant
position (subscript 0), to form the sum bit and carry bit. The input carry C0 in the least
significant position must be 0. The value of Ci+1 in a given significant position is the
output carry of the full adder. This value is transferred into the input carry of the full
adder that adds the bits one
higher significant position to the left. The sum bits are thus generated for the correct
sum bits to appear at the outputs.
The 4 – bit adder is a typical example of a standard component. It can be used in
many applications involving arithmetic operations. Observe that the design of this
circuit by the classical method would require a truth table with 29 = 512 entries, since
there are nine inputs to the circuit.

25
4-Bit Binary Subtractor:
The subtraction of unsigned binary numbers can be done most conveniently by
means of complements. Remember that the subtraction A-B can be done by taking the
2’s complement o B and adding it to A. the 2’s complement can be obtained by taking
1’s complement and adding one to the least significant pair of bits. The 1’s complement
can be implemented with inverters and a one can be added to the sum through the input
carry.
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input carry
C0 must be equal to 1 when performing subtraction. The operation thus performed
becomes A, plus the 1’s complement of B, plus 1. This is equal to A plus the 2’s
complement of B. for unsigned numbers, this gives A-B if A≥B or the 2’s complement
of (B-A) if A<B. For signed numbers, the result is A-B, provided that there is no
overflow.
4- Bit Binary Adder/Subtractor:
The addition and subtraction operation can be combined into one circuit with
one common binary adder. The mode input M controls the operation. When M=0, the
circuit is adder circuit. When M=1, it becomes Subtractor. Each XOR gate receives
input M and one of the inputs of B. when M=0, we have B 0 =B. the full adders
receive the value of B, the input carry is 0, and the circuit performs A plus B. when
M=1, we have B 1 = B’ and C0 = 1. The B inputs are all complemented and a 1 is
added through the input carry. The circuit performs the operation A plus 2’s
complement of B. (The XOR output V is for detecting an overflow )
4-Bit Bcd Adder:
Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output
sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two
decimal digits must be represented in BCD and should appear in the form listed in the
columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4 bit adder to produce the
binary sum. The logic circuit that detects the necessary correction can be derived from
the truth table entries. It is obvious that a correction is needed when the binary sum has
an output carry K=1. The other six combinations from 1010 through 1111 that need a
correction have a 1 in position Z8,we specify further that either Z4 or Z2 must have a
26
1.the condition for a correction and an output carry can be expressed by the Boolean
function
C = K+Z8Z4+Z8Z2
When C=1, it is necessary to add 0110 to the binary sum and provide an output
carry for the next stage.
The two decimal digits, together with the input carry, are first added in the top
4-bit adder to produce the binary sum. When the output carry is equal to zero, nothing
is added to the binary sum. When it is equal to one, binary 0110 is added to the binary
sum through the bottom 4 – bit adder. The output carry generated from the bottom
adder can be ignored, since it supplies information already available at the output carry
terminal.
PROCEDURE:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.
Truth Table:

Subtraction
Input Data A Input Data B Addition

A A A A B B B B S S S S D D D D
C B
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0
0 0 1 0 1 0 0 0
0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 1
1 1 1 0 1 1 1 1
1 0 1 0 1 1 0 1

27
DEVICE SELECTION:
4 bit Binary Adder - IC 7483
XOR Gate - IC 7486
NO OF GATES REQUIRED:
4 bit Binary Adder - IC 7483 - 1
XOR Gate - IC 7486 – 5

LOGIC DIAGRAM:
4-BIT BINARY ADDER/ SUBTRACTOR

28
PIN DIAGRAM:
IC 7483: IC 7486:

29
OUTPUT VERIFICATION TABLE:

Input Data A Input Data B Addition Subtraction

A A A A B B B B S S S S D D D D
C B
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
1 0 0 0 0 0 1 0
1 0 0 0 1 0 0 0
0 0 1 0 1 0 0 0
0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 1
1 1 1 0 1 1 1 1
1 0 1 0 1 1 0 1

BCD ADDER
TRUTH TABLE:

BinarySum BCD SUM CARRY

K Z8 Z4 Z2 Z1 S4 S3 S2 S1 C
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 0
0 0 0 1 0 0 0 1 0 0
0 0 0 1 1 0 0 1 1 0
0 0 1 0 0 0 1 0 0 0
0 0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 1 1 0 0
0 0 1 1 1 0 1 1 1 0
0 1 0 0 0 1 0 0 0 0
0 1 0 0 1 1 0 0 1 0
0 1 0 1 0 0 0 0 0 1
0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 0 0 1 0 1
0 1 1 0 1 0 0 1 1 1
0 1 1 1 0 0 1 0 0 1
0 1 1 1 1 0 1 0 1 1
1 0 0 0 0 0 1 1 0 1
1 0 0 0 1 0 1 1 1 1
1 0 0 1 0 1 0 0 0 1
1 0 0 1 1 1 0 0 1 1

30
K MAP SIMPLIFICATION:

Y = S4 (S3 + S2)
CIRCUIT DIAGRAM:
BCD ADDER

DEVICE SELECTION: IC 7483 – BINARY ADDER

IC7432 –OR GATE
IC7408 – AND GATE

31
NO OF DEVICES REQUIRED:
IC 7483 – BINARY ADDER - 2
IC7432 – OR GATE -2
IC7408 – AND GATE -2
LOGIC DIAGRAM:

PIN DIAGRAM

32
VERIFICATION TABLE:

BinarySum BCD SUM CARRY

K Z8 Z4 Z2 Z1 S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1

RESULT:
Thus the 4-bit binary adder / subtractor and BCD adder are designed using
IC 7483 and their truth tables are verified.
33
 3. DESIGN AND IMPLEMENTATION OF MULTIPLEXER&
DEMULTIPLEXER
AIM:
To design multiplexer & demultiplexer using logic gates
APPARATUS REQUIRED:

S.No COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit
that selects binary information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a set of selection
lines. Normally there are 2n input line and n selection lines whose bit combination
determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used
as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.

PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

34
MULTIPLEXER:
TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

DESIGN PROCEDURE:
From the truth table, the logic expressions for the gray code outputs can be
written as:
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0
FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

DEVICE SELECTION:
NOT Gate – (IC7404)
3 i/p AND Gate – (IC7411)
OR Gate – (IC7432)

NO OF GATES REQUIRED:
NOT Gate – (IC7404)-1
AND Gate – (IC7411)-4
OR Gate – (IC7432)- 3

35
CIRCUIT DIAGRAM FOR MULTIPLEXER:

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

36
OUTPUT VERIFICATION TABLE:
Data select inputs Output
S1 S0 Y
0 0
0 1
1 0
1 1

DEMULTIPLEXER:
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

DESIGN PROCEDURE:
From the truth table, the logic expressions for the gray code outputs can be
written as:
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0
FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:

37
DEVICE SELECTION:
NOT Gate – (IC7404)
AND Gate – (IC7411)

NO OF GATES REQUIRED:
NOT Gate – (IC7404)-2
AND Gate – (IC7411)-4

38
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

OUTPUT VERIFICATION TABLE:

Data i/p Select i/p Outputs
D S1 S0 Y3 Y2 Y1 Y0

RESULT:
Thus the multiplexer and demultiplexer are designed and implemented using
logic gates and truth tables are verified.

39
 4. DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM:
To design an encoder and decoder circuits using logic gates and study of IC
7445 and IC 74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:
ENCODER:
An encoder is a digital circuit that performs inverse operation of a decoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight
inputs, one for each octal digit and three output that generate the corresponding binary
code. In encoder it is assumed that only one input has a value of one at any given time
otherwise the circuit is meaningless. It has an ambiguity that when all inputs are zero
the outputs are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded
input into coded output where input and output codes are different. The input code
generally has fewer bits than the output code. Each input code word produces a
different output code word i.e there is one to one mapping can be expressed in truth
table. In the block diagram of decoder circuit the encoded information is present as n
input producing 2n possible outputs. 2n output values are from 0 through out 2n – 1.

PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table

40
ENCODER:

TRUTH TABLE:

INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

DESIGN PROCEDURE:
From the truth table, the logic expressions for the gray code outputs can be
written as:

LOGIC DIAGRAM FOR ENCODER:

DEVICE SELECTION:
OR Gate – (IC7432)

NO OF GATES REQUIRED:
41
 OR Gate – (IC7432)-9

DECODER:
TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

DESIGN PROCEDURE:
From the truth table, the logic expressions for the gray code outputs can be
written as:

D0 =A’B’
D1 =A’B
D2 = AB’
D3 = AB

LOGIC DIAGRAM FOR DECODER:

RESULT:
Thus the encoder and decoder using logic gates are designed and truth tables are
verified.
42
 5. CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER
AND MOD 10/MOD 12 RIPPLE COUNTER

AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its

clock input. Counter represents the number of clock pulses arrived. A specified
sequence of states appears as counter output. This is the main difference between a
register and a counter. There are two types of counter, synchronous and asynchronous.
In synchronous common clock is given to all flip flop and in asynchronous first flip
flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q
output of previous stage. A soon the clock of second stage is triggered by output of first
stage. Because of inherent propagation delay time all flip flops are not activated at same
time which results in asynchronous operation.

PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

43
4 BIT RIPPLE COUNTER:

TRUTH TABLE
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

44
PIN DIAGRAM FOR IC 7476:

MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

45
MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:

CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 0 0 0 0

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

RESULT:
Thus the 4 bit ripple counter and mod 10/ mod 12 ripple counters are designed
and truth tables are verified.

46
 6. DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN
COUNTER
AIM:
To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its
clock input. Counter represents the number of clock pulses arrived. An up/down
counter is one that is capable of progressing in increasing order or decreasing order
through a certain sequence. An up/down counter is also called bidirectional counter.
Usually up/down operation of the counter is controlled by up/down signal. When this
signal is high counter goes through up sequence and when up/down signal is low
counter follows reverse sequence.
PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

3 BIT SYNCHRONOUS UP/DOWN COUNTER

CHARACTERISTICS TABLE FOR JK FLIPFLOP:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

47
 Input Present State Next State A B C
Up/Down
QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
TRUTH TABLE FOR JK FLIPFLOP:

K MAP FOR JK FLIPFLOP:

48
STATE DIAGRAM FOR 3 BIT UP/DOWN COUNTER:

49
PIN DIAGRAM

PIN DIAGRAM FOR IC 7476 PIN DIAGRAM FOR IC 7411

PIN DIAGRAM FOR IC 7432 PIN DIAGRAM FOR IC 7486

50
PIN DIAGRAM FOR IC 7404

LOGIC DIAGRAM:

51
DEVICE SELECTION:
No of gates selected: 9
Gate details:
Not gate (7404) – 2
Or gate (7432) – 1
Xor gate (7486) – 1
And gate (74LS11) – 2
Jk flip flop (IC 7476) – 3

RESULT:
Thus the design and implementation of 3 bit synchronous up/down counter is
constructed and truth table is verified

52
53