Verilog Syntax Cheat Sheet

- Data Formats: - Modules

- Standard Syntax: [WIDTH]'[BASE][VALUE] - Encapsulate blocks of logic into a reusable
- Example: 16'ha; -> 16 bit field, value of 0x000a container with a well-defined interface
- Bases: d = decimal, b = binary, h = hex - Example: module adder
- Strings treated as 1 byte-per-character #(
- Operations parameter WIDTH = 16
- Bitwise )
- Example: 3’b010 | 3’b110 -> 3’b111 [OR] (
3’b101 & 3’b100 -> 3’b100 [AND] input [WIDTH-1:0] a; // Signals In
3’b101 ^ 3’b100 -> 3’b001 [XOR] input [WIDTH-1:0] b;
~3’b010 -> 3’b101 [NOT] output [WIDTH:0] sum; // Signals Out
- Shifts output overflow;
- Example 4’b0111 << 1 -> 4’b1110 [Left Shift] );
4’b1111 >> 1 -> 4’b0111 [Right Shift]
- Arithmetic // Logic Goes Here
- Example: 3’b010 + 3’b100 -> 3’b110 [Addition] endmodule;
3’b100 – 3’b001 -> 3’b011 [Subtraction] - Instantiating Modules
- Comparators - Example: adder // Module Name
- Example: 3’b100 > 3’b011 -> 1’b1 [Greater Than] #( .WIDTH (16) )
3’b100 == 3’b010 -> 1’b0 [Equal To] adderInst // Instance Name
3’b100 != 3’b000 -> 1’b1 [Not Equal To] ( .a (w_a),
- Wires and Regs // Port b is attached to wire w_b
- Wires .b (w_b),
- Continuous assignments; do not "hold value" .sum (w_sum),
- Typically used for combinatorial logic assignment .overflow (w_overflow) );
- If unassigned, dflt value is 'z' (high impedance) - Constructs
- Use w/ 'assign' Statements - If/Else
- Example: assign z = x & y; - Example: always@(posedge clk) begin
assign w = z | v; if (y)
- z updates whenever x and y update x <= v;
w updates whenever z or v updates else if (w)
- Regs x <= w;
- Hold prior value until sensitivity list fires else
- A register does not always imply a flip-flop x <= x;
- Often used for clocked logic (i.e. registers) end
- Has a default value of ‘x’ (unknown) if unassigned - If...Else cases imply priority and are evaluated
- Example: always@(posedge clk) begin sequentially
if (rst) - Case Statements
q <= '0; - Example: // Combinatorial Logic
else always@(*) begin
q <= y; case (x)
end 1'b0:
- Triggered on positive edge of each clock y <= v;
- ‘q’ synthesizes as a register 1'b1:
- For best results you should only assign a reg in a y <= w;
single process default:
- Use ‘<=’ in processes to assign to regs. y <= '0;
- Variable declaration (Scalars, 2d Arrays) endcase
- Types end
- Single Bits: - This should resolve to a 2-to-1 Mux. 'x' is
- Ex: wire x; reg y; // 1 Bit Each the select line. v/w are Inputs
- Bit Vectors - ‘default’ case is not strictly necessary here
- Ex: wire [2:0] x; reg [2:0] y; // 3 Bits Each since all combinations are covered. It is best
- 2d Vectors practice to include it though.
- Ex: wire [7:0] x [3:0] // 4x8 Entries
- Bit Manipulation
- Bit Slicing
- Example: reg [15:0] data; wire [7:0] field;
// Take Lower 8 Bits of Data
assign field = data[7:0];
- Bit Concatenation
- Example: reg [15:0] data; wire [7:0] field;
// Flip the Nibbles
assign field = {data[3:0], data[7:4]};
- Array Indexing
- Example: wire [7:0] x [3:0]
x[0] // 8 Bit Entry at Array Idx 0
x[1][3:0] // Lower 4 Bits of Idx 1
Verilog Syntax Cheat Sheet