ECE520 – VLSI Design
Lecture 16: Adders
Payman Zarkesh-Ha
Office: ECE Bldg. 230B
Office hours: Tuesday 2:00-3:00PM or by appointment
E-mail: [email protected]
ECE520 – Lecture 16 University of New Mexico Slide: 1
Review of Last Lecture
Dynamic Logic
● Advantages of dynamic logic
● Problems of dynamic logic
● Fixes to problems in dynamic logic
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1
Today’s Lecture
Adders: A Basic Arithmetic Building Block
● Ripple-Carry Adder
● Mirror Adder
● Transmission Gate Adder
● Carry Bypass Adder
● Carry-Select Adder
● Carry Lookahead Adder
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Design of Adders
These are the heart of an ALU
They are often on a critical path; i.e. a speed limiting timing path
This is a broad topic and still the subject of ongoing research
Consequently, we’ll only cover the basic types
Bit 3
Data-Out
Multiplexer
Bit 2
Data-In
Register
Adder
Shifter
Bit 1
Bit 0
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Truth Table for a Full Adder
A B
Cin Full Cout
adder
Sum
S = A B Ci
= A BC i + ABC i + ABC i + ABCi
C o = AB + BC i + AC i
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Definition of: Generate, Propagate, and Delete
We define three new variables which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A B
Delete = A B
Can also derive expressions for S and Co based on D and P
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Ripple Carry Adder
Each bit looks at the preceding carry out and its inputs
The delay of the adder is linear with the number of bits
Each bit is a delay stage since it waits for the preceding bit carry
result
tadder = (N-1)tcarry + tsum
A0 B0 A1 B1 A2 B2 A3 B3
Ci,0 Co,0 Co,1 Co,2 Co,3
FA FA FA FA
( Ci,1)
S0 S1 S2 S3
Goal: Make the fastest possible carry path circuit
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Conventional Implementation
Conventional design requires 2 XOR and 3 NAND2 logic gates
This will require 36 transistor (12 for each XOR and 4 for each
NAND)
What input of NAND2 makes the carry faster?
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Complementary Static CMOS Full Adder
VDD
VDD
Ci A B
A B
A
B
Ci B
VDD
A
X
Ci
Ci A S
Ci
A B B VDD
A B Ci A
Co B
28 Transistors
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Inversion Property
Inverting all inputs to a full adder results in inverted values for
all outputs
A B A B
Ci FA Co Ci FA Co
S S
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Minimizing Critical Path by Inverter Removal
Allows us to remove inverter in carry chain (at what cost?)
Even cell Odd cell
A0 B0 A1 B1 A2 B2 A3 B3
Ci,0 Co,0 Co,1 Co,2 Co,3
FA FA FA FA
S0 S1 S2 S3
Exploit Inversion Property
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Mirror Adder
Uses a symmetric architecture (NOT DUAL)
VDD
VDD VDD A
A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A
24 transistors
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Mirror Adder Details
The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the
carry-generation circuitry
When laying out the cell, the most critical issue is the
minimization of the capacitance at node Co. The reduction of the
diffusion capacitances is particularly important.
The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .
The transistors connected to Ci are placed closest to the output.
Only the transistors in the carry stage have to be optimized for
optimal speed. All transistors in the sum stage can be minimal
size.
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Transmission Gate XOR
This transmission XOR gate requires only 8 transistor
Swap inverter to top for XNOR gate
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Transmission Gate Full Adder
This requires only 24 transistors
But, still delay in Carry path is large (Series path to CO)
P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci
A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P
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Carry-Bypass Adder
Ripple carry can be accelerated by sending the carries forward
and looking at more than one at a time
The result is a carry bypass adder
P0 G1 P0 G1 P2 G2 P3 G3
Ci,0 C o,0 C o ,1 Co,2 Co,3
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o ,0 Co,1 C o,2
Multiplexer
FA FA FA FA
Co,3
Idea: If (P0 and P1 and P2 and P3 = 1)
then Co3 = C0, else “kill” or “generate”.
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Carry-Bypass Adder – Critical Path
Still overall delay is a linear function of the number of adder bits
But at reduced slope
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup tsetup Setup tbypass Setup Setup
Carry Carry Carry Carry
propagation propagation propagation propagation
Sum Sum Sum tsum Sum
M bits
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum
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Carry-Ripple versus Carry-Bypass
tp
ripple adder
bypass adder
4..8
N
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Carry-Select Adder
Basic idea is to precompute both possibilities, and choose when
Cin is available
The carry select adder generates two sums, one for C=1 and one
for C=0. The correct answer is selected when the carry is known
This method consumes more power!
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Carry-Select Adder – Critical Path
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup Setup Setup Setup
0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry
1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry
Multiplexer Multiplexer Multiplexer Multiplexer
Ci,0 Co,3 Co,7 Co,11 Co,15
Sum Generation Sum Generation Sum Generation Sum Generation
S0–3 S4–7 S8–11 S12–15
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Carry-Lookahead Adder
It all comes down to computing carry out faster
The obvious expensive solution:
● Carry out of bit 4 depends on all inputs to bits 1-4 so, treat it as a single
Boolean expression and make a circuit, possibly one large complex gate
● Simplifying down to P and G helps a lot here
Even so 4 bits of lookahead= 9 input function
Cout = G3 + P3 (G2 + P2 (G1 + P1 (G0 + P0 Cin)))
Called Carry lookahead
Different amounts of lookahead possible
Just makes blocks of bits act like single bit
Can be combined with other designs
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Example: 4 bit Carry-Lookahead Adder
Expanding Lookahead equations: VDD
C o k = G k + Pk Gk – 1 + Pk – 1 Co k – 2 G3
G2
G1
All the way:
G0
C o k = G k + P k G k – 1 + P k – 1 + P 1 G 0 + P0 Ci 0
Ci,0
Co,3
P0
P1
P2
P3
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Example: 16 bit Carry-Lookahead Adder
These can be similarly extended to a 32 bit adder
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