IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO.

4, APRIL 2004 569

Two-Dimensional Analytical Modeling of Fully

Depleted DMG SOI MOSFET and Evidence for
Diminished SCEs
M. Jagadesh Kumar, Senior Member, IEEE, and Anurag Chaudhry

Abstract—A two–dimensional (2-D) analytical model for the has better control over its active device region in the thin film
surface potential variation along the channel in fully depleted and hence charge-sharing effects from source/drain regions
dual-material gate silicon-on-insulator MOSFETs is developed to are substantially reduced. However, the thin-film thickness has
investigate the short-channel effects (SCEs). Our model includes
the effects of the source/drain and body doping concentrations, to reduce to the order of 10 nm to significantly improve the
the lengths of the gate metals and their work functions, applied device performance, which becomes prohibitively difficult to
drain and substrate biases, the thickness of the gate and buried manufacture and causes large device external resistance due to
oxide and also the silicon thin film. We demonstrate that the shallow source/drain extension (SDE) depths
surface potential in the channel region exhibits a step function Long et al. [2] recently demonstrated that the application of
that ensures the screening of the drain potential variation by
the gate near the drain resulting in suppressed SCEs like the dual-material gate (DMG) in bulk MOSFET leads to a simulta-
hot-carrier effect and drain-induced barrier-lowering (DIBL). neous transconductance enhancement and suppression of SCEs
The model is extended to find an expression for the threshold due to the introduction of a step function in the channel po-
voltage in the submicrometer regime, which predicts a desirable tential. In a DMG MOSFET, the work function of metal gate
“rollup” in the threshold voltage with decreasing channel lengths. 1 (M1) is greater than metal gate 2 (M2) i.e., for an
The accuracy of the results obtained using our analytical model is
verified using 2-D numerical simulations. n-channel MOSFET and vice-versa for a p-channel MOSFET.
However, the effects of the DMG structure have not been studied
Index Terms—Device scaling, insulated gate field effect tran- so far in the case of SOI MOSFETs, which play an important
sistors, short-channel effects (SCEs), silicon-on-insulator (SOI)
MOSFET, threshold voltage, two-dimensional (2-D) modeling. role in the present day CMOS design. The aim of this paper is,
therefore, to study for the first time the potential benefits of-
fered by the DMG gate in suppressing the SCEs in SOI MOS-
I. INTRODUCTION FETs using two-dimensional (2–D) modeling. In this paper, an
analytical short-channel model for a fully depleted DMG SOI
I N KEEPING with the progress in process technology,
CMOS devices have been scaled down, continuously
pushing the MOS technology into the deep-submicrometer
MOSFET is presented by solving the 2-D Poisson equation. The
model is used to calculate the surface potential distribution in
era. However, when the channel length shrinks, the absolute the SOI thin film under the two metal gates and to explain the
value of threshold voltage becomes smaller due to the reduced unique attributes of the DMG structure in suppressing the SCEs
controllability of the gate over depletion region by the increased like hot-carrier effect, DIBL and threshold voltage “rollup”
charge-sharing from the source/drain. Therefore, the study of in SOI MOSFETs. This model thus provides an efficient tool for
short-channel effects (SCEs) has assumed a significant role design and characterization of the novel DMG SOI MOSFET.
because both the threshold voltage rolloff at decreasing gate The effects of varying device parameters can easily be inves-
length as well as drain-induced barrier lowering (DIBL) at tigated using the simple models presented in this paper. The
increasing drain voltage pose a serious challenge to the efforts model results are verified by comparing them with the 2-D sim-
for down-scaling the CMOS technology. ulated results from MEDICI [3].
Thin-film, fully depleted silicon-on-insulator (SOI) MOS-
FETs offer superior electrical characteristics over bulk MOS II. TWO-DIMENSIONAL MODEL FOR SURFACE POTENTIAL
devices, such as reduced junction capacitances, increased A schematic cross-sectional view of a fully depleted SOI
channel mobility, excellent latchup immunity and reduced MOSFET is shown in Fig. 1 with gate metals M1 and M2 of
SCEs [1]. As a consequence, deep-submicrometer SOI circuit lengths and , respectively. Assuming that the impurity
design and simulation are increasingly becoming important in density in the channel region is uniform, and the influence of
very large-scale technology (VLSI) technology research. In charge carriers and fixed oxide charges on the electrostatics of
contrast to the bulk device, the front gate of the SOI device the channel can be neglected, the potential distribution in the
silicon thin film, before the onset of strong inversion can be
Manuscript received June 23, 2003; revised November 18, 2003. The review written as [4]
of this paper was arranged by Editor R. Shrivastava.
The authors are with the Department of Electrical Engineering, Indian Insti- for
tute of Technology, Delhi, 110 016 India (e-mail: [email protected]).
Digital Object Identifier 10.1109/TED.2004.823803 (1)
0018-9383/04$20.00 © 2004 IEEE
570 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004

1) Electric flux at the gate/front-oxide interface is contin-

uous for both the metal gates

for M1 (5)

for M2 (6)

where is the dielectric constant of the oxide, is the

gate oxide thickness, and

and

where is the gate-to-source bias voltage, and

Fig. 1. Cross-sectional view of an n-channel fully depleted DMG SOI are the front-channel flatband voltages of M1 and
MOSFET. M2, respectively.
2) Electric flux at the interface of buried oxide and the back-
channel is continuous for both the metal gates.
where is the film doping concentration, is the dielectric
constant of silicon, is the film thickness and is the de- for M1 (7)
vice channel length. The potential profile in the vertical direc-
tion, i.e., the -dependence of can be approximated by
for M2 (8)
a simple parabolic function as proposed by Young [4] for fully
depleted SOI MOSFETs
where is the buried oxide thickness, is the poten-
(2) tial function along the backside oxide–silicon interface,
and , where is the substrate
where is the surface potential and the arbitrary coeffi- bias, and is the back-channel flatband voltage.
cients and are functions of only. 3) Surface potential at the interface of the two dissimilar
In a conventional SOI MOSFET, the gate is made of only metals is continuous
one material, but in the DMG structure, we have two different
materials with different work functions, which are amalgamated
(9)
together laterally. Therefore, the flatband voltage for the two
gates would be different, as it depends upon and , the
metal work functions of M1 and M2, respectively, which are 4) Electric flux at the interface of the two dissimilar metals
given as is continuous

and (10)

The semiconductor work function can be written as

5) The potential at the source end is

(11)
where is the Fermi potential, is the
silicon bandgap, is the electron affinity, is the thermal 6) The potential at the drain end is
voltage, and is the intrinsic carrier concentration.
In the DMG structure, since the gate is divided into two parts, (12)
the potential under gate regions M1 and M2 can be written as
where is the built-in
potential across the body–source junction. The constants
for (3) , , , and in (3) and (4) can be
deduced from the boundary conditions (5)–(8). Substi-
tuting their values in (3) and (4) and then in (1) we obtain
for (4)

The Poisson’s equation is solved separately under the two gate and
regions using the following boundary conditions. (13)
KUMAR AND CHAUDHRY: 2-D ANALYTICAL MODELING OF FULLY DEPLETED DMG SOI MOSFET 571

where The DIBL effect can be demonstrated by plotting the surface

potential minima , as a function of the position along
the channel for different drain bias conditions.
The electric field pattern along the channel determines the
electron transport velocity through the channel. The electric
field component in the -direction, under the metal gates M1
and M2 is given as

(18)

and (19)

The above two equations are useful in examining how the drain
side electric field is modified by the DMG structure.

III. TWO-DIMENSIONAL THRESHOLD VOLTAGE MODEL FOR

where , and . DMG FD SOI MOSFET
The above equations are simple second-order nonhomoge- The threshold voltage is that value of the gate voltage
nous differential equations with constant coefficients, which at which a conducting channel is induced at the surface of SOI
have a solution of the form MOSFET. In a fully depleted thin film SOI, it is desirable that
the front channel turns on before the back channel. Therefore,
the threshold voltage is taken to be that value of gate source
(14)
voltage for which , where is the difference
between the extrinsic Fermi level in the bulk region and the in-
trinsic Fermi level. In the case of DMG structure, due to the co-
(15) existence of metal gates M1 and M2, with different work func-
tions, the surface potential minima is solely determined by the
where and . Now using boundary condi- metal gate with higher work function. So the threshold voltage
tions (9)–(12) to solve for , , and , we obtain the equa- is defined as the value of at which the minimum surface po-
tion shown at the bottom of the page, where and tential equals . Hence, we can determine the value
. The above expression for surface potential can of threshold voltage as the value of by solving (16).
be reduced to the form presented in [4] for a single material When and , we can approximate and as
gate (SMG) structure upon substituting , and
in (14).
The minimum potential of the front-channel can be calculated
from (14) as and

(16)
and upon solving for , we obtain an expression of the form
The minima occurs at for the threshold voltage

(17)

and
572 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004

where

(a)

and

A significant result of this formulation is the ability to tune the

surface potential by “gate-material engineering.” The depen-
dence of surface potential and hence, threshold voltage on the
difference between the gate material work functions of the two
gate metals can offer another degree of freedom for the SOI tran-
sistor design. This has also been observed for the DMG structure
on bulk MOSFETs [5].

IV. RESULTS AND DISCUSSION

To verify the proposed analytical model, the 2-D device sim- (b)
ulator MEDICI [3] was used to simulate the surface potential Fig. 2. (a) Surface channel potential profiles of a fully depleted DMG
distribution within the silicon thin film. A fully depleted (FD) SOI MOSFET obtained from the analytical model and MEDICI simulation
n-channel DMG SOI structure is implemented in MEDICI for different drain biases with a channel length L = 0:1 m. (b) Surface
channel potential profiles of a fully depleted DMG SOI MOSFET obtained
having uniformly doped source/drain and body regions. Typical from the analytical model and MEDICI simulation for different drain biases
values of the workfunction of gate metals M1 and M2 are with a channel length L = 0:2 m. The screening effect is distinctly visible.
chosen as 4.77 and 4.1 eV, respectively, for a DMG SOI, and The parameters used are t = 5 nm, t = 450 nm, t = 150 nm, and
4.77 eV for the SMG SOI gate workfunction. All the device V = 0 V.
parameters of DMG and SMG are equivalent unless otherwise
stated and are given in the figure captions.
In Fig. 2, the calculated and simulated values of surface
potential are plotted against the horizontal distance in the
channel for channel lengths of 0.1 m and 0.2 m at different
drain voltages. It can be seen from the figure that due to the
presence of the DMG, there is no significant change in the
potential under the gate M1 as the drain bias is increased even
for channel lengths up to 100 nm. Hence, the channel region
under M1 is “screened” from the changes in the drain potential,
i.e., the drain voltage is not absorbed under M1, but is under
M2. As a consequence, has only a very small influence
on drain current after saturation and the drain conductance
Fig. 3. Longitudinal electric field along the channel toward the drain end
is reduced. It is evident from the figure that the shift in the obtained from the analytical model and MEDICI simulation in DMG SOI
point of the minimum potential is almost zero irrespective of and SMG-SOI MOSFETs with a channel length L = 0:4 m and a drain
the applied drain bias. This is a clear indication that the DIBL bias V = 1:75 V. The parameters used are V = 0:15 V, t = 5 nm,
effect is considerably reduced for the DMG SOI MOSFET. The t = 400 nm, t = 100 nm, V 2
= 0 V, and N = 6 10 cm .
model predictions correlate well with the simulation results
proving the accuracy of our proposed analytical model. the presence of a lower function gate at the drain side reduces
In Fig. 3, the electric distribution along the channel near the peak electric field considerably. This reduction of the
the drain is shown for SMG and DMG SOI MOSFETs with a electric field experienced by the carriers in the channel can be
channel length m. It is evident from the figure that interpreted as the reduction of the hot-carrier effect at the drain
KUMAR AND CHAUDHRY: 2-D ANALYTICAL MODELING OF FULLY DEPLETED DMG SOI MOSFET 573

Fig. 4. Variation of surface potential with position in channel for different

combination of gate lengths L and L , keeping the sum (L + L ) constant.
(a)

(b)
Fig. 5. Variation of the front-channel minimum potential with channel length
= +
L ( L L ) for fully depleted DMG SOI MOSFETs for different silicon Fig. 6. (a) Threshold voltage versus channel length for channel lengths up to
thin-film thickness, and with L constant at 0.1 m. The parameters used are 100 nm with V = 50 mV. (b) Threshold voltage versus channel length for
V = 0 15: V, t =5 nm, t = 400 nm, and V =0 V. V = 50 mV. The parameters used are t =5 nm, t = 450 nm, t =
50 nm, and V =0 V.

end. As shown in the figure, the results from the analytical

model are in close proximity with the simulation results. is verified by the close match between the analytical results and
Fig. 4 shows the variation of surface potential with the the 2-D simulation results [3].
normalized channel position for different combinations of gate In Fig. 6, the calculated values of threshold voltage as a func-
lengths and of M1 and M2, respectively, keeping the tion of channel-length are compared with those obtained from
sum of total gate length, ( ), to be constant. It is seen 2-D simulation [3] extracted from the commonly used max-
from the figure that the position of minimum surface potential, imum transconductance method for two different values of .
lying under M1 is shifting toward the source as the length of It is seen from Fig. 6(a) that the threshold voltage obtained from
gate M1 is reduced. This causes the peak electric field in the the analytical model tracks the simulation values very well but
channel to shift more toward the source end and thus there is with an insignificant negative offset of approximately 90 mV
a more uniform electric field profile in the channel. Moreover, whereas the offset is nearly 20–50 mV for Fig. 6(b). This small
it is observed that the channel potential minima for the three discrepancy between analytical and simulated values is due
cases are not the same. This happens because as increases, a to the two different definitions of threshold voltage used for
portion of the channel controlled by the gate metal with larger comparison viz., and . As is often done in liter-
workfunction [6] is increased. ature, in our model we have used as the threshold
The variation of the front-channel minimum potential as a condition while MEDICI calculates the threshold voltage from
function of channel length ( ) for fully depleted the maximum condition. The model results when compared
DMG SOI with silicon thin-film thickness and 50 nm to the simulation data, however, justify the validity of the model
is shown in Fig. 5. In the case of DMG SOI MOSFETs, the de- for channel lengths well up to 100 nm and as can be discerned
pendence of minimum channel potential on the thin-film thick- from the figures, the predictions are in line with MEDICI results.
ness can be more effectively reduced by decreasing as com- In Fig. 7, the effect of “gate-workfunction engineering” on
pared to the SMG SOI MOSFETs. This is due to the existence of the threshold voltage is shown for a fully depleted DMG SOI
a workfunction difference in the case of DMG SOI MOSFETs. MOSFET of channel length ( ) 0.5 m for two
The validity of model for the minimum surface potential under different ratios of and . It is evident that with the in-
the gate for different combinations of and of and creasing workfunction difference, threshold voltage increases
574 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004

method of tilt-angle evaporation (TAE) [2]. With the CMOS

processing technology aggressively pushing forward, fabri-
cating sub-100-nm feature gate lengths should not preclude the
possibility of realizing the substantial performance gains over
conventional SOI and excellent immunity against SCEs that
the DMG SOI MOSFET promises.

REFERENCES
[1] T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, “Experimental
0.25-m-gate fully depleted CMOS/SIMOX process using a new
two-step LOCOS isolation technique,” IEEE Trans. Electron Devices,
vol. 42, pp. 1481–1486, Aug. 1995.
[2] W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, “Dual material gate
Fig. 7. Threshold voltage variation with gate workfunction difference with (DMG) field effect transistor,” IEEE Trans. Electron Devices, vol. 46,
 fixed at 4.1 eV for the DMG SOI MOSFET a with channel length L
= + =5 = 400
pp. 865–870, May 1999.
( L L ) of 0.5 m. The parameters used are t nm, t nm,
= 50 =0 = 6 2 10
[3] MEDICI 4.0, Technology Modeling Associates, Palo Alto, CA, 1997.
t nm, V V, and N cm . [4] K. K. Young, “Short-channel effect in fully depleted SOI MOSFETs,”
IEEE Trans. Electron Devices, vol. 36, pp. 399–402, Feb. 1989.
[5] X. Zhou, “Exploring the novel characteristics of hetero-material gate
but, for the same workfunction difference a higher ratio field-effect transistors (HMGFETs) with gate-material engineering,”
leads to a corresponding increase in threshold voltage. This is IEEE Trans. Electron Devices, vol. 47, pp. 113–120, Jan. 2000.
[6] X. Zhou and W. Long, “A novel hetero-material gate (HMG) MOSFET
due to the increasing proportion of channel length , under the for deep-submicrometer ULSI technology,” IEEE Trans. Electron De-
larger workfunction gate M1. vices, vol. 45, pp. 2546–2548, Dec. 1998.

V. CONCLUSION
For the first time, we have examined the effectiveness of the M. Jagadesh Kumar (SM’99) was born in Mami-
DMG structure in fully depleted SOI MOSFETs to suppress dala, Nalgonda district, Andhra Pradesh, India. He re-
ceived the M.S. and Ph.D. degrees, both in electrical
SCEs by developing a 2-D analytical model for surface poten- engineering from the Indian Institute of Technology
tial and threshold voltage and comparing the results with accu- (IIT), Madras, India.
rate MEDICI [3] simulations. The calculated values of the sur- From 1991 to 1994, his postdoctoral research was
in modeling and processing of high-speed bipolar
face potential in the silicon thin film obtained from the proposed transistors with Prof. D. J. Roulston, Department
model agree well with the simulated results. Our results unam- of Electrical and Computer Engineering, University
biguously establish that the introduction of the DMG structure of Waterloo, Waterloo, ON, Canada. During his
stay at Waterloo, he also collaborated with Prof.
in a fully depleted SOI MOSFET leads to subdued SCEs due S. G. Chamberlain on amorphous silicon TFTs. From 1994 to 1995, he was with
to a step-function in the channel potential profile. The shift in the Department of Electronics and Electrical Communication Engineering, IIT,
the surface channel potential minima position is negligible with Kharagpur, and later moved to the Department of Electrical Engineering, IIT,
Delhi, where he was made an Associate Professor in 1997. More than once, his
increasing drain biases. The electric field in the channel at the teaching has been rated as “outstanding” by the Faculty Appraisal Committee,
drain end is also reduced leading to reduced hot-carrier effect. IIT Delhi. His research interests are in VLSI device modeling and simulation,
Also, the variation of the minimum channel potential with de- IC technology, and power semiconductor devices.
Dr. Kumar is a Fellow of the Institute of Electronics and Telecommunication
creasing thin-film thickness can be more effectively reduced in Engineers (IETE), India.
the DMG structure at shallow thin-film thicknesses. Further, it
is clearly seen that the DMG structure gives rise to the desir-
able threshold voltage “rollup” with decreasing channel lengths.
Thus, the introduction of the DMG structure opens up a new Anurag Chaudhry received the B.E. degree (with
distinction) in electronics and communication
avenue to improve the short-channel behavior of the SOI MOS- engineering from Birla Institute of Technology,
FETs over their single-gate SOI and the bulk counterparts. Mesra, India, in 1999. He is currently pursuing the
One of the difficulties in integrating DMG structure in the M.S. degree at the Indian Institute of Technology,
Delhi, India.
present CMOS technology maybe the increased constraint From 1999 to 2001, he worked as a Design Engi-
on lithography due to its asymmetric gate structure. Zhou neer in the FPGA Group, ST Microelectronics, Ltd.,
[5] suggested two fabrication procedures requiring only one Noida, India. His work primarily involved proposing
logic block architecture for an FPGA. His research
additional mask step for realizing the DMG FET in bulk CMOS interests include modeling and simulation of novel
technology. Wong et al. demonstrated a DMG HFET using the device structures on SOI MOSFETs.