Design and Implementation of
VLSI Systems
Lecture 06
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EXERCISE 1
Find the output voltage for the pass transistor networks
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EXERCISE 2
Sketch a transistor-level schematic for a compound
CMOS logic gate for each of the following functions:
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EXERCISE 3
Sketch a transistor-level schematic for the logic
function Y = AB + BC + CA
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EXERCISE 4
Using only NAND gate, generate following logic gates:
• NOT
• AND
• OR
• XOR
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EXERCISE 5
Find the logic function of following circuit
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EXERCISE 6
Calculate the transistor widths chosen to achieve effective
rise and fall resistances equal to a unit inverter of following
circuits
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EXERCISE 7
Select gate sizes y and z to minimize delay from A to B
Logical Effort: G=
Electrical Effort: H=
Branching Effort: B=
Path Effort: F=
Best Stage Effort: f=
Delay: D=
Work backward for sizes:
z=
y=
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EXERCISE 8
1 ) Sketch a 6 input OR gate with transistor widths
chosen to achieve effective rise and fall resistances equal
to a unit inverter
2) Cin and Cout of the gate above is 30 and 90
respectively. Using Linear Delay Model, calculate
transistor width to achieve best delay for this gate
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EXERCISE 9
1 ) Sketch a 2-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to a
unit inverter (R).
2) Using RC Delay Model, estimate tpdr tpdf tcdr and tcdf of
this gate driving h identical gates.
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EXERCISE 10
Using RC Delay Model, derive the equation of Linear
Delay Model to calculate delay of a gate
d = f + p = gh + p (in unit of t)
f: effort delay (a.k.a. stage effort)
g: logical effort
h: electrical effort
p: parasitic delay
t: constant for a fabrication process, t = 3RC
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SOLUTION 1
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SOLUTION 2
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SOLUTION 2
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SOLUTION 3
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SOLUTION 4
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SOLUTION 8
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SOLUTION 8
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