56F8013/56F8011

Data Sheet
Technical Data

56F8000
16-bit Digital Signal Controllers

MC56F8013
Rev. 12
05/2008

freescale.com
 Document Revision History

Version History Description of Change

Rev. 0 Initial release.

Rev. 1 Updates to Part 10, Specifications,

Table 10-1, added maximum clamp current, per pin
Table 10-12, clarified variation over temperature table and graph
Table 10-16, added LIN slave timing

Rev. 2 Added alternate pins to Figure 11-1 and Table 11-1.

Rev. 3 Corrected ADC offering on page 3, clarified Section 1.4.1, corrected bit selects in Timer
Channel 3 Input (TC3_INP) bit 9, Section 6.3.1.7, and simplified notes in Table 10-9.

Rev. 4 Added clarification on sync inputs in Section 1.4.1, added voltage difference specification to
Table 10-1 and Table 10-4, deleted formula for Ambient Operating Temperature in
Table 10-4, also a note for pin group 3 to Table 10-1, corrected Table 8-1, error in Port C
peripheral function configuration, removed text from notes in Table 10-9 that referred to
multiple flash blocks - this family has one flash block. Added RoHs and “pb-free” language to
back cover.

Rev. 5 Updates to Section 10

Table 10-5, corrected max values for ADC Input Current High and Low; corrected typ value
for pull-up disabled Digital Input Current Low (a)
Table 10-6, corrected typ and added max values for Standby > Stop and Powerdown modes
Table 10-7, corrected min value for Low-Voltage Interrupt for 3.3V
Table 10-11, corrected typ and max values and units for PLL lock time
Table 10-12, corrected typ values for Relaxation Oscillator output frequency and variation
over temperature (also increased temp range to 150 degreesC) and added variation over
temperature from 0—105 degreesC
Updated Figure 10-5
Table 10-19, updated max values for Integral Non-Linearity full input signal range, Negative
Differential Non-Linearity, ADC internal clock, Offset Voltage Internal Ref, Gain Error and
Offset Voltage External Ref; updated typ values for Negative Differential Non-Linearity, Offset
Voltage Internal Ref, Gain Error and Offset Voltage External Ref; added new min values and
corrected typ values for Signal-to-noise ratio, Total Harmonic Distortion, Spurious Free
Dynamic Range, Signal-to-noise plus distortion, Effective Number of Bits

Rev. 6 Added details to Section 1. Clarified language in State During Reset column in Table 2-3;
corrected flash data retention temperature in Table 10-4; moved input current high/low
toTable 10-19 and location of footnotes in Table 10-5; reorganized Table 10-19; clarified title
of Figure 10-1.

Rev. 7 Added information on automotive device for 56F8013.

Added information on 56F8011device; edited to indicate differences in 56F8013 and 56F8011
devices.
Updated values for VEI3.3 and VEI2.5 in Table 10-7.
Deleted values for input and output voltage in Table 10-8.
Added row for MC56F8013MFAE in Table 10-12.

56F8013/56F8011 Data Sheet, Rev. 12

2 Freescale Semiconductor
 Document Revision History (Continued)

Version History Description of Change

Rev. 8 • In Table 10-4, added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode
from 400kHz to 200kHz.

Rev. 9 In Table 10-19, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.

Rev. 10 Added the following note to the description of the TMS signal in Table 2-3:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.

Rev. 11 Removed “Preliminary” and made changes throughout the book, including changes in the
following sections:
• Feature additions to Section 1.1.4
• Deleted Section 1.4.1
• Table 2-3
• Added diagram in Section 3.5.1
• Added paragraph to Section 5.3
• Deleted Section 5.5, “Operating Modes”
• Added features to Section 6.2
• Section 6.3.8.1 and Section 6.3.8.2
• Deleted note from Section 6.3.8.3
• Clarifications to Section 6.3 register descriptions
• Removed paragraph from Section 6.4

Rev. 12 • Revised Section 7, Security Features.

• Updated temperature information in Table 10-1 and Table 10-4.
• Fixed miscellaneous errors.

Please see http://www.freescale.com for the most current data sheet revision.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 3
56F8013/56F8011 General Description
Note: Features in italics describe the 56F8011 device.

• Up to 32 MIPS at 32MHz core frequency • One Serial Peripheral Interface (SPI)

• DSP and MCU functionality in a unified, • One 16-bit Quad Timer
C-efficient architecture
• One Inter-Integrated Circuit (I2C) Port
• 56F8013 device offers 16KB Program Flash
56F8011 device offers 12KB Program Flash • Computer Operating Properly (COP)/Watchdog
• 56F8013 device offers 4KB Unified Data/Program • On-Chip Relaxation Oscillator
RAM • Integrated Power-On Reset and Low-Voltage Interrupt
56F8011 device offers 2KB Unified Data/Program Module
RAM • JTAG/Enhanced On-Chip Emulation (OnCE™) for
• One 6-channel PWM module unobtrusive, real-time debugging
• Two 3-channel 12-bit ADCs • Up to 26 GPIO lines
• One Serial Communication Interface (SCI) with LIN • 32-pin LQFP Package
slave functionality

RESET VCAP VDD VSS VDDA VSSA

4 2

JTAG/EOnCE Digital Reg Analog Reg

PWM Port or
7 or Timer Port Low-Voltage
PWM Outputs GPIOD 16-Bit
or GPIOA Supervisor
56800E Core
Data ALU
Program Controller Address Bit
16 x 16 + 36 -> 36-Bit MAC
and Hardware Generation Unit Manipulation
Three 16-bit Input Registers
Looping Unit Unit
Four 36-bit Accumulators

PAB
PDB
CDBR
3 AD0 CDBW
ADC
or Memory R/W Control
GPIOC XDB2
3 AD1 Program Memory
XAB1
8K x 16 Flash
XAB2
6K x 16 Flash System Bus
PAB
Unified Data / Control
Program RAM PDB
4KB CDBR
2KB CDBW

IPBus Bridge (IPBB)

2 Timer or
GPIOB

SPI or I2C SCI System P

COP/ Interrupt O
or Timer or I2C Integration R Clock O
Watchdog Controller S
or GPIOB or GPIOB Module Generator* C
*Includes On-Chip
4 2
Relaxation Oscillator

56F8013/56F8011 Block Diagram

56F8013/56F8011 Data Sheet, Rev. 12

4 Freescale Semiconductor
 56F8013/56F8011 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 6 Part 8: General Purpose Input/Output
1.1. 56F8013/56F8011 Features . . . . . . . . . . . . . 6 (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
1.2. 56F8013/56F8011 Description . . . . . . . . . . . 8 8.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . 86
1.3. Award-Winning Development Environment . 9 8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 86
1.4. Architecture Block Diagram . . . . . . . . . . . . . 9 8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . . 88
1.5. Synchronize ADC with PWM . . . . . . . . . . . . 9
1.6. Multiple Frequency PWM . . . . . . . . . . . . . . . 9 Part 9: Joint Test Action Group (JTAG) . . . 93
1.7. Product Documentation . . . . . . . . . . . . . . . 13 9.1. 56F8013/56F8011 Information . . . . . . . . . . . 93
1.8. Data Sheet Conventions. . . . . . . . . . . . . . . 13
Part 10: Specifications. . . . . . . . . . . . . . . . . 93
Part 2: Signal/Connection Descriptions . . 14 10.1. General Characteristics . . . . . . . . . . . . . . . 93
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.2. DC Electrical Characteristics . . . . . . . . . . . 97
2.2. 56F8013/56F8011 Signal Pins . . . . . . . . . . 18 10.3. AC Electrical Characteristics . . . . . . . . . . . 99
10.4. Flash Memory Characteristics . . . . . . . . . 100
Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . 26 10.5. External Clock Operation Timing . . . . . . . 101
3.1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.6. Phase Locked Loop Timing . . . . . . . . . . . 101
3.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.7. Relaxation Oscillator Timing. . . . . . . . . . . 102
3.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 26 10.8. Reset, Stop, Wait, Mode Select, and
3.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 28 Interrupt Timing . . . . . . . . . . . . . . . . . . . . 103
3.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 29 10.9. Serial Peripheral Interface (SPI) Timing . . 105
10.10. Quad Timer Timing. . . . . . . . . . . . . . . . . 108
Part 4: Memory Map . . . . . . . . . . . . . . . . . . 29 10.11. Serial Communication Interface (SCI)
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.2. Interrupt Vector Table . . . . . . . . . . . . . . . . . 29 10.12. Inter-Integrated Circuit Interface (I2C)
4.3. Program Map . . . . . . . . . . . . . . . . . . . . . . . 31 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.13. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 112
4.5. EOnCE Memory Map . . . . . . . . . . . . . . . . . 34 10.14. Analog-to-Digital Converter (ADC)
4.6. Peripheral Memory Mapped Registers . . . . 35 Parameters . . . . . . . . . . . . . . . . . . . . . . . 114
10.15. Equivalent Circuit for ADC Inputs . . . . . . 115
Part 5: Interrupt Controller (ITCN) . . . . . . . 44 10.16. Power Consumption . . . . . . . . . . . . . . . . 116
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Part 11: Packaging . . . . . . . . . . . . . . . . . . . 118
5.3. Functional Description . . . . . . . . . . . . . . . . 44 11.1. 56F8013/56F8011 Package and Pin-Out
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 47 Information . . . . . . . . . . . . . . . . . . . . . . . . 118
5.5. Register Descriptions . . . . . . . . . . . . . . . . . 48
5.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Part 12: Design Considerations . . . . . . . . 121
12.1. Thermal Design Considerations . . . . . . . . 121
Part 6: System Integration Module (SIM). . 64 12.2. Electrical Design Considerations . . . . . . . 122
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Part 13: Ordering Information . . . . . . . . . . 124
6.3. Register Descriptions . . . . . . . . . . . . . . . . . 66
6.4. Clock Generation Overview . . . . . . . . . . . . 79 Part 14: Appendix. . . . . . . . . . . . . . . . . . . . 124
6.5. Power-Down Modes . . . . . . . . . . . . . . . . . . 79
6.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.7. Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Part 7: Security Features . . . . . . . . . . . . . . 84

7.1. Operation with Security Enabled . . . . . . . . 84
7.2. Flash Access Lock and Unlock Mechanisms 85
7.3. Product Analysis . . . . . . . . . . . . . . . . . . . . . 86

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 5
Part 1 Overview
1.1 56F8013/56F8011 Features
1.1.1 Digital Signal Controller Core
• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging

1.1.2 Differences Between Devices

Table 1-1 outlines the key differences between the 56F8013 and 56F8011 devices.

Table 1-1 Device Differences

Feature 56F8013 56F8011

Program Flash 16KB 12KB

Unified Data/Program RAM 4KB 2KB

1.1.3 Memory
• Dual Harvard architecture permits as many as three simultaneous accesses to program and data
memory
• Flash security and protection that prevent unauthorized users from gaining access to the internal
Flash
• On-chip memory:
— 16KB of Program Flash (56F8013 device)
12KB of Program Flash (56F8011 device)
— 4KB of Unified Data/Program RAM (56F8013 device)
2KB of Unified Data/Program RAM (56F8011 device)
• EEPROM emulation capability using Flash

56F8013/56F8011 Data Sheet, Rev. 12

6 Freescale Semiconductor
 56F8013/56F8011 Features

1.1.4 Peripheral Circuits for 56F8013/56F8011

• One multi-function six-output Pulse Width Modulator (PWM) module
— Up to 96MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and Edge-aligned PWM signal mode
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Each complementary PWM signal pair can output different switching frequency by selecting
PWM generation sources from:
– PWM generator
– External GPIO
– Internal timers
– ADC conversion result of over/under limits:
– When the conversion result is greater than high limit, deactivate PWM signal
– When the conversion result is less than low limit, activate the PWM signal
• Two independent 12-bit Analog-to-Digital Converters (ADCs)
— 2 x 3 channel inputs
— Supports both simultaneous and sequential conversions
— ADC conversions can be synchronized by both PWM and timer modules
— Sampling rate up to 2.67MSPS
— 8-word result buffer registers
— ADC Smart Power Management (Auto-standby, auto-powerdown)
• One 16-bit multi-purpose Quad Timer module (TMR)
— Up to 96MHz operating clock
— Four independent 16-bit counter/timers with cascading capability
— Each timer has capture and compare capability
— Up to 12 operating modes
• One Serial Communication Interface (SCI) with LIN Slave functionality
— Full-duplex or single-wire operation
— Two receiver wake-up methods:
– Idle line
– Address mark
• One Serial Peripheral Interface (SPI)
— Full-duplex operation
— Master and slave modes
— Programmable Length Transactions (2 to 16 bits)
• One Inter-Integrated Circuit (I2C) port
— Operates up to 400kbps
— Supports both master and slave operation
• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 7
 • Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance
• Integrated Power-On Reset and Low-Voltage Interrupt Module
• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals
• Clock Sources:
— On-chip relaxation oscillator
— External clock source
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• JTAG/EOnCE debug programming interface for real-time debugging

1.1.5 Energy Information

• Fabricated in high-density CMOS with 5V tolerance
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power

1.2 56F8013/56F8011 Description

The 56F8013/56F8011 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs).
It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller
with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8013/56F8011 is well-suited for many
applications. The 56F8013/56F8011 includes many peripherals that are especially useful for industrial
control, motion control, home appliances, general purpose inverters, smart sensors, fire and security
systems, switched mode power supply, power management, and medical monitoring applications.
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient, compact
DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F8013/56F8011 supports program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. The 56F8013/56F8011 also offers up to 26
General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F8013 Digital Signal Controller includes 16KB of Program Flash and 4KB of Unified
Data/Program RAM. The 56F8011 Digital Signal Controller includes 12KB of Program Flash and 2KB
of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in
pages. Program Flash page erase size is 512 Bytes (256 Words).
A full set of programmable peripherals—PWM, ADCs, SCI, SPI, I2C, Quad Timer—supports various
applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals
can also be used as General Purpose Input/Outputs (GPIOs).

56F8013/56F8011 Data Sheet, Rev. 12

8 Freescale Semiconductor
 Award-Winning Development Environment

1.3 Award-Winning Development Environment

Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and
development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs
create a complete, scalable tools solution for easy, fast, and efficient development.

1.4 Architecture Block Diagram

The 56F8013/56F8011’s architecture is shown in Figure 1-1, Figure 1-2, and Figure 1-3. Figure 1-1
illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and
the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and
control blocks connected to the IPBus Bridge. Figure 1-3 details how the device’s I/O pins are muxed.
The figures do not show the on-board regulator and power and ground signals. Please see Part 2,
Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals.

1.5 Synchronize ADC with PWM

ADC conversion can be synchronized with PWM module via Quad Timer channel 2 and 3 if needed.
Internally, the PWM synch signal, which is generated at every PWM reload, can be connected to the timer
channel 3 input and the timer channel 2 and 3 outputs are connected to ADC sync inputs. Timer channel
3 output is connected to SYNC0 and Timer channel 2 is connected to SYNC1. The setting is controlled by
TC3_INP bit in the SIM Control Register; see Section 6.3.1.
SYNC0 is the master ADC sync input is used to trigger both ADCA and ADCB in sequence and parallel
mode. SYNC1 is used to trigger ADCB in parallel independent mode, while SYNC0 is used to trigger
ADCA. See 56F801X Peripheral Reference Manual for additional information.

1.6 Multiple Frequency PWM

When both PWM channels of a complementary pair in software control mode and software control bits
are set to 1, each complementary PWM signal pair—PWM 0 and 1; PWM 2 and 3; PWM 4 and 5—can
select a PWM source of one of following sources that enables each PWM pair to output different frequency
PWM signal.
• External GPIO input:
— GPIOB2 input can be used to drive PWM 0 and 1
— GPIOB3 input can be used to drive PWM 2 and 3
— GPIOB4 input can be used to drive PWM 4 and 5
• Quad Timer output:
— Timer0 output can be used to drive PWM 0 and 1

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 9
 — Timer2 output can be used to drive PWM 2 and 3
— Timer3 output can be used to drive PWM 4 and 5
• ADC conversion result:
— Signal of Over/Under limit of ADC sample 0 can be used to drive PWM 0 and 1
— Signal of Over/Under limit of ADC sample 1 can be used to drive PWM 2 and 3
— Signal of Over/Under limit of ADC sample 2 can be used to drive PWM 4 and 5

DSP56800E Core

Program Control Unit

ALU1 ALU2
Address
PC
Generation
LA
Instruction Unit
LA2 Decoder R0
(AGU)
HWS0 R1
HWS1 R2
Interrupt Program
FIRA M01 R3
Unit Memory
OMR N3 R4
SR R5
LC Looping
N
Unit
LC2
SP
FISR

XAB1

XAB2

PAB Data /
Program
PDB RAM
CDBW
CDBR

XDB2

A2 A1 A0
Bit-
B2 B1 B0 IPBUS
Manipulation
C2 C1 C0 Interface
Unit
D2 D1 D0
Y1
Y Data
Enhanced Y0
OnCE™ X0 Arithmetic
Logic Unit
(ALU)
JTAG TAP
MAC and ALU Multi-Bit Shifter

Figure 1-1 56800E Core Block Diagram

56F8013/56F8011 Data Sheet, Rev. 12

10 Freescale Semiconductor
 Multiple Frequency PWM

To/From IPBus Bridge

CLKGEN Interrupt
(ROSC / PLL / Controller
CLKIN)
Low-Voltage Interrupt
8 GPIO A
GPIOAn
POR & LVI
8
GPIOBn GPIO B
System POR
6
GPIOCn GPIO C
RESET / GPIOA7
SIM
4
GPIODn GPIO D
COP Reset

COP

IPBus
(Continues on Figure 1-3)

Figure 1-2 Peripheral Subsystem

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 11
 (Continued from Figure 1-2)
To/From IPBus Bridge
4 PWM0 - 3
PWM0 - 3
2
PWM PWM4, 5 GPIOA0 - 3
Fault1, 2 2 PWM4, 5
Fault0 Fault1, 2
Output Controls Fault3
T2, 3
GPIOA4 - 5
Reload
Pulse 2
3 2 Fault0

from ADC GPIOA6

Fault3

2
T3i T2/3 T1
Timer T1 GPIOB5
T0
T2o, T3o T0

I2C is muxed with both SPI and SCI. CLKO

T2 and T3 are muxed with SPI and PWM.
GPIOB4
2 2
TXD, RXD 2
SCI

GPIOB6 - 7
SDA, SCL 2
I2C

SCLK, SS 2
GPIOB0 - 1
SPI MISO, MOSI 2 T2, 3

3
to PWM
GPIOB2 - 3
3
Sync0, Over/Under ANA0, 1, 3
Sync1 Limits ANA0, 1, 3
ANA2
ANA2 GPIOC0, 1, 3
ADC VREFH, VREFL
ANB2
ANB2
2 VREFH, VREFL
ANB0, 1, 3
GPIOC2, 6

3 ANB0, 1, 3

GPIOC4, 5, 7
IPBus

Figure 1-3 56F8013/56F8011 Peripheral I/O Pin-Out

56F8013/56F8011 Data Sheet, Rev. 12

12 Freescale Semiconductor
 Product Documentation

1.7 Product Documentation

The documents listed in Table 1-2 are required for a complete description and proper design with the 56F8013
or 56F8011. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at:
http://www.freescale.com

Table 1-2 56F8013/56F8011 Chip Documentation

Topic Description Order Number

DSP56800E Detailed description of the 56800E family architecture, DSP56800ERM

Reference Manual 16-bit Digital Signal Controller core processor, and the
instruction set
56F801X Peripheral Detailed description of peripherals of the 56F801X MC56F8000RM
Reference Manual family of devices
56F801X Serial Detailed description of the Serial Bootloader in the 56F801XBLUG
Bootloader User Guide 56F801x family of devices
56F8013/56F8011 Electrical and timing specifications, pin descriptions, MC56F8013
Technical Data Sheet and package descriptions (this document)
Errata Details any chip issues that might be present MC56F8013E
MC56F8011E

1.8 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Examples: Signal/Symbol Logic State Signal State Voltage1

PIN True Asserted VIL/VOL

PIN False Deasserted VIH/VOH

PIN True Asserted VIH/VOH

PIN False Deasserted VIL/VOL

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 13
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8013/56F8011 are organized into functional groups, as detailed in
Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or
signals present on a pin, sorted by pin number.

Table 2-1 Functional Group Pin Allocations

Functional Group Number of Pins

Power (VDD or VDDA) 2

Ground (VSS or VSSA) 3

Supply Capacitors 1

Reset 1

Pulse Width Modulator (PWM) Ports1 7

Serial Peripheral Interface (SPI) Ports2 4

Analog-to-Digital Converter (ADC) Ports 6

Timer Module Ports3 2

Serial Communications Interface (SCI) Ports4 2

JTAG/Enhanced On-Chip Emulation (EOnCE) 4

1. Pins in this section can function as Timer and GPIO.
2. Pins in this section can function as Timer, I2C, and GPIO.
3. Pins can function as PWM and GPIO.
4. Pins in this section can function as I2C and GPIO.

56F8013/56F8011 Data Sheet, Rev. 12

14 Freescale Semiconductor
 Introduction

Table 2-2 56F8013/56F8011 Pins

Peripherals:

LQFP Pin Quad Power &

Signal Name GPIO I2C SCI SPI ADC PWM JTAG Misc.
Pin # Name Timer Ground

1 GPIOB6 GPIOB6, RXD, B6 SDA RXD CLKIN

SDA, CLKIN
2 GPIOB1 GPIOB1, SS, B1 SDA SS
SDA
3 GPIOB7 GPIOB7, TXD, B7 SCL TXD
SCL
4 GPIOB5 GPIOB5, T1, B5 FAULT3 T1
FAULT3
5 ANB0 ANB0, GPIOC4 C4 ANB0
6 ANB1 ANB1, GPIOC5 C5 ANB1
7 ANB2 ANB2, VREFL, C6 ANB2,
GPIOC6 VREFL

8 VDDA VDDA VDDA

9 VSSA VSSA VSSA

10 ANA2 ANA2, VREFH, C2 ANA2,

GPIOC2 VREFH

11 ANA1 ANA1, GPIOC1 C1 ANA1

12 ANA0 ANA0, GPIOC0 C0 ANA0
13 VSS_IO VSS VSS

14 TCK TCK, GPIOD2 D2 TCK

15 RESET RESET, GPIOA7 A7 RESET
16 GPIOB3 GPIOB3, MOSI, B3 MOSI T3
T3
17 GPIOB2 GPIOB2, MISO, B2 MISO T2
T2
18 GPIOA6 GPIOA6, FAULT0 A6 FAULT0
19 GPIOB4 GPIOB4, T0, B4 T0 CLKO
CLKO
20 GPIOA5 GPIOA5, PWM5, A5 PWM5, T3
FAULT2, T3 FAULT2
21 GPIOB0 GPIOB0, SCLK, B0 SCL SCLK
SCL
22 GPIOA4 GPIOA4, PWM4, A4 PWM4, T2
FAULT1, T2 FAULT1
23 GPIOA2 GPIOA2, PWM2 A2 PWM2
24 GPIOA3 GPIOA3, PWM3 A3 PWM3

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 15
 Table 2-2 56F8013/56F8011 Pins (Continued)
Peripherals:

LQFP Pin Quad Power &

Signal Name GPIO I2C SCI SPI ADC PWM JTAG Misc.
Pin # Name Timer Ground

25 VCAP VCAP VCAP

26 VDD VDD VDD

27 VSS_IO VSS VSS

28 GPIOA1 GPIOA1, PWM1 A1 PWM1

29 GPIOA0 GPIOA0, PWM0 A0 PWM0
30 TDI TDI, GPIOD0 D0 TDI
31 TMS TMS, GPIOD3 D3 TMS
32 TDO TDO, GPIOD1 D1 TDO

56F8013/56F8011 Data Sheet, Rev. 12

16 Freescale Semiconductor
 Introduction

VDD
Power
1
VSS
Ground 2
VDDA
Power 1
VSSA
Ground 1
56F8013 /
GPIOB0 (SCLK, SCL)
Other
VCAP
56F8011 1 SPI Port or
Supply 1 GPIOB1 (SS, SDA) I2C Port or
Ports 1 Timer Port
GPIOB2 (MISO, T2) or GPIO
1
GPIOB3 (MOSI, T3)
1
SCI Port or GPIOB6 (RXD, SDA, CLKIN)
1 GPIOA0 - 2 (PWM0 - 2)
I2C Port or 3
GPIO GPIOB7 (TXD, SCL)
GPIOA3 (PWM3)
1 1 PWM Port or
GPIOA4 (PWM4, FAULT1, T2) Timer Port or
1
GPIOA5 (PWM5, FAULT2, T3) GPIO
1
RESET RESET (GPIOA7) GPIOA6 (FAULT0)
1 1

ANA0 - 1 (GPIOC0 - 1)
2
ANA2 (VREFH, GPIOC2)
Timer Port GPIOB4 (T0, CLKO) 1
1 ADC Port or
or GPIO
GPIOB5 (T1, FAULT3) GPIO
1 ANB0 - 1 (GPIOC4 - 5)
2
ANB2 (VREFL, GPIOC6)
1

TCK (GPIOD2)
1
JTAG/ TMS (GPIOD3)
EOnCE Port 1
TDI (GPIOD0)
or GPIO 1
TDO (GPIOD1)
1

Figure 2-1 56F8013/56F8011 Signals Identified by Functional Group

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 17
2.2 56F8013/56F8011 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP

Signal LQFP State During

Type Signal Description
Name Pin No. Reset

VDD 26 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface.

VSS 13 Supply Supply VSS — These pins provide ground for chip logic and I/O drivers.

VSS 27

VDDA 8 Supply Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.

VSSA 9 Supply Supply ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.

VCAP 25 Supply Supply VCAP — Connect a 2.2 μF or greater bypass capacitor between this
pin and VSS_IO, which is required by the internal voltage regulator
for proper chip operation. See Section 10.2.1.

GPIOB6 1 Input/ Input with Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(RXD) Input Receive Data — SCI receive data input.

(SDA1) Input/ Serial Data — This pin serves as the I2C serial data line.
Output

(CLKIN) Input Clock Input — This pin serves as an optional external clock input.

After reset, the default state is GPIOB6. The alternative peripheral

functionality is controlled via the SIM (See Section 6.3.8) and the
CLKMODE bit of the OCCS Oscillator Control Register.

1. This signal is also brought out on the GPIOB1 pin.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

18 Freescale Semiconductor
 56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal LQFP State During

Type Signal Description
Name Pin No. Reset

GPIOB7 3 Input/ Input with Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(TXD) Output Transmit Data — SCI transmit data output or transmit / receive in
single wire operation.

(SCL2) Input/ Serial Clock — This pin serves as the I2C serial clock.
Output
After reset, the default state is GPIOB7. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.

2. This signal is also brought out on the GPIOB0 pin.

RESET 15 Input Input with Reset — This input is a direct hardware reset on the processor.
internal When RESET is asserted low, the chip is initialized and placed in the
pull-up reset state. A Schmitt trigger input is used for noise immunity. The
enabled internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.

(GPIOA7) Input/Open Port A GPIO — This GPIO pin can be individually programmed as
Drain an input or open drain output pin. Note that RESET functionality is
Output disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.

After reset, the default state is RESET.

GPIOB4 19 Input/ Input with Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(T0) Input/ T0 — Timer, Channel 0
Output

(CLKO) Output Clock Output — This is a buffered clock signal. Using the
SIM_CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled (logic 0), CLK_MSTR
(system clock), IPBus clock, or oscillator output. See Section 6.3.7.

After reset, the default state is GPIOB4. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 19
Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal LQFP State During

Type Signal Description
Name Pin No. Reset

GPIOB5 4 Input/ Input with Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(T1) Input/ T1 — Timer, Channel 1
Output

(FAULT3) Input FAULT3 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.

After reset, the default state is GPIOB5. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

TCK 14 Input Input with Test Clock Input — This input pin provides a gated clock to
internal synchronize the test logic and shift serial data to the JTAG/EOnCE
pull-up port. The pin is connected internally to a pull-up resistor. A Schmitt
enabled trigger input is used for noise immunity.

(GPIOD2) Input/ Port D GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is TCK.

TMS 31 Input Input with Test Mode Select Input — This input pin is used to sequence the
internal JTAG TAP controller’s state machine. It is sampled on the rising
pull-up edge of TCK and has an on-chip pull-up resistor.
enabled
(GPIOD3) Input/ Port D GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is TMS.

Note: Always tie the TMS pin to VDD through a 2.2K resistor if this pin
is configured as TMS.

TDI 30 Input Input with Test Data Input — This input pin provides a serial input data stream
internal to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
pull-up and has an on-chip pull-up resistor.
enabled
(GPIOD0) Input/ Port D GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is TDI.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

20 Freescale Semiconductor
 56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal LQFP State During

Type Signal Description
Name Pin No. Reset

TDO 32 Output Output Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.

(GPIOD1) Input/ Port D GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is TDO.

GPIOB0 21 Input/ Input with Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(SCLK) Input/ SPI Serial Clock — In the master mode, this pin serves as an
Output output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.

(SCL3) Input/ Serial Data — This pin serves as the I2C serial clock.
Output
After reset, the default state is GPIOB0. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.

3. This signal is also brought out on the GPIOB7 pin.

GPIOB1 2 Input/ Input with Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(SS) Input SPI Slave Select — SS is used in slave mode to indicate to the SPI
module that the current transfer is to be received.

(SDA4) Input/ Serial Clock — This pin serves as the I2C serial data line.
Output
After reset, the default state is GPIOB1. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.

4. This signal is also brought out on the GPIOB6 pin.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 21
Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal LQFP State During

Type Signal Description
Name Pin No. Reset

GPIOB2 17 Input/ Input with Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(MISO) Input/ SPI Master In/Slave Out — This serial data pin is an input to a
Output master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.

(T25) Input/ T2 — Timer, Channel 2

Output
After reset, the default state is GPIOB2. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.

5. This signal is also brought out on the GPIOA4 pin.

GPIOB3 16 Input/ Input with Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(MOSI) Input/ SPI Master Out/Slave In— This serial data pin is an output from a
Output master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.

(T36) Input/ T3 — Timer, Channel 3

Output
After reset, the default state is GPIOB3. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.

6. This signal is also brought out on the GPIOA5 pin.

GPIOA0 29 Input/ Input with Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(PWM0) Output PWM0 — This is one of the six PWM output pins.

After reset, the default state is GPIOA0.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

22 Freescale Semiconductor
 56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal LQFP State During

Type Signal Description
Name Pin No. Reset

GPIOA1 28 Input/ Input with Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(PWM1) Output PWM1 — This is one of the six PWM output pins.

After reset, the default state is GPIOA1.

GPIOA2 23 Input/ Input with Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(PWM2) Output PWM2 — This is one of the six PWM output pins.

After reset, the default state is GPIOA2.

GPIOA3 24 Input/ Input with Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(PWM3) Output PWM3 — This is one of the six PWM output pins.

After reset, the default state is GPIOA3.

GPIOA4 22 Input/ Input with Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(PWM4) Output PWM4 — This is one of the six PWM output pins.

(FAULT1) Input Fault1 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.

(T27) Input/ T2 — Timer, Channel 2

Output
After reset, the default state is GPIOA4. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.

7. This signal is also brought out on the GPIOB2 pin.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 23
Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal LQFP State During

Type Signal Description
Name Pin No. Reset

GPIOA5 20 Input/ Input with Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(PWM5) Output PWM5 — This is one of the six PWM output pins.

(FAULT2) Input Fault2 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.

(T38) Input/ T3 — Timer, Channel 3

Output
After reset, the default state is GPIOA5. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.

8. This signal is also brought out on the GPIOB3 pin.

GPIOA6 18 Input/ Input with Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pull-up
enabled
(FAULT0) Input Fault0 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.

After reset, the default state is GPIOA6.

ANA0 12 Input Analog ANA0 — Analog input to ADC A, channel 0

Input

(GPIOC0) Input/ Port C GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is ANA0.

ANA1 11 Input Analog ANA1 — Analog input to ADC A, channel 1

Input

(GPIOC1) Input/ Port C GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is ANA1.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

24 Freescale Semiconductor
 56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal LQFP State During

Type Signal Description
Name Pin No. Reset

ANA2 10 Input Analog ANA2 — Analog input to ADC A, channel 2

Input

(VREFH) Input VREFH — Analog reference voltage high

(GPIOC2) Input/ Port C GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is ANA2.

ANB0 5 Input Analog ANB0 — Analog input to ADC B, channel 0

Input

(GPIOC4) Input/ Port C GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is ANB0.

ANB1 6 Input Analog ANB1 — Analog input to ADC B, channel 1

Input

(GPIOC5) Input/ Port C GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is ANB1.

ANB2 7 Input Analog ANB2 — Analog input to ADC B, channel 2

Input

(VREFL) Input VREFL — Analog reference voltage low. This should normally be
connected to a low-noise VSS.

(GPIOC6) Input/ Port C GPIO — This GPIO pin can be individually programmed as
Output an input or output pin.

After reset, the default state is ANB2.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 25
Part 3 OCCS
3.1 Overview
This module provides the system clock, which is used to generate the various chip clocks. This module
also produces the oscillator clock plus the ADC clock and high-speed peripheral clock.
The on-chip clock synthesis module allows product design using an internal relaxation oscillator to run
56F801X family parts at user-selectable frequencies up to 32MHz.

3.2 Features
The On-Chip Clock Synthesis (OCCS) module interfaces to the oscillator and PLL. The OCCS module
features:
• Internal relaxation oscillator
• Ability to power down the internal relaxation oscillator
• Ability to put the internal relaxation oscillator into a standby mode
• 3-bit postscaler provides control for the PLL output
• Ability to power down the internal PLL
• Provides 2X system clock, which operates at twice the system clock, to the System Integration Model (SIM)
that is used to generate the various device clocks
• Provides 3X system clock, which operates at three times the system clock, to PWM and Timer
• Safety shutdown feature is available in the event that the PLL reference clock is lost
• Can be driven from an external clock source
The clock generation module provides the programming interface for both the PLL and internal relaxation
oscillator.

3.3 Operating Modes

In 56F801X family parts, either an internal oscillator or an external frequency source can be used to
provide a reference clock to the SIM.
The 2X system clock source output from the OCCS can be described by one of the following equations:
2X system frequency = oscillator frequency
2X system frequency = (oscillator frequency X 8) / (postscaler)
where:
postscaler = 1, 2, 4, 8, 16, or 32 PLL output divider
The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle
in the system clock output.

56F8013/56F8011 Data Sheet, Rev. 12

26 Freescale Semiconductor
 Operating Modes

The 56F801X family parts’ on-chip clock synthesis module has the following registers:
• Control Register (OCCS_CR)
• Divide-by Register (OCCS_DB)
• Status Register (OCCS_SR)
• Shutdown Register (OCCS_SHUTDN)
• Oscillator Control Register (OCCS_OCTRL)
For more information on these registers, please refer to the 56F801X Peripheral Reference Manual.

3.3.1 External Clock Source

The recommended method of connecting an external clock is illustrated in Figure 3-1. The external clock
source is connected to GPIOB6 / RXD / SDA / CLKIN.

56F8013/56F8011
GPIOB6 / RXD / SDA / CLKIN

External Clock

Figure 3-1 Connecting an External Clock Signal using GPIOB6 / RXD / SDA / CLKIN

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 27
3.4 Block Diagram
Figure 3-2 provides a block diagram which shows how the 56F8013/56F8011 creates its internal clock,
using the relaxation oscillator as an 8MHz clock reference for the PLL.

TRIM[9:0]

Relaxation ROSB
OSC
ROPD
Bus Interface and Bus
Control Interface
GPIOB6 / RXD

MUX PRECS

MSTR_OSC
SYS_CLK_x2
source to the SIM

MUX
FOUT Postscaler (64MHz max)
PLL ÷3 (÷ 1, 2, 4, 8, 16, 32)
X 24

ZSRC

PLLCOD
÷2
FEEDBACK

HS PERF CLK
MUX

Postscaler (96MHz max)

(÷ 1, 2, 4, 8, 16, 32)
FOUT/2

Lock LCK
Detector

Loss of
Loss of Reference Clock Interrupt
Reference
Clock
Detector

Figure 3-2 OCCS Block Diagram with Relaxation Oscillator

56F8013/56F8011 Data Sheet, Rev. 12

28 Freescale Semiconductor
 Pin Descriptions

3.5 Pin Descriptions

3.5.1 External Reference (GPIOB6 / RXD / SDA / CLKIN)
After reset, the internal relaxation oscillator is selected as the clock source for the chip. The user then has
the option of switching to an external clock reference if desired by enabling the PRECS bit in the OCCS
Oscillator Control register.

Part 4 Memory Map

4.1 Introduction
The 56F8013/56F8011 device is a 16-bit motor-control chip based on the 56800E core. It uses a
Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is
used in both spaces and Flash memory is used only in Program space.
This section provides memory maps for:
• Program Address Space, including the Interrupt Vector Table
• Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.

Table 4-1 Chip Memory Configurations

On-Chip Memory 56F8013 56F8011 Use Restrictions

Program Flash 8k x 16 6k x 16 Erase / Program via Flash interface unit and word writes to CDBW
(PFLASH)

Unified RAM (ram) 2k x 16 1k x 16 Usable by both the Program and Data memory spaces

4.2 Interrupt Vector Table

Table 4-2 provides the 56F8013/56F8011’s reset and interrupt priority structure, including on-chip
peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts
lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing
some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.5.6
for the reset value of the VBA.
By default, VBA = 0, and the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 29
 Table 4-2 Interrupt Vector Table Contents1
Vector Priority Vector Base
Peripheral Interrupt Function
Number Level Address +
core P:$00 Reserved for Reset Overlay2
core P:$02 Reserved for COP Reset Overlay
core 2 3 P:$04 Illegal Instruction
core 3 3 P:$06 SW Interrupt 3
core 4 3 P:$08 HW Stack Overflow
core 5 3 P:$0A Misaligned Long Word Access
core 6 1-3 P:$0C EOnCE Step Counter
core 7 1-3 P:$0E EOnCE Breakpoint Unit 0
core 8 1-3 P:$10 EOnCE Trace Buffer
core 9 1-3 P:$12 EOnCE Transmit Register Empty
core 10 1-3 P:$14 EOnCE Receive Register Full
core 11 2 P:$16 SW Interrupt 2
core 12 1 P:$18 SW Interrupt 1
core 13 0 P:$1A SW Interrupt 0
14 Reserved
15 Reserved
PS 16 0-2 P:$20 Power Sense
OCCS 17 0-2 P:$22 PLL Lock, Loss of Clock Reference Interrupt
FM 18 0-2 P:$24 FM Access Error Interrupt
FM 19 0-2 P:$26 FM Command Complete
FM 20 0-2 P:$28 FM Command, data and address Buffers Empty
21 Reserved
GPIOD 22 0-2 P:$2C GPIOD
GPIOC 23 0-2 P:$2E GPIOC
GPIOB 24 0-2 P:$30 GPIOB
GPIOA 25 0-2 P:$32 GPIOA
SPI 26 0-2 P:$34 SPI Receiver Full / Error
SPI 27 0-2 P:$36 SPI Transmitter Empty
SCI 28 0-2 P:$38 SCI Transmitter Empty
SCI 29 0-2 P:$3A SCI Transmitter Idle
SCI 30 0-2 P:$3C SCI Reserved
SCI 31 0-2 P:$3E SCI Receiver Error
SCI 32 0-2 P:$40 SCI Receiver Full
33, 34 Reserved
I2C 35 0-2 P:$46 I2C
Timer 36 0-2 P:$48 Timer Channel 0
Timer 37 0-2 P:$4A Timer Channel 1
(Continues next page)

56F8013/56F8011 Data Sheet, Rev. 12

30 Freescale Semiconductor
 Program Map

Table 4-2 Interrupt Vector Table Contents1 (Continued)

Vector Priority Vector Base
Peripheral Interrupt Function
Number Level Address +
Timer 38 0-2 P:$4C Timer Channel 2
Timer 39 0-2 P:$4E Timer Channel 3
ADC 40 0-2 P:$50 ADCA Conversion Complete
ADC 41 0-2 P:$52 ADCB Conversion Complete
ADC 42 0-2 P:$54 ADC Zero Crossing or Limit Error
PWM 43 0-2 P:$56 Reload PWM
PWM 44 0-2 P:$58 PWM Fault
SWILP 45 -1 P:$5A SW Interrupt Low Priority
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to the reset value, the first two locations of the vector table will overlay the chip reset addresses.

4.3 Program Map

The Program Memory map is shown in Table 4-3.

Table 4-3 Program Memory Map for 56F80131

Begin/End Address Memory Allocation

P: $FF FFFF RESERVED

P: $00 8800

P: $00 87FF On-Chip RAM2

P: $00 8000 4KB

P: $00 7FFF RESERVED

P: $00 2000

P: $00 1FFF Internal Program Flash

P: $00 0000 16KB
Cop Reset Address = $00 0002
Boot Location = $00 0000
1. All addresses are 16-bit Word addresses.
2. This RAM is shared with Data space starting at address X: $00 0000;
see Figure 4-1.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 31
 Table 4-4 Program Memory Map for 56F80111
Begin/End Address Memory Allocation

P: $1F FFFF RESERVED

P: $00 8400

P: $00 83FF On-Chip RAM2

P: $00 8000 2KB

P: $00 7FFF RESERVED

P: $00 2000

P: $00 1FFF Internal Program Flash

P: $00 0800 12KB
Cop Reset Address = $00 0802
Boot Location = $00 0800

P: $00 07FF RESERVED

P: $00 0000
1. All addresses are 16-bit Word addresses.
2. This RAM is shared with Data space starting at address X: $00 0000;
see Figure 4-1.

4.4 Data Map

Table 4-5 Data Memory Map for 56F80131

Begin/End Address Memory Allocation

X:$FF FFFF EOnCE

X:$FF FF00 256 locations allocated

X:$FF FEFF
RESERVED
X:$01 0000

X:$00 FFFF On-Chip Peripherals

X:$00 F000 4096 locations allocated

X:$00 EFFF RESERVED

X:$00 8800

X:$00 EFFF RESERVED

X:$00 0800

X:$00 7FFF RESERVED

X:$00 0040

X:$00 07FF On-Chip Data RAM2

X:$00 0000 4KB
1. All addresses are 16-bit Word addresses.
2. This RAM is shared with Program space starting at P: $00 8000; see
Figure 4-1.

56F8013/56F8011 Data Sheet, Rev. 12

32 Freescale Semiconductor
 Data Map

Table 4-6 Data Memory Map for 56F80111

Begin/End Address Memory Allocation

X:$FF FFFF EOnCE

X:$FF FF00 256 locations allocated

X:$FF FEFF
RESERVED
X:$01 0000

X:$00 FFFF On-Chip Peripherals

X:$00 F000 4096 locations allocated

X:$00 EFFF RESERVED

X:$00 0400

X:$00 03FF On-Chip Data RAM2

X:$00 0000 2KB
1. All addresses are 16-bit Word addresses.
2. This RAM is shared with Program space starting at P: $00 8000; see
Figure 4-1.

Program Data
EOnCE
Reserved
Reserved
RAM
Peripherals
Reserved
Dual Port RAM
Reserved
Flash
RAM

Figure 4-1 Dual Port RAM

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 33
4.5 EOnCE Memory Map
Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.

Table 4-7 EOnCE Memory Map

Address Register Acronym Register Name
X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word
Receive Register Upper Word
X:$FF FFFE OTX / ORX (32 bits) Transmit Register
Receive Register
X:$FF FFFD OTXRXSR Transmit and Receive Status and Control Register
X:$FF FFFC OCLSR Core Lock / Unlock Status Register
X:$FF FFFB - X:$FF FFA1 Reserved
X:$FF FFA0 OCR Control Register
X:$FF FF9F Instruction Step Counter
X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter
X:$FF FF9D OSR Status Register
X:$FF FF9C OBASE Peripheral Base Address Register
X:$FF FF9B OTBCR Trace Buffer Control Register
X:$FF FF9A OTBPR Trace Buffer Pointer Register
X:$FF FF99 Trace Buffer Register Stages
X:$FF FF98 OTB (21 - 24 bits/stage) Trace Buffer Register Stages
X:$FF FF97 Breakpoint Unit Control Register
X:$FF FF96 OBCR (24 bits) Breakpoint Unit Control Register
X:$FF FF95 Breakpoint Unit Address Register 1
X:$FF FF94 OBAR1 (24 bits) Breakpoint Unit Address Register 1
X:$FF FF93 Breakpoint Unit Address Register 2
X:$FF FF92 OBAR2 (32 bits) Breakpoint Unit Address Register 2
X:$FF FF91 Breakpoint Unit Mask Register 2
X:$FF FF90 OBMSK (32 bits) Breakpoint Unit Mask Register 2
X:$FF FF8F Reserved
X:$FF FF8E OBCNTR EOnCE Breakpoint Unit Counter
X:$FF FF8D Reserved
X:$FF FF8C Reserved
X:$FF FF8B Reserved
X:$FF FF8A OESCR External Signal Control Register
X:$FF FF89 - X:$FF FF00 Reserved

56F8013/56F8011 Data Sheet, Rev. 12

34 Freescale Semiconductor
 Peripheral Memory Mapped Registers

4.6 Peripheral Memory Mapped Registers

On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-8 summarizes base addresses for the set of peripherals on the 56F8013/56F8011 device.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.

Table 4-8 Data Memory Peripheral Base Address Map Summary

Peripheral Prefix Base Address Table Number
Timer TMRn X:$00 F000 4-9
PWM PWM X:$00 F040 4-10
ITCN ITCN X:$00 F060 4-11
ADC ADC X:$00 F080 4-12
SCI SCI X:$00 F0B0 4-13
SPI SPI X:$00 F0C0 4-14
I 2C I2C X:$00 F0D0 4-15
COP COP X:$00 F0E0 4-16
CLK, PLL, OSC, TEST OCCS X:$00 F0F0 4-17
GPIO Port A GPIOA X:$00 F100 4-18
GPIO Port B GPIOB X:$00 F110 4-19
GPIO Port C GPIOC X:$00 F120 4-20
GPIO Port D GPIOD X:$00 F130 4-21
SIM SIM X:$00 F140 4-22
Power Supervisor PS X:$00 F160 4-23
FM FM X:$00 F400 4-24

Table 4-9 Quad Timer Registers Address Map

(TMR_BASE = $00 F000)
Register Acronym Address Offset Register Description
TMR0_COMP1 $0 Compare Register 1
TMR0_COMP2 $1 Compare Register 2
TMR0_CAPT $2 Capture Register
TMR0_LOAD $3 Load Register
TMR0_HOLD $4 Hold Register
TMR0_CNTR $5 Counter Register
TMR0_CTRL $6 Control Register
TMR0_SCTRL $7 Status and Control Register
TMR0_CMPLD1 $8 Comparator Load Register 1

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 35
 Table 4-9 Quad Timer Registers Address Map (Continued)
(TMR_BASE = $00 F000)
Register Acronym Address Offset Register Description
TMR0_CMPLD2 $9 Comparator Load Register 2
TMR0_CSCTRL $A Comparator Status and Control Register
Reserved
TMR1_COMP1 $10 Compare Register 1
TMR1_COMP2 $11 Compare Register 2
TMR1_CAPT $12 Capture Register
TMR1_LOAD $13 Load Register
TMR1_HOLD $14 Hold Register
TMR1_CNTR $15 Counter Register
TMR1_CTRL $16 Control Register
TMR1_SCTRL $17 Status and Control Register
TMR1_CMPLD1 $18 Comparator Load Register 1
TMR1_CMPLD2 $19 Comparator Load Register 2
TMR1_CSCTRL $1A Comparator Status and Control Register
Reserved
TMR2_COMP1 $20 Compare Register 1
TMR2_COMP2 $21 Compare Register 2
TMR2_CAPT $22 Capture Register
TMR2_LOAD $23 Load Register
TMR2_HOLD $24 Hold Register
TMR2_CNTR $25 Counter Register
TMR2_CTRL $26 Control Register
TMR2_SCTRL $27 Status and Control Register
TMR2_CMPLD1 $28 Comparator Load Register 1
TMR2_CMPLD2 $29 Comparator Load Register 2
TMR2_CSCTRL $2A Comparator Status and Control Register
Reserved
TMR3_COMP1 $30 Compare Register 1
TMR3_COMP2 $31 Compare Register 2
TMR3_CAPT $32 Capture Register
TMR3_LOAD $33 Load Register
TMR3_HOLD $34 Hold Register
TMR3_CNTR $35 Counter Register
TMR3_CTRL $36 Control Register
TMR3_SCTRL $37 Status and Control Register
TMR3_CMPLD1 $38 Comparator Load Register 1
TMR3_CMPLD2 $39 Comparator Load Register 2
TMR3_CSCTRL $3A Comparator Status and Control Register

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36 Freescale Semiconductor
 Peripheral Memory Mapped Registers

Table 4-10 Pulse Width Modulator Registers Address Map

(PWM_BASE = $00 F040)
Register Acronym Address Offset Register Description
PWM_CTRL $0 Control Register
PWM_FCTRL $1 Fault Control Register
PWM_FLTACK $2 Fault Status Acknowledge Register
PWM_OUT $3 Output Control Register
PWM_CNTR $4 Counter Register
PWM_CMOD $5 Counter Modulo Register
PWM_VAL0 $6 Value Register 0
PWM_VAL1 $7 Value Register 1
PWM_VAL2 $8 Value Register 2
PWM_VAL3 $9 Value Register 3
PWM_VAL4 $A Value Register 4
PWM_VAL5 $B Value Register 5
PWM_DTIM0 $C Dead Time Register 0
PWM_DTIM1 $D Dead Time Register 1
PWM_DMAP1 $E Disable Mapping Register 1
PWM_DMAP2 $F Disable Mapping Register 2
PWM_CNFG $10 Configure Register
PWM_CCTRL $11 Channel Control Register
PWM_PORT $12 Port Register
PWM_ICCTRL $13 Internal Correction Control Register
PWM_SCTRL $14 Source Control Register

Table 4-11 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F060)
Register Acronym Address Offset Register Description
ITCN_IPR0 $0 Interrupt Priority Register 0
ITCN_IPR1 $1 Interrupt Priority Register 1
ITCN_IPR2 $2 Interrupt Priority Register 2
ITCN_IPR3 $3 Interrupt Priority Register 3
ITCN_IPR4 $4 Interrupt Priority Register 4
ITCN_VBA $5 Vector Base Address Register
ITCN_FIM0 $6 Fast Interrupt Match 0 Register
ITCN_FIVAL0 $7 Fast Interrupt Vector Address Low 0 Register
ITCN_FIVAH0 $8 Fast Interrupt Vector Address High 0 Register
ITCN_FIM1 $9 Fast Interrupt Match 1 Register

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Freescale Semiconductor 37
 Table 4-11 Interrupt Control Registers Address Map (Continued)
(ITCN_BASE = $00 F060)
Register Acronym Address Offset Register Description
ITCN_FIVAL1 $A Fast Interrupt Vector Address Low 1 Register
ITCN_FIVAH1 $B Fast Interrupt Vector Address High 1 Register
ITCN_IRQP0 $C IRQ Pending Register 0
ITCN_IRQP1 $D IRQ Pending Register 1
ITCN_IRQP2 $E IRQ Pending Register 2
Reserved
ITCN_ICTRL $12 Interrupt Control Register
Reserved

Table 4-12 Analog-to-Digital Converter Registers Address Map

(ADC_BASE = $00 F080)
Register Acronym Address Offset Register Description
ADC_CTRL1 $0 Control Register 1
ADC_CTRL2 $1 Control Register 2
ADC_ZXCTRL $2 Zero Crossing Control Register
ADC_CLIST 1 $3 Channel List Register 1
ADC_CLIST 2 $4 Channel List Register 2
ADC_SDIS $5 Sample Disable Register
ADC_STAT $6 Status Register
ADC_LIMSTAT $7 Limit Status Register
ADC_ZXSTAT $8 Zero Crossing Status Register
ADC_RSLT0 $9 Result Register 0
ADC_RSLT1 $A Result Register 1
ADC_RSLT2 $B Result Register 2
ADC_RSLT3 $C Result Register 3
ADC_RSLT4 $D Result Register 4
ADC_RSLT5 $E Result Register 5
ADC_RSLT6 $F Result Register 6
ADC_RSLT7 $10 Result Register 7
ADC_LOLIM0 $11 Low Limit Register 0
ADC_LOLIM1 $12 Low Limit Register 1
ADC_LOLIM2 $13 Low Limit Register 2
ADC_LOLIM3 $14 Low Limit Register 3
ADC_LOLIM4 $15 Low Limit Register 4
ADC_LOLIM5 $16 Low Limit Register 5
ADC_LOLIM6 $17 Low Limit Register 6
ADC_LOLIM7 $18 Low Limit Register 7

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38 Freescale Semiconductor
 Peripheral Memory Mapped Registers

Table 4-12 Analog-to-Digital Converter Registers Address Map (Continued)

(ADC_BASE = $00 F080)
Register Acronym Address Offset Register Description
ADC_HILIM0 $19 High Limit Register 0
ADC_HILIM1 $1A High Limit Register 1
ADC_HILIM2 $1B High Limit Register 2
ADC_HILIM3 $1C High Limit Register 3
ADC_HILIM4 $1D High Limit Register 4
ADC_HILIM5 $1E High Limit Register 5
ADC_HILIM6 $1F High Limit Register 6
ADC_HILIM7 $20 High Limit Register 7
ADC_OFFST0 $21 Offset Register 0
ADC_OFFST1 $22 Offset Register 1
ADC_OFFST2 $23 Offset Register 2
ADC_OFFST3 $24 Offset Register 3
ADC_OFFST4 $25 Offset Register 4
ADC_OFFST5 $26 Offset Register 5
ADC_OFFST6 $27 Offset Register 6
ADC_OFFST7 $28 Offset Register 7
ADC_PWR $29 Power Control Register
ADC_VREF $2A Voltage Reference Register
Reserved

Table 4-13 Serial Communication Interface Registers Address Map

(SCI_BASE = $00 F0B0)
Register Acronym Address Offset Register Description
SCI_RATE $0 Baud Rate Register
SCI_CTRL1 $1 Control Register 1
SCI_CTRL2 $2 Control Register 2
SCI_STAT $3 Status Register
SCI_DATA $4 Data Register

Table 4-14 Serial Peripheral Interface Registers Address Map

(SPI_BASE = $00 F0C0)
Register Acronym Address Offset Register Description
SPI_SCTRL $0 Status and Control Register
SPI_DSCTRL $1 Data Size and ControlRegister
SPI_DRCV $2 Data Receive Register
SPI_DXMIT $3 Data Transmit Register

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Freescale Semiconductor 39
 Table 4-15 I2C Registers Address Map
(I2C_BASE = $00 F0D0)
Register Acronym Address Offset Register Description
I2C_ADDR $0 Address Register
I2C_FDIV $1 Frequency Divider Register
I2C_CTRL $2 Control Register
I2C_STAT $3 Status Register
I2C_DATA $4 Data I/O Register
I2C_NFILT $5 Noise Filter Register

Table 4-16 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F0E0)
Register Acronym Address Offset Register Description
COP_CTRL $0 Control Register
COP_TOUT $1 Time-Out Register
COP_CNTR $2 Counter Register

Table 4-17 Clock Generation Module Registers Address Map

(OCCS_BASE = $00 F0F0)
Register Acronym Address Offset Register Description
OCCS_CTRL $0 Control Register
OCCS_DIVBY $1 Divide-By Register
OCCS_STAT $2 Status Register
Reserved
OCCS_SHUTDN $4 Shutdown Register
OCCS_OCTRL $5 Oscillator Control Register

56F8013/56F8011 Data Sheet, Rev. 12

40 Freescale Semiconductor
 Peripheral Memory Mapped Registers

Table 4-18 GPIOA Registers Address Map

(GPIOA_BASE = $00 F100)
Register Acronym Address Offset Register Description
GPIOA_PUPEN $0 Pull-up Enable Register
GPIOA_DATA $1 Data Register
GPIOA_DDIR $2 Data Direction Register
GPIOA_PEREN $3 Peripheral Enable Register
GPIOA_IASSRT $4 Interrupt Assert Register
GPIOA_IEN $5 Interrupt Enable Register
GPIOA_IEPOL $6 Interrupt Edge Polarity Register
GPIOA_IPEND $7 Interrupt Pending Register
GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register
GPIOA_PPOUTM $9 Push-Pull Output Mode Control Register
GPIOA_RDATA $A Raw Data Register
GPIOA_DRIVE $B Drive Strength Control Register

Table 4-19 GPIOB Registers Address Map

(GPIOB_BASE = $00 F110)
Register Acronym Address Offset Register Description
GPIOB_PUPEN $0 Pull-up Enable Register
GPIOB_DATA $1 Data Register
GPIOB_DDIR $2 Data Direction Register
GPIOB_PEREN $3 Peripheral Enable Register
GPIOB_IASSRT $4 Interrupt Assert Register
GPIOB_IEN $5 Interrupt Enable Register
GPIOB_IEPOL $6 Interrupt Edge Polarity Register
GPIOB_IPEND $7 Interrupt Pending Register
GPIOB_IEDGE $8 Interrupt Edge-Sensitive Register
GPIOB_PPOUTM $9 Push-Pull Output Mode Control Register
GPIOB_RDATA $A Raw Data Register
GPIOB_DRIVE $B Drive Strength Control Register

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Freescale Semiconductor 41
 Table 4-20 GPIOC Registers Address Map
(GPIOC_BASE = $00 F120)
Register Acronym Address Offset Register Description
GPIOC_PUPEN $0 Pull-up Enable Register
GPIOC_DATA $1 Data Register
GPIOC_DDIR $2 Data Direction Register
GPIOC_PEREN $3 Peripheral Enable Register
GPIOC_IASSRT $4 Interrupt Assert Register
GPIOC_IEN $5 Interrupt Enable Register
GPIOC_IEPOL $6 Interrupt Edge Polarity Register
GPIOC_IPEND $7 Interrupt Pending Register
GPIOC_IEDGE $8 Interrupt Edge-Sensitive Register
GPIOC_PPOUTM $9 Push-Pull Output Mode Control Register
GPIOC_RDATA $A Raw Data Register
GPIOC_DRIVE $B Drive Strength Control Register

Table 4-21 GPIOD Registers Address Map

(GPIOD_BASE = $00 F130)
Register Acronym Address Offset Register Description
GPIOD_PUPEN $0 Pull-up Enable Register
GPIOD_DATA $1 Data Register
GPIOD_DDIR $2 Data Direction Register
GPIOD_PEREN $3 Peripheral Enable Register
GPIOD_IASSRT $4 Interrupt Assert Register
GPIOD_IEN $5 Interrupt Enable Register
GPIOD_IEPOL $6 Interrupt Edge Polarity Register
GPIOD_IPEND $7 Interrupt Pending Register
GPIOD_IEDGE $8 Interrupt Edge-Sensitive Register
GPIOD_PPOUTM $9 Push-Pull Output Mode Control Register
GPIOD_RDATA $A Raw Data Register
GPIOD_DRIVE $B Drive Strength Control Register

56F8013/56F8011 Data Sheet, Rev. 12

42 Freescale Semiconductor
 Peripheral Memory Mapped Registers

Table 4-22 System Integration Module Registers Address Map

(SIM_BASE = $00 F140)
Register Acronym Address Offset Register Description
SIM_CTRL $0 Control Register
SIM_RSTAT $1 Reset Status Register
SIM_SWC0 $2 Software Control Register 0
SIM_SWC1 $3 Software Control Register 1
SIM_SWC2 $4 Software Control Register 2
SIM_SWC3 $5 Software Control Register 3
SIM_MSHID $6 Most Significant Half JTAG ID
SIM_LSHID $7 Least Significant Half JTAG ID
SIM_PWR $8 Power Control Register
Reserved
SIM_CLKOUT $A Clock Out Select Register
SIM_GPS $B GPIO Peripheral Select Register
SIM_PCE $C Peripheral Clock Enable Register
SIM_IOSAHI $D I/O Short Address Location High Register
SIM_IOSALO $E I/O Short Address Location Low Register

Table 4-23 Power Supervisor Registers Address Map

(PS_BASE = $00 F160)
Register Acronym Address Offset Register Description
PS_CTRL $0 Control Register
PS_STAT $1 Status Register

Table 4-24 Flash Module Registers Address Map

(FM_BASE = $00 F400)
Register Acronym Address Offset Register Description
FM_CLKDIV $0 Clock Divider Register
FM_CNFG $1 Configuration Register
$2 Reserved
FM_SECHI $3 Security High Half Register
FM_SECLO $4 Security Low Half Register
$5 - $9 Reserved
FM_PROT $10 Protection Register
$11 - $12 Reserved
FM_USTAT $13 User Status Register

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 43
 Table 4-24 Flash Module Registers Address Map (Continued)
(FM_BASE = $00 F400)
Register Acronym Address Offset Register Description
FM_CMD $14 Command Register
$15 Reserved
$16 Reserved
$17 Reserved
FM_DATA $18 Data Buffer Register
$19 Reserved
$1A Reserved
FM_OPT1 $1B Optional Data 1 Register
Reserved
FM_TSTSIG $1D Test Array Signature Register

Part 5 Interrupt Controller (ITCN)

5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in
order to service this interrupt.

5.2 Features
The ITCN module design includes these distinctive features:
• Programmable priority levels for each IRQ
• Two programmable Fast Interrupts
• Notification to SIM module to restart clocks out of Wait and Stop modes
• Ability to drive initial address on the address bus after reset
For further information, see Table 4-2, Interrupt Vector Table Contents.

5.3 Functional Description

The Interrupt Controller contains registers that allow each of the 46 interrupt sources to be set to one of
four priority levels (excluding certain interrupts that are of fixed priority). All of the interrupt requests of
a given level are priority encoded to determine the lowest numerical value of the active interrupt requests
for that level. Within a given priority level, number 0 is the highest priority and number 45 is the lowest.
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN can wake
up the core and restart system clocks by signaling a pending IRQ to the System Integration Module (SIM)
to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to

56F8013/56F8011 Data Sheet, Rev. 12

44 Freescale Semiconductor
 Functional Description

entering the Wait or Stop mode.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 45
5.3.1 Normal Interrupt Handling
Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base
Address (VBA) and the vector number to determine the vector address, generating an offset into the vector
table for each interrupt.

5.3.2 Interrupt Nesting

Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following table defines the nesting requirements for each priority level.

Table 5-1 Interrupt Mask Bit Definition

SR[9] SR[8] Exceptions Permitted Exceptions Masked

0 0 Priorities 0, 1, 2, 3 None

0 1 Priorities 1, 2, 3 Priority 0

1 0 Priorities 2, 3 Priorities 0, 1

1 1 Priority 3 Priorities 0, 1, 2

5.3.3 Fast Interrupt Handling

Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
Fast Interrupts before the core does.
A Fast Interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its Fast Interrupt handling.

56F8013/56F8011 Data Sheet, Rev. 12

46 Freescale Semiconductor
 Block Diagram

5.4 Block Diagram

any0
Priority Level 0
Level

46 -> 6
Priority 6
INT0 2 -> 4 Encoder
Decode

INT

VAB
CONTROL
IPIC

any3
Level 3 IACK

SR[9:8]
Priority
Level 46 -> 6
Priority 6 PIC_EN
Encoder

INT45 2 -> 4
Decode

Figure 5-1 Interrupt Controller Block Diagram

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 47
5.5 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN module has 16 registers.

Table 5-2 ITCN Register Summary

(ITCN_BASE = $00 F060)
Register
Base Address + Register Name Section Location
Acronym

IPR0 $0 Interrupt Priority Register 0 5.5.1

IPR1 $1 Interrupt Priority Register 1 5.5.2
IPR2 $2 Interrupt Priority Register 2 5.5.3
IPR3 $3 Interrupt Priority Register 3 5.5.4
IPR4 $4 Interrupt Priority Register 4 5.5.5
VBA $5 Vector Base Address Register 5.5.6
FIM0 $6 Fast Interrupt Match 0 Register 5.5.7
FIVAL0 $7 Fast Interrupt 0 Vector Address Low Register 5.5.8
FIVAH0 $8 Fast Interrupt 0 Vector Address High 0 Register 5.5.9
FIM1 $9 Fast Interrupt Match 1 Register 5.5.10
FIVAL1 $A Fast Interrupt 1 Vector Address Low Register 5.5.11
FIVAH1 $B Fast Interrupt 1 Vector Address High Register 5.5.12
IRQP0 $C IRQ Pending Register 0 5.5.13
IRQP1 $D IRQ Pending Register 1 5.5.14
IRQP2 $E IRQ Pending Register 2 5.5.15
Reserved
ICTRL $12 Interrupt Control Register 5.5.16
Reserved

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48 Freescale Semiconductor
 Register Descriptions

Add. Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset Name
R 0 0 0 0
$0 IPR0 LVI IPL RX_REG IPL TX_REG IPL TRBUF IPL BKPT_U IPL STPCNT IPL
W
R 0 0
$1 IPR1 GPIOB IPL GPIOC IPL GPIOD IPL FM_CBE IPL FM_CC IPL FM_ERR IPL PLL IPL
W
R SCI_RCV SCI_RERR 0 0 SCI_XMIT SPI_XMIT
$2 IPR2 SCI_TIDL IPL SPI_RCV IPL GPIOA IPL
W IPL IPL IPL IPL
R ADCA_CC I2C_ADDR 0 0 0 0
$3 IPR3 TMR_3 IPL TMR_2 IPL TMR_1 IPL TMR_0 IPL
W IPL IPL
R 0 0 0 0 0 0 0 0 ADC_ZC_LE
$4 IPR4 PWM_F IPL PWM_RL IPL ADCB_CC IPL
W IPL
R 0 0
$5 VBA VECTOR_BASE_ADDRESS
W
R 0 0 0 0 0 0 0 0 0 0
$6 FIM0 FAST INTERRUPT 0
W
R
$7 FIVAL0 FAST INTERRUPT 0 VECTOR ADDRESS LOW
W
R 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR
$8 FIVAH0
W ADDRESS HIGH
R 0 0 0 0 0 0 0 0 0 0
$9 FIM1 FAST INTERRUPT 1
W
R
$A FIVAL1 FAST INTERRUPT 1 VECTOR ADDRESS LOW
W
R 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR
$B FIVAH1
W ADDRESS HIGH
R PENDING[16:2] 1
$C IRQP0
W
R PENDING[32:17]
$D IRQP1
W
R 1 1 1 PENDING[45:33]
$E IRQP2
W
Reserved
R INT IPIC VAB INT_ 1 1 1 0 0
$12 ICTRL
W DIS

Reserved

= Reserved

Figure 5-2 ITCN Register Map Summary

5.5.1 Interrupt Priority Register 0 (IPR0)

Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0
LVI IPL RX_REG IPL TX_REG IPL TRBUF IPL BKPT_U IPL STPCNT IPL
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-3 Interrupt Priority Register 0 (IPR0)

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 49
5.5.1.1 LVI IPL—Bits 15–14
This field is used to set the interrupt priority levels for a peripheral IRQ. This IRQ is limited to priorities
0 through 2 and is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.1.2 Reserved—Bits 13–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.1.3 EOnCE Receive Register Full Interrupt Priority Level

(RX_REG IPL)— Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.5.1.4 EOnCE Transmit Register Empty Interrupt Priority Level

(TX_REG IPL)— Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.5.1.5 EOnCE Trace Buffer Interrupt Priority Level

(TRBUF IPL)— Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.5.1.6 EOnCE Breakpoint Unit Interrupt Priority Level

(BKPT_U IPL)— Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

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50 Freescale Semiconductor
 Register Descriptions

It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.5.1.7 EOnCE Step Counter Interrupt Priority Level

(STPCNT IPL)— Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3

5.5.2 Interrupt Priority Register 1 (IPR1)

Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0
GPIOB IPL GPIOC IPL GPIOD IPL FM_CBE IPL FM_CC IPL FM_ERR IPL PLL IPL
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-4 Interrupt Priority Register 1 (IPR1)

5.5.2.1 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.2.2 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

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Freescale Semiconductor 51
5.5.2.3 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.2.4 Reserved—Bits 9–8

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.2.5 FM Command, Data, Address Buffers Empty Interrupt Priority Level

(FM_CBE IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.2.6 FM Command Complete Priority Level (FM_CC IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.2.7 FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

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52 Freescale Semiconductor
 Register Descriptions

5.5.2.8 PLL Loss of Reference or Change in Lock Status Interrupt Priority Level
(PLL IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.3 Interrupt Priority Register 2 (IPR2)

Base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read SCI_RERR 0 0
SCI_RCV IPL SCI_TIDL IPL SCI_XMIT IPL SPI_XMIT IPL SPI_RCV IPL GPIOA IPL
Write IPL

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-5 Interrupt Priority Register 2 (IPR2)

5.5.3.1 SCI Receiver Full Interrupt Priority Level (SCI_RCV IPL)—

Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.3.2 SCI Receiver Error Interrupt Priority Level (SCI_RERR IPL)—

Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.3.3 Reserved—Bits 11–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

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Freescale Semiconductor 53
5.5.3.4 SCI Transmitter Idle Interrupt Priority Level (SCI_TIDL IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.3.5 SCI Transmitter Empty Interrupt Priority Level (SCI_XMIT IPL)—

Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.3.6 SPI Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)—

Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.3.7 SPI Receiver Full Interrupt Priority Level (SPI_RCV IPL)—

Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

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54 Freescale Semiconductor
 Register Descriptions

5.5.3.8 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.4 Interrupt Priority Register 3 (IPR3)

Base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read I2C_ADDR 0 0 0 0
ADCA_CC IPL TMR_3 IPL TMR_2 IPL TMR_1 IPL TMR_0 IPL
Write IPL

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-6 Interrupt Priority Register 3 (IPR3)

5.5.4.1 ADCA Conversion Complete Interrupt Priority Level

(ADCA_CC IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.4.2 Timer Channel 3 Interrupt Priority Level (TMR_3 IPL)—Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.4.3 Timer Channel 2 Interrupt Priority Level (TMR_2 IPL)—Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

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Freescale Semiconductor 55
5.5.4.4 Timer Channel 1 Interrupt Priority Level (TMR_1 IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.4.5 Timer Channel 0 Interrupt Priority Level (TMR_0 IPL)—Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.4.6 I2C Address Detect Interrupt Priority Level (I2C_ADDR IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.4.7 Reserved—Bits 3–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.5 Interrupt Priority Register 4 (IPR4)

Base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 ADC_ZC_LE ADCB_CC
PWM_F IPL PWM_RL IPL
Write IPL IPL

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-7 Interrupt Priority Register 4 (IPR4)

5.5.5.1 Reserved—Bits 15–8

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

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56 Freescale Semiconductor
 Register Descriptions

5.5.5.2 PWM Fault Interrupt Priority Level (PWM_F IPL)—

Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.5.3 Reload PWM Interrupt Priority Level (PWM_RL IPL)—

Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.5.4 ADC Zero Crossing or Limit Error Interrupt Priority Level

(ADC_ZC_LE IPL)— Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

5.5.5.5 ADCB Conversion Complete Interrupt Priority Level

(ADCB_CC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2

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Freescale Semiconductor 57
5.5.6 Vector Base Address Register (VBA)
Base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0
VECTOR_BASE_ADDRESS
Write
RESET1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1. The 56F8013 resets to a value of 0x0000. This corresponds to reset addresses of 0x000000.
The 56F8011 resets to a value of 0x0010. This corresponds to reset addresses of 0x000800.

Figure 5-8 Vector Base Address Register (VBA)

5.5.6.1 Reserved—Bits 15–14

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.6.2 Vector Address Bus (VAB) Bits 13—0

The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits
are determined based on the highest priority interrupt and are then appended onto VBA before presenting
the full VAB to the Core.

5.5.7 Fast Interrupt Match 0 Register (FIM0)

Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0
FAST INTERRUPT 0
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-9 Fast Interrupt Match 0 Register (FIM0)

5.5.7.1 Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.7.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority
level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to
the vector table.

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58 Freescale Semiconductor
 Register Descriptions

5.5.8 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
FAST INTERRUPT 0 VECTOR ADDRESS LOW
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.5.8.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.5.9 Fast Interrupt 0 Vector Address High Register (FIVAH0)

Base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR
Write ADDRESS HIGH

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-11 Fast Interrupt 0 Vector Address High Register (FIVAH0)

5.5.9.1 Reserved—Bits 15–5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.9.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.5.10 Fast Interrupt 1 Match Register (FIM1)

Base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0
FAST INTERRUPT 1
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-12 Fast Interrupt 1 Match Register (FIM1)

5.5.10.1 Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.10.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 59
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority
level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to
the vector table.

5.5.11 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Base + $A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
FAST INTERRUPT 1 VECTOR ADDRESS LOW
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

5.5.11.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.5.12 Fast Interrupt 1 Vector Address High (FIVAH1)

Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR
Write ADDRESS HIGH

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 5-14 Fast Interrupt 1 Vector Address High Register (FIVAH1)

5.5.12.1 Reserved—Bits 15–5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.12.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.5.13 IRQ Pending Register 0 (IRQP0)

Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read PENDING[16:2] 1
Write
RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 5-15 IRQ Pending Register 0 (IRQP0)

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60 Freescale Semiconductor
 Register Descriptions

5.5.13.1 IRQ Pending (PENDING)—Bits 15–1

This register combines with IRQP1 and IRQP2 to represent the pending IRQs for interrupt vector numbers
2 through 45.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number

5.5.13.2 Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.5.14 IRQ Pending Register 1 (IRQP1)

Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read PENDING[32:17]
Write
RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 5-16 IRQ Pending Register 1 (IRQP1)

5.5.14.1 IRQ Pending (PENDING)—Bits 32–17

This register combines with IRQP0 and IRQP2 to represent the pending IRQs for interrupt vector numbers
2 through 45.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number

5.5.15 IRQ Pending Register 2 (IRQP2)

Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 1 1 1 PENDING[45:33]
Write
RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 5-17 IRQ Pending Register 2 (IRQP2)

5.5.15.1 IRQ Pending (PENDING)—Bits 45–33

This register combines with IRQP0 and IRQP1 to represent the pending IRQs for interrupt vector numbers
2 through 45.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number

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Freescale Semiconductor 61
5.5.16 Interrupt Control Register (ICTRL)
$Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read INT IPIC VAB INT_ 1 1 1 0 0
Write DIS

RESET 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0

Figure 5-18 Interrupt Control Register (ICTRL)

5.5.16.1 Interrupt (INT)—Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.
• 0 = No interrupt is being sent to the 56800E core
• 1 = An interrupt is being sent to the 56800E core

5.5.16.2 Interrupt Priority Level (IPIC)—Bits 14–13

These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being
sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service
routine.
Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
• 00 = Required nested exception priority levels are 0, 1, 2, or 3
• 01 = Required nested exception priority levels are 1, 2, or 3
• 10 = Required nested exception priority levels are 2 or 3
• 11 = Required nested exception priority level is 3

Table 5-3 Interrupt Priority Encoding

Current Interrupt Required Nested
IPIC_VALUE[1:0]
Priority Level Exception Priority

00 No interrupt or SWILP Priorities 0, 1, 2, 3

01 Priority 0 Priorities 1, 2, 3
10 Priority 1 Priorities 2, 3
11 Priority 2 or 3 Priority 3

5.5.16.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6

This read-only field shows the vector number (VAB[6:0]) used at the time the last IRQ was taken. In the
case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when
the 56800E core jumps to a new interrupt service routine.

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62 Freescale Semiconductor
 Resets

Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.

5.5.16.4 Interrupt Disable (INT_DIS)—Bit 5

This bit allows all interrupts to be disabled.
• 0 = Normal operation (default)
• 1 = All interrupts disabled

5.5.16.5 Reserved—Bits 4–2

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.5.16.6 Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6 Resets
5.6.1 General

Table 5-4 Reset Summary

Reset Priority Source Characteristics

Core Reset RST Core reset from the SIM

5.6.2 Description of Reset Operation

5.6.2.1 Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in Figure 5-19.

RES

CLK

VAB RESET_VECTOR_ADR

PAB READ_ADR

Figure 5-19 Reset Interface

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Freescale Semiconductor 63
5.6.3 ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
• Illegal Instruction
• SW Interrupt 3
• HW Stack Overflow
• Misaligned Long Word Access
• SW Interrupt 2
• SW Interrupt 1
• SW Interrupt 0
• SW Interrupt LP
These interrupts are enabled at their fixed priority levels.

Part 6 System Integration Module (SIM)

6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The System Integration Module
is responsible for the following functions:
• Reset sequencing
• Clock control & distribution
• Stop/Wait control
• System status registers
• Registers for software access to the JTAG ID of the chip
• Test registers
• Power control
• I/O pad multiplexing
These are discussed in more detail in the sections that follow.

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64 Freescale Semiconductor
 Features

6.2 Features
The SIM has the following features:
• Reset sequencing
• Core and peripheral clock control and distribution
• Stop/Wait mode control
• System status
• Power control
• Control I/O multiplexing
• System bus clocks with pipeline hold-off support
• System clocks for non-pipelined interfaces
• Peripheral clocks for Quad Timer and PWM with high-speed (3X) option
• Power-saving clock gating for peripherals
• Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, and peripheral clock
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
• Controls, with write protection, the enable/disable of 56800E core WAIT and STOP instructions
• Controls, with write protection, the enable/disable of Large Regulator Standby mode
• Controls to route functional signals to selected peripherals and I/O pads
• Controls deassertion sequence of internal resets
• Software-initiated reset
• Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
• Timer channel Stop mode clocking controls
• SCI Stop mode clocking control to support LIN Sleep mode stop recovery
• Short addressing location control
• Registers for containing the JTAG ID of the chip
• Controls output to CLKO pin

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Freescale Semiconductor 65
6.3 Register Descriptions

Table 6-1 SIM Registers (SIM_BASE = $00 F140)

Address Offset Address Acronym Register Name Section Location

Base + $0 SIM_CTRL Control Register 6.3.1

Base + $1 SIM_RSTAT Reset Status Register 6.3.2
Base + $2 SIM_SWC0 Software Control Register 0 6.3.3
Base + $3 SIM_SWC1 Software Control Register 1 6.3.3
Base + $4 SIM_SWC2 Software Control Register 2 6.3.3
Base + $5 SIM_SWC3 Software Control Register 3 6.3.3
Base + $6 SIM_MSHID Most Significant Half of JTAG ID 6.3.4
Base + $7 SIM_LSHID Least Significant Half of JTAG ID 6.3.5
Base + $8 SIM_PWR Power Control Register 6.3.6
Reserved
Base + $A SIM_CLKOUT CLKO Select Register 6.3.7
Base + $B SIM_GPS GPIO Peripheral Select Register 6.3.8
Base + $C SIM_PCE Peripheral Clock Enable Register 6.3.9
Base + $D SIM_IOSAHI I/O Short Address Location High Register 6.3.10
Base + $E SIM_IOSALO I/O Short Address Location Low Register 6.3.10

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66 Freescale Semiconductor
 Register Descriptions

Add. Address
Offset Acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIM_ R TC3_ TC2_ TC1_ TC0_ SCI_ 0 TC3_ 0 0 0 ONCE SW STOP_ WAIT_
$0
CTRL W SD SD SD SD SD INP EBL0 RST DISABLE DISABLE

SIM_ R 0 0 0 0 0 0 0 0 0 0 0 0
$1 SWR COPR EXTR POR
RSTAT W
R
$2 SIM_SWC0 Software Control Data 0
W
R
$3 SIM_SWC1 Software Control Data 1
W
R
$4 SIM_SWC2 Software Control Data 2
W
R
$5 SIM_SWC3 Software Control Data 3
W
R 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0
$6 SIM_MSHID
W
R 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1
$7 SIM_LSHID
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$8 SIM_PWR LRSTDBY
W
Reserved
SIM_ R 0 0 0 0 0 0 CLK
$A PWM3 PWM2 PWM1 PWM0 CLKOSEL
CLKOUT W DIS
R 0 0 CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_
$B SIM_GPS TCR PCR CFG_A5 CFG_A4
W B7 B6 B5 B4 B3 B2 B1 B0
R 0 0 0 0 0 0 0 0 0 0
$C SIM_PCE I2C ADC TMR SCI SPI PWM
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$D SIM_IOSAHI ISAL[23:22]
W
R
$E SIM_IOSALO ISAL[21:6]
W

0 = Read as 0 1 = Read as 1
= Reserved = Reserved

Figure 6-1 SIM Register Map Summary

6.3.1 SIM Control Register (SIM_CTRL)

Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read TC3_ TC2_ TC1_ TC0_ SCI_ 0 TC3_ 0 0 0 ONCE SW STOP_ WAIT_
Write SD SD SD SD SD INP EBL RST DISABLE DISABLE

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 6-2 SIM Control Register (SIM_CTRL)

6.3.1.1 Timer Channel 3 Stop Disable (TC3_SD)—Bit 15

This bit enables the operation of the Timer Channel 3 peripheral clock in Stop mode.
• 0 = Timer Channel 3 disabled in Stop mode

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 67
 • 1 = Timer Channel 3 enabled in Stop mode

6.3.1.2 Timer Channel 2 Stop Disable (TC2_SD)—Bit 14

This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode.
• 0 = Timer Channel 2 disabled in Stop mode
• 1 = Timer Channel 2 enabled in Stop mode

6.3.1.3 Timer Channel 1 Stop Disable (TC1_SD)—Bit 13

This bit enables the operation of the Timer Channel 1 peripheral clock in Stop mode.
• 0 = Timer Channel 1 disabled in Stop mode
• 1 = Timer Channel 1 enabled in Stop mode

6.3.1.4 Timer Channel 0 Stop Disable (TC0_SD)—Bit 12

This bit enables the operation of the Timer Channel 0 peripheral clock in Stop mode.
• 0 = Timer Channel 0 disabled in Stop mode
• 1 = Timer Channel 0 enabled in Stop mode

6.3.1.5 SCI Stop Disable (SCI_SD)—Bit 11

This bit enables the operation of the SCI peripheral clock in Stop mode. This is recommended for use in
LIN mode so that the SCI can generate interrupts and recover from Stop mode while the LIN interface is
in Sleep mode and using Stop mode to reduce power consumption.
• 0 = SCI disabled in Stop mode
• 1 = SCI enabled in Stop mode

6.3.1.6 Reserved—Bit 10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.1.7 Timer Channel 3 Input (TC3_INP)—Bit 9

This bit selects the input of Timer Channel 3 to be from the PWM Sync signal or GPIO pin.
• 1 = Timer Channel 3 Input from PWM sync signal
• 0 = Timer Channel 3 Input controlled by SIM_GPS register CFG_B3 and CFG_A5 fields

6.3.1.8 Reserved—Bits 8–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.1.9 OnCE Enable (ONCEEBL)—Bit 5

• 0 = OnCE clock to 56800E core enabled when core TAP is enabled
• 1 = OnCE clock to 56800E core is always enabled

6.3.1.10 Software Reset (SWRST)—Bit 4

Writing 1 to this field will cause the part to reset.

56F8013/56F8011 Data Sheet, Rev. 12

68 Freescale Semiconductor
 Register Descriptions

6.3.1.11 Stop Disable (STOP_DISABLE[1:0])—Bits 3–2

• 00 = Stop mode will be entered when the 56800E core executes a STOP instruction
• 01 = The 56800E STOP instruction will not cause entry into Stop mode
• 10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
STOP_DISABLE field is write-protected until the next reset
• 11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
write-protected until the next reset

6.3.1.12 Wait Disable (WAIT_DISABLE[1:0])—Bits 1–0

• 00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
• 01 = The 56800E WAIT instruction will not cause entry into Wait mode
• 10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
WAIT_DISABLE field is write-protected until the next reset
• 11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
write-protected until the next reset

6.3.2 SIM Reset Status Register (SIM_RSTAT)

This register is updated upon any system reset and indicates the cause of the most recent reset. It also
controls whether the COP reset vector or regular reset vector in the vector table is used. This register is
asynchronously reset during Power-On Reset (see power supervisor module) and subsequently is
synchronously updated based on the level of the external reset, software reset, or cop reset inputs. Only
one source will ever be indicated. In the event that multiple reset sources assert simultaneously, the
highest-precedence source will be indicated. The precedence from highest to lowest is POR, EXTR,
COPR, and SWR. While POR is always set during a Power-On Reset, EXTR will become set if the
external reset pin is asserted or remains asserted after the Power-On Reset (POR) has deasserted.

Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0 0 0
SWR COPR EXTR POR
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0

Figure 6-3 SIM Reset Status Register (SIM_RSTAT)

6.3.2.1 Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as zero and cannot be modified by writing.

6.3.2.2 Software Reset (SWR)—Bit 5

When set, this bit indicates that the previous system reset occurred as a result of a software reset (written
1 to SWRST bit in the SIM_CTRL register). It will not be set if a COP, external, or POR reset also
occurred.

6.3.2.3 COP Reset (COPR)—Bit 4

When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 69
(COP) timer. It will not be set if an external or POR reset also occurred. If COPR is set as code starts
executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.

6.3.2.4 External Reset (EXTR)—Bit 3

When set, this bit indicates that the previous system reset was caused by an external reset. It will only be
set if the external reset pin was asserted or remained asserted after the Power-On Reset deasserted.

6.3.2.5 Power-On Reset (POR)—Bit 2

This bit is set during a Power-On Reset.

6.3.2.6 Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1,

SIM_SWC2, and SIM_SWC3)
Only SIM_SWC0 is shown in this section. SIM_SWC1, SIM_SWC2, and SIM_SWC3 are identical in
functionality.

Base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
Software Control Data 0
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 6-4 SIM Software Control Register 0 (SIM_SWC0)

6.3.3.1 Software Control Data 0 (FIELD)—Bits 15–0

This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).

6.3.4 Most Significant Half of JTAG ID (SIM_MSHID)

This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F2.

Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0
Write
RESET 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0

Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)

56F8013/56F8011 Data Sheet, Rev. 12

70 Freescale Semiconductor
 Register Descriptions

6.3.5 Least Significant Half of JTAG ID (SIM_LSHID)

This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$401D.

Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1
Write
RESET 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1

Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)

6.3.6 SIM Power Control Register (SIM_PWR)

This register controls the Standby mode of the large regulator. The large regulator derives the core digital
logic power supply from the IO power supply. In some circumstances, the large regulator may be put in a
reduced-power Standby mode without interfering with part operation. Refer to the overview of
power-down modes and the overview of clock generation for more information on the use of large
regulator standby.

Base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LRSTDBY
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 6-7 SIM Power Control Register (SIM_PWR)

6.3.6.1 Reserved—Bits 15–2

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.6.2 Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0

This bit controls the pull-up resistors on the IRQA pin.
• 00 = Large regulator is in Normal mode
• 01 = Large regulator is in Standby (reduced-power) mode
• 10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset
• 11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset
NOTE:
Standby mode can be used when device operates below 200KHz with PLL shut
down.

6.3.7 CLKO Select Register (SIM_CLKOUT)

The CLKO select register can be used to multiplex out selected clocks generated inside the clock

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 71
generation and SIM modules. All functionality is for test purposes only and is subject to
unspecified latencies. Glitches may be produced when the clock is enabled or switched.
The lower four bits of the GPIO A register can function as GPIO, PWM, or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOA_PEREN. If GPIOA[3:0] are
programmed to operate as peripheral outputs, then the choice between PWM and additional clock outputs
is done here in the CLKOUT. The default state is for the peripheral function of GPIOA[3:0] to be
programmed as PWM. This can be changed by altering PWM3 through PWM0.

Base + $A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 CLK
PWM3 PWM2 PWM1 PWM0 CLKOSEL
Write DIS

RESET 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

Figure 6-8 CLKO Select Register (SIM_CLKOUT)

6.3.7.1 Reserved—Bits 15–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.7.2 PWM3—Bit 9
• 0 = Peripheral output function of GPIOA[3] is defined to be PWM3
• 1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock

6.3.7.3 PWM2—Bit 8
• 0 = Peripheral output function of GPIOA[2] is defined to be PWM2
• 1 = Peripheral output function of GPIOA[2] is defined to be the system clock

6.3.7.4 PWM1—Bit 7
• 0 = Peripheral output function of GPIOA[1] is defined to be PWM1
• 1 = Peripheral output function of GPIOA[1] is defined to be two times the rate of the system clock

6.3.7.5 PWM0—Bit 6
• 0 = Peripheral output function of GPIOA[0] is defined to be PWM0
• 1 = Peripheral output function of GPIOA[0] is defined to be three times the rate of the system clock

6.3.7.6 Clockout Disable (CLKDIS)—Bit 5

• 0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
• 1 = CLKOUT is 0

6.3.7.7 Clockout Select (CLKOSEL)—Bits 4–0

Selects clock to be muxed out on the CLKO pin.
• 00000 = Reserved for factory test—Continuous system clock

56F8013/56F8011 Data Sheet, Rev. 12

72 Freescale Semiconductor
 Register Descriptions

• 01001 = Reserved for factory test—OCCS MSTR OSC clock

• 01011 = Reserved for factory test—ADC clock
• 01100 = Reserved for factory test—JTAG TCLK
• 01101 = Reserved for factory test—Continuous peripheral clock
• 01110 = Reserved for factory test—Continuous inverted peripheral clock
• 01111 = Reserved for factory test—Continuous high-speed peripheral clock

6.3.8 SIM GPIO Peripheral Select Register (SIM_GPS)

All of the peripheral pins on the 56F8013/56F8011 share their Input/Output (I/O) with GPIO ports. To
select peripheral or GPIO control, program corresponding bit in the GPIOx_PEREN register in GPIO
module. See the 56F801x Peripheral Reference Manual for detail. In some cases, there are two possible
peripherals as well as the GPIO functionality available for control of the I/O. In these cases, the SIM_GPS
register is used to determine which peripheral has control when the corresponding I/O pin is configured in
peripheral mode.
As shown in Figure 6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which
pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when
PEREN = 1.

GPIOB_PEREN Register

GPIO Controlled 0
I/O Pad Control

1
SIM_GPS Register

Quad Timer Controlled 0

SCI Controlled 1

Figure 6-9 Overall Control of Pads Using SIM_GPS Control

Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_
TCR PCR CFG_A5 CFG_A4
Write B7 B6 B5 B4 B3 B2 B1 B0

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 73
6.3.8.1 Quad Timer Clock Rate (TCR)—Bit 15
This bit selects the clock speed for the Quad Timermodule.
• 0 = Quad Timer module clock rate equals system clock rate, to a maximum 32MHz (default)
• 1 = Quad Timer module clock rate equals three times system clock rate, to a maximum 96MHz
Note: This bit should only be changed while the TMR module’s clock is disabled. See Section 6.3.9.
Note: High-speed clocking is only available when the PLL is being used.
Note: If the PWM sync signal pulse is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section
6.3.1.7), then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2.

6.3.8.2 PWM Clock Rate (PCR)—Bit 14

This bit selects the clock speed for the PWM module.
• 0 = PWM module clock rate equals system clock rate, to a maximum 32MHz (default)
• 1 = PWM module clock rate equals three times system clock rate, to a maximum 96MHz
Note: This bit should only be changed while the PWM module’s clock is disabled. See Section 6.3.9.
Note: High-speed clocking is only available when the PLL is being used.
Note: If the PWM sync signal is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section 6.3.1.7),
then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2.

Table 6-2 Allowable Quad Timer and PWM Clock Rates

when Using PWM Reload Pulse
Quad Timer

Clock Speed 1X 3X

1X OK OK
PWM
3X NO OK

6.3.8.3 Reserved—Bits 13–12

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.8.4 Configure GPIOB7 (CFG_B7)—Bit 11

This bit selects the alternate function for GPIOB7.
• 0 = TXD — SCI Transmit Data (default)
• 1 = SCL — I2C Serial Clock

6.3.8.5 Configure GPIOB6 (CFG_B6)—Bit 10

This bit selects the alternate function for GPIOB6.

56F8013/56F8011 Data Sheet, Rev. 12

74 Freescale Semiconductor
 Register Descriptions

• 0 = RXD — SCI Receive Data(default)

• 1 = SDA — I2C Serial Data
Note: The PRECS bit in the OCCS Oscillator Control register can enable this pin as the
source clock to the chip. In this mode, make sure that no on-chip peripheral (including the
GPIO) is driving this pin.

6.3.8.6 Configure GPIOB5 (CFG_B5)—Bit 9

This bit selects the alternate function for GPIOB5.
• 0 = T1 — Timer Channel 1 input/output(default)
• 1 = FAULT3 — PWM FAULT3 Input

6.3.8.7 Configure GPIOB4 (CFG_B4)—Bit 8

This bit selects the alternate function for GPIOB4.
• 0 = T0 — Timer Channel 0 input/output (default)
• 1 = CLKO — Clock Output

6.3.8.8 Configure GPIOB3 (CFG_B3)—Bit 7

This bit selects the alternate function for GPIOB3.
• 0 = MOSI — SPI Master Out/Slave In (default)
• 1 = T3 — Time Channel 3 input/output

6.3.8.9 Configure GPIOB2 (CFG_B2)—Bit 6

This bit selects the alternate function for GPIOB2.
• 0 = MISO — SPI Master In/Slave Out (default)
• 1 = T2 — Timer Channel 2 input/output

6.3.8.10 Configure GPIOB1 (CFG_B1)—Bit 5

This bit selects the alternate function for GPIOB1.
• 0 = SS — SPI Slave Select(default)
• 1 = SDA— I2C Serial Data

6.3.8.11 Configure GPIOB0 (CFG_B0)—Bit 4

This bit selects the alternate function for GPIOB0.
• 0 = SCLK — SPI Serial Clock (default)
• 1 = SCL — I2C Serial Clock

6.3.8.12 Configure GPIOA5[1:0] (CFG_A5)—Bits 3–2

These bits select the alternate function for GPIOA5.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 75
 • 00 = PWM5 — PWM5 Output (default)
• 01 = PWM5 — PWM5 Output
• 10 = FAULT2 — PWM FAULT2 Input
• 11 = T3 — Timer Channel 3 input/output

6.3.8.13 Configure GPIOA4[1:0] (CFG_A4)—Bits 1–0

These bits select the alternate function for GPIOA4.
• 00 = PWM4 — PWM4 Output (default)
• 01 = PWM4 — PWM4 Output
• 10 = FAULT1— PWM FAULT1 Input
• 11 = T2 — Timer Channel 2 input/output
NOTE:
Take care when programming the following CFG_* signals so as not to connect
two different I/O pins to the same peripheral input. For example, do not set
CFG_B7 to select SCL and also set CFG_B0 to select SCL. If this occurs for an
output signal, then the signal will be routed to two I/O pins. For input signals, the
values on the two I/O pins will be ORed together before reaching the peripheral.

6.3.9 Peripheral Clock Enable Register (SIM_PCE)

The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip. The
corresponding peripheral should itself be disabled while its clock is shut off.

Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0
I2C ADC TMR SCI SPI PWM
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 6-11 Peripheral Clock Enable Register (SIM_PCE)

6.3.9.1 I2C Clock Enable (I2C)—Bit 15

• 0 = The clock is not provided to the I2C module(the 12C module is disabled)
• 1 = Clocks to the I2C module are enabled

6.3.9.2 Reserved—Bit 14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.3 Analog-to-Digital Converter IPBus Clock Enable (ADC)—Bit 13

• 0 = The clock is not provided to the ADC module (the ADC module is disabled)
• 1 = Clocks to the ADC module are enabled

56F8013/56F8011 Data Sheet, Rev. 12

76 Freescale Semiconductor
 Register Descriptions

6.3.9.4 Reserved—Bits 12–7

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.5 Timer Clock Enable (TMR)—Bit 6

• 0 = The clock is not provided to the Quad Timer module(the Quad Timer module is disabled)
• 1 = Clocks to the Quad Timer module are enabled

6.3.9.6 Reserved—Bit 5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.7 SCI Clock Enable (SCI)—Bit 4

• 0 = The clock is not provided to the SCI module (the SCI module is disabled)
• 1 = Clocks to the SCI module are enabled

6.3.9.8 Reserved—Bit 3
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.9 SPI Clock Enable (SPI)—Bit 2

• 0 = The clock is not provided to the SPI module (the SPI module is disabled)
• 1 = Clocks to the SPI module are enabled

6.3.9.10 Reserved—Bit 1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.11 PWM Clock Enable (PWM)—Bit 0

• 0 = The clock is not provided to the PWM module (the PWM module is disabled)
• 1 = Clocks to the PWM module are enabled

6.3.10 I/O Short Address Location Register (SIM_IOSAHI and

SIM_IOSALO)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in Figure 6-12.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 77
 “Hard Coded” Address Portion Instruction Portion

6 Bits from I/O Short Address Mode Instruction

16 Bits from SIM_IOSALO Register

2 bits from SIM_IOSAHI Register

Full 24-Bit for Short I/O Address

Figure 6-12 I/O Short Address Determination

With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note: The default value of this register set points to the EOnCE registers.
Note: The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.

Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ISAL[23:22]
Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Figure 6-13 I/O Short Address Location High Register (SIM_IOSAHI)

6.3.10.1 Reserved—Bits 15—2

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.10.2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0

This field represents the upper two address bits of the “hard coded” I/O short address.

56F8013/56F8011 Data Sheet, Rev. 12

78 Freescale Semiconductor
 Clock Generation Overview

Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
ISAL[21:6]
Write
RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO)

6.3.10.3 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.4 Clock Generation Overview

The SIM uses master clocks, 2X system clock at a maximum of 64MHz, from the OCCS module to
produce the peripheral and system (core and memory) clocks at a maximum of 32MHz. It divides the
master clock by two and gates it with appropriate power mode and clock gating controls. The high speed
peripheral clock from OCCS operates at three times the system clock for PWM and Quad Timer module
at a maximum of 96MHz.
The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either
an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC). The
relaxation oscillator can be operated at full speed (8MHz), standby speed (200kHz), or powered down. An
8MHz clock can be multiplied to 192 MHz using the PLL and postscaled to provide a variety of high speed
clock rates. Either the postscaled PLL output or input clock of PLL signal can be selected to produce the
master clocks to the SIM. When the PLL is not selected, the high speed peripheral clock is disabled and
the 2X system clock is input clock from either internal relaxation oscillator or external clock source.
In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to provide flexible
control of clocking and power utilization. The SIM’s clock enable controls can be used to disable
individual clocks when not needed. The clock rate controls enable the high speed clocking option for the
Timer channels and PWM but require the PLL to be on and selected. Refer to the 56F801X Peripheral
User Manual for further details.

6.5 Power-Down Modes

The 56F8013/56F8011 operates in one of five Power-Down modes, as shown in Table 6-3.

Table 6-3 Clock Operation in Power-Down Modes

Mode Core Clocks Peripheral Clocks Description
Run Core and memory Peripheral clocks Device is fully functional
clocks disabled enabled

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 79
 Table 6-3 Clock Operation in Power-Down Modes (Continued)
Mode Core Clocks Peripheral Clocks Description
Wait Core and memory Peripheral clocks Core executes WAIT instruction to enter this
clocks disabled enabled mode.
Typically used for power-conscious applications.
Possible recoveries from Wait mode to Run
mode are:
1. Any interrupt
2. Executing a Debug mode entry command
during the 56800E core JTAG interface
2. Any reset (POR, external, software, COP)
Stop Master clock generation in the OCCS Core executes STOP instruction to enter this
remains operational, but the SIM disables mode. Possible recoveries from Stop mode to
the generation of system and peripheral Run mode are:
clocks. 1. Interrupt from Timer channels that have been
configured to operate in Stop mode (TCx_SD)
2. Interrupt for SCI configured to operate in Stop
mode (SCI_SD)
3. Low-voltage interrupt
4. Executing a Debug mode entry command
using the 56800E core JTAG interface
5. Any reset (POR, external, software, COP)
Standby The OCCS generates the 2X system clock The user configures the OCCS and SIM to select
at a reduced frequency (200kHz). The PLL the relaxation oscillator clock source (PRECS),
and high speed peripheral clocks are shut down the PLL (PLLPD), put the relaxation
disabled and the high-speed peripheral oscillator in Standby mode (ROSB), and put the
option is not available. System and large regulator in Standby (LRSTDBY). The part
peripheral clocks operate at 100kHz. is fully operational, but operating at a minimum
frequency and power configuration. Recovery
requires reversing the sequence used to enter
this mode (allowing for PLL lock time).
Power-Down Master clock generation in the OCCS is The user configures the OCCS and SIM to enter
completely shut down. All system and Standby mode as shown in the previous
peripheral clocks are disabled. description, followed by powering down the
oscillator (ROPD). The only possible recoveries
from this mode are:
1. External Reset
2. Power-On Reset

The power modes provide additional means to disable clock domains, configure the voltage regulator, and
configure clock generation to manage power utilization, as shown in Table 6-3. Run, Wait, and Stop
modes provide means of enabling/disabling the peripheral and/or core clocking as a group. Stop disable
controls are provided for selected peripherals in the control register so that these peripheral clocks can
optionally continue to operate in Stop mode and generate interrupts which will return the part from Stop
to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is
possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.
A 200kHz clock external clock can optionally be used in Standby mode to produce the required Standby
100kHz system bus rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully
disables the part and minimizes its power utilization but is only recoverable via reset.
When the PLL is not selected and the system bus is operating at around 100kHz, the large regulator can
be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator.

56F8013/56F8011 Data Sheet, Rev. 12

80 Freescale Semiconductor
 Resets

All peripherals, except the COP/watchdog timer, run at the system clock (peripheral bus) frequency1,
which is the same as the main processor frequency in this architecture. The COP timer runs at
MSTR_OSC / 1024. The maximum frequency of operation is SYS_CLK = 32MHz. The only exception is
the Quad Timer and PWM, which can be configured to operate at three times the system bus rate using
TCR and PCR controls, provided the PLL is active and selected.

6.6 Resets
The SIM supports four sources of reset, as shown in Figure 6-15. The two asynchronous sources are the
external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset,
which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, and the COP
reset. The SIM uses these to generate resets for the internal logic. These are outlined in Table 6-4. The
first column lists the four primary resets which are calculated. The JTAG circuitry is reset by the Power-On
Reset. Columns two through five indicate which reset sources trigger these reset signals. The last column
provides additional detail.

Table 6-4 Primary System Resets

Reset Sources

Reset Signal POR External Software COP Comments

EXTENDED_POR X Stretched version of POR. Relevant 64

Relaxation Oscillator Clock cycles after
POR deasserts.

CLKGEN_RST X X X X Released 32 Relaxation Oscillator Clock

cycles after all reset sources have
released.

PERIP_RST X X X X Releases 32 Relaxation Oscillator Clock

cycles after the CLKGEN_RST is
released.

CORE_RST X X X X Releases 32 SYS_CLK periods after

PERIP_RST is released.

Figure 6-15 provides a graphic illustration of the details in Table 6-4. Note that the POR_Delay blocks
use the Relaxation Oscillator Clock as their time base since other system clocks are inactive during this
phase of reset.

1. The Quad Timer and PWM modules can be operated at three times the IPBus clock frequency.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 81
 EXTENDED_POR
JTAG

POR
Power-On
Reset pulse shaper Memory
(active Delay 64 Subsystem
CLKGEN_RST
low) MSTR_OSC OCCS
Clocks

COMBINED_RST
External
RESET IN RESET Delay 32 PERIP_RST
Peripherals
(active MSTR_OSC
low) Clocks
pulse shaper
Delay 32
COP sys clocks
(active
low) SW Reset pulse shaper 56800E
Delay 32
sys clocks

pulse shaper
Delay blocks assert immediately and
deassert only after the programmed
CORE_RST
number of clock cycles.

Figure 6-15 Sources of RESET Functional Diagram (Test modes not included)

POR resets are extended 64 MSTR_OSC clocks to stabilize the power supply. All resets are subsequently
extended for an additional 32 MSTR_OSC clocks and 64 system clocks as the various internal reset
controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset
from when power comes on to when code is running is 28μS. An external reset generation chip may also
be used. Resets may be asserted asynchronously, but they are always released internally on a rising edge
of the system clock.

56F8013/56F8011 Data Sheet, Rev. 12

82 Freescale Semiconductor
 Clocks

6.7 Clocks
The memory, peripheral and core clocks all operate at the same frequency (32MHz max) with the
exception of the Quad Timer and PWM peripheral clocks, which have the option (using TCR and PCR) to
operate three times faster. The SIM is responsible for stalling individual clocks as a response to various
hold-off requests, low power modes, and other configuration parameters. The SIM has access to the
following signals from the OCCS module:
MSTR_OSC This comes from the input clock source mux of the OCCS. It is the output of the
relaxation oscillator or the external clock source, depending on PRECS. It is not
guaranteed to be at 50% duty cycle (+ or - 10% can probably be assumed for design
purposes). This clock runs continuously, even during resetm and is used for reset
generation.
HS_PERF The PLL multiplies the MSTR_OSC by 24, to a maximum of 192MHz. The ZSRC
field in OCCS selects the active source to be the PLL. This is divided by 2 and
postscaled to produce this maximum 96MHz clock. It is used without further division
to produce the high-speed (3x system bus rate) variants of the Quad Timer and PWM
peripheral clocks. This clock is disabled when ZSRC is selecting MSTR_OSC.
SYS_CLK_x2 The PLL can multiply the MSTR_OSC by 24, to a maximum of 192MHz. When the
PLL is selected by the OCCS ZSRC field, the PLL is divided by three and postscaled
to produce this maximum 64MHz clock. When MSTR_OSC is selected by the OCCS
ZSRC field, MSTR_OSC feeds SYS_CLK_x2 directly. The SIM takes this clock and
divides it by two to generate all the normal (1x system bus rate) peripheral and system
clocks.

While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks,
the ADC standby and conversion clocks are generated by a direct interface between the ADC and the
OCCS module.
Figure 6-16 illustrates clock relationships to one another and to the various resets as the device comes out
of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external
reset, COP and Software reset). In the 56F8013/56F8011 architecture, this signal will be stretched by the
SIM for a period of time (up to 96 MSTR_OSC clock cycles, depending upon the status of the POR) to
create the clock generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST
synchronously with the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is
delayed 32 SYS_CLK cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then
delayed by 32 SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be
released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is
necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E
core becoming active.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 83
 Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles
for combined reset extension

RST

MSTR_OSC

Switch on falling OSC_CLK

96 MSTR_OSC cycles

CKGEN_RST

SYS_CLK_x2

SYS_CLK

SYS_CLK_D

SYS_CLK_DIV2
32 SYS_CLK cycles delay Switch on falling SYS_CLK

PERIP_RST

Switch on falling SYS_CLK

32 SYS_CLK cycles delay

CORE_RST

Figure 6-16 Timing Relationships of Reset Signal to Clocks

6.8 Interrupts
The SIM generates no interrupts.

Part 7 Security Features

The 56F8013/56F8011 offers security features intended to prevent unauthorized users from reading the
contents of the flash memory (FM) array. The 56F8013/56F8011’s flash security consists of several
hardware interlocks that prevent unauthorized users from gaining access to the flash array.
After flash security is set, an authorized user is still able to access on-chip memory if the user purposely
includes a subroutine to read and transfer the contents of internal memory via serial communication
peripherals, as this code would defeat the purpose of security.

7.1 Operation with Security Enabled

After the user has programmed the flash with his application code, the 56F8013/56F8011 can be secured
by programming a security word ($E70A) into program memory location $00 1FF7. This nonvolatile word
will keep the device secured through reset and through power-down of the device. Refer to the flash

56F8013/56F8011 Data Sheet, Rev. 12

84 Freescale Semiconductor
 Flash Access Lock and Unlock Mechanisms

memory chapter in MC56F8000RM, the 56F8000 Peripheral Reference Manual for details. When flash
security mode is enabled, the 56F8013/56F8011 will disable the core EOnCE debug capabilities. Normal
program execution is otherwise unaffected.

7.2 Flash Access Lock and Unlock Mechanisms

There are several methods that effectively lock or unlock the on-chip flash.

7.2.1 Disabling EOnCE Access

On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE
port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active
and provides the chip’s boundary scan capability and access to the ID register, but proper implementation
of flash security will block any attempt to access the internal flash memory via the EOnCE port when
security is enabled.

7.2.2 Flash Lockout Recovery Using JTAG

If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash
contents, including the configuration field, thus disabling security (the protection register is cleared). This
does not compromise security, as the entire contents of the user’s secured code stored in flash are erased
before security is disabled on the device on the next reset or power-up sequence.
To start the lockout recovery sequence via JTAG, the JTAG public instruction
(LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register.
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock
divider value must be shifted into the corresponding 7-bit data register. After the data register has been
updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout
sequence to commence. The controller must remain in this state until the erase sequence has completed.
Refer to MC56F8000RM, the 56F8000 Peripheral Reference Manual, for more details, or contact
Freescale.
Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
and the device to return to normal unsecured operation. Power-on reset will also reset both.

7.2.3 Flash Lockout Recovery Using CodeWarrior

CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by
Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory configuration
file. The command Unlock_Flash_on_Connect1 in the .cfg file accomplishes the same task as using the
Debug menu.
This lockout recovery mechanism also includes the complete erasure of the internal flash contents,
including the configuration field, thus disabling security (the protection register is cleared).

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 85
7.2.4 Flash Lockout Recovery Without Mass Erase
The user can un-secure a secured device by programming the word $0000 into program memory location
$00 1FF7. After completing the programming, both the JTAG TAP controller and the device must be
reset in order to return to normal unsecured operation. Power-on reset will also reset both.
The user is responsible for directing the device to invoke the flash programming subroutine to reprogram
the word $0000 into program memory location $00 1FF7. This is done by, for example, toggling a specific
pin, or by downloading a user-defined key through serial interfaces.
Note: Flash contents can only be programmed for 1s to 0s.

7.3 Product Analysis

The recommended method of unsecuring a secured device for product analysis of field failures is via the
method suggested in Section 7.2.4. The customer would need to supply Technical Support with the details
of the protocol to access the subroutines in flash. An alternative method for performing analysis on a
secured device would be to mass-erase and reprogram the flash with the original code, but also either
modify the security word or else not program the security word.

Part 8 General Purpose Input/Output (GPIO)

8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F801X Peripheral User
Manual and contains only chip-specific information. This information supercedes the generic information
in the 56F801X Peripheral User Manual.

8.2 Configuration
There are four GPIO ports defined on the 56F8013/56F8011. The width of each port, the associated
peripheral and reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown
in Table 8-2.

56F8013/56F8011 Data Sheet, Rev. 12

86 Freescale Semiconductor
 Configuration

Table 8-1 GPIO Ports Configuration

Available Pins in
GPIO Port Peripheral Function Reset Function
56F8013/56F8011

A 8 PWM, Reset GPIO, except GPIOA7

B 8 SPI, SCI, Timer GPIO

C 6 ADC (GPIOC3 and GPIOC7 are not Analog

bonded out on the 56F8013/56F8011)

D 4 JTAG JTAG

Table 8-2 GPIO External Signals Map

Pins in shaded rows are not available in 56F8013/56F8011

LQFP
GPIO Function Peripheral Function Notes
Package Pin

GPIOA0 PWM0 29 Defaults to A0

GPIOA1 PWM1 28 Defaults toA1

GPIOA2 PWM2 23 Defaults to A2

GPIOA3 PWM3 24 Defaults to A3

GPIOA4 PWM4 / FAULT1 / T2 22 SIM register SIM_GPS is used to select

between PWM4, FAULT1, and T2
Defaults to A4

GPIOA5 PWM5 / FAULT2 / T3 20 SIM register SIM_GPS is used to select

between PWM5, FAULT2, and T3
Defaults to A5

GPIOA6 FAULT0 18 Defaults to A6

GPIOA7 RESET 15 Defaults to RESET

GPIOB0 SCLK / SCL 21 SIM register SIM_GPS is used to select

between SCLK and SCL
Defaults to B0

GPIOB1 SS / SDA 2 SIM register SIM_GPS is used to select

between SS and SDA
Defaults to B1

GPIOB2 MISO / T2 17 SIM register SIM_GPS is used to select

between MISO and T2
Defaults to B2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 87
 Table 8-2 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8013/56F8011

LQFP
GPIO Function Peripheral Function Notes
Package Pin

GPIOB3 MOSI / T3 16 SIM register SIM_GPS is used to select

between MOSI and T3
Defaults to B3

GPIOB4 T0 / CLKO 19 SIM register SIM_GPS is used to select

between T0 and CLKO
Defaults to B4

GPIOB5 T1 / FAULT3 4 SIM register SIM_GPS is used to select

between T1 and FAULT3
Defaults to B5

GPIOB6 RXD / SDA / CLKIN 1 SIM register SIM_GPS is used to select

between RXD and SDA. CLKIN
functionality is enabled using the PLL
Control Register within the OCCS block.
Defaults to B6

GPIOB7 TXD / SCL 3 SIM register SIM_GPS is used to select

between TXD and SCL
Defaults to B7

GPIOC0 ANA0 12 Defaults to ANA0

GPIOC1 ANA1 11 Defaults to ANA1

GPIOC2 ANA2 / VREFH 10 Defaults to ANA2

GPIOC3 ANA3 Not bonded out in 56F8013/56F8011

Defaults to ANA3

GPIOC4 ANB0 5 Defaults to ANB0

GPIOC5 ANB1 6 Defaults to ANB1

GPIOC6 ANB2 / VREFL 7 Defaults to ANB2

GPIOC7 ANB3 Not bonded out in 56F8013/56F8011

Defaults to ANB3

GPIOD0 TDI 30 Defaults to TDI

GPIOD1 TDO 32 Defaults to TDO

GPIOD2 TCK 14 Defaults to TCK

GPIOD3 TMS 31 Defaults to TMS

8.3 Reset Values

Tables 4-18 through 4-21 detail registers for the 56F8013/56F8011; Figures 8-1 through 8-4 summarize
register maps and reset values.

56F8013/56F8011 Data Sheet, Rev. 12

88 Freescale Semiconductor
 Reset Values

Add.
Register Acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset

R 0 0 0 0 0 0 0 0
PU
$0 GPIOA_PUPEN W
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0
D
$1 GPIOA_DATA W
RS 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0
DD
$2 GPIOA_DDIR W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
PE
$3 GPIOA_PEREN W
RS 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IA
$4 GPIOA_IASSRT W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IEN
$5 GPIOA_IEN W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IEPOL
$6 GPIOA_IEPOL W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IPR
$7 GPIOA_IPEND W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IES
$8 GPIOA_IEDGE W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
OEN
$9 GPIOA_PPOUTM W
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0 RAW DATA
$A GPIOA_RDATA W
RS X X X X X X X X X X X X X X X X

R 0 0 0 0 0 0 0 0
DRIVE
$B GPIOA_DRIVE W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 Read as 0
W Reserved
RS Reset

Figure 8-1 GPIOA Register Map Summary

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 89
 Add.
Register Acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset

R 0 0 0 0 0 0 0 0
PU
$0 GPIOB_PUPEN W
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0
D
$1 GPIOB_DATA W
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0
DD
$2 GPIOB_DDIR W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
PE
$3 GPIOB_PEREN W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IA
$4 GPIOB_IASSRT W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IEN
$5 GPIOB_IEN W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IEPOL
$6 GPIOB_IEPOL W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IPR
$7 GPIOB_IPEND W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IES
$8 GPIOB_IEDGE W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
OEN
$9 GPIOB_PPOUTM W
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0 RAW DATA
$A GPIOB_RDATA W
RS X X X X X X X X X X X X X X X X

R 0 0 0 0 0 0 0 0
DRIVE
$B GPIOB_DRIVE W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 Read as 0
W Reserved
RS Reset

Figure 8-2 GPIOB Register Map Summary

56F8013/56F8011 Data Sheet, Rev. 12

90 Freescale Semiconductor
 Reset Values

Add.
Register Acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset

R 0 0 0 0 0 0 0 0
PU
$0 GPIOC_PUPEN W
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0
D
$1 GPIOC_DATA W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
DD
$2 GPIOC_DDIR W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
PE
$3 GPIOC_PEREN W
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0
IA
$4 GPIOC_IASSRT W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IEN
$5 GPIOC_IEN W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IEPOL
$6 GPIOC_IEPOL W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IPR
$7 GPIOC_IPEND W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
IES
$8 GPIOC_IEDGE W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0
OEN
$9 GPIOC_PPOUTM W
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0 RAW DATA
$A GPIOC_RDATA W
RS X X X X X X X X X X X X X X X X

R 0 0 0 0 0 0 0 0
DRIVE
$B GPIOC_DRIVE W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 Read as 0
W Reserved
RS Reset

Figure 8-3 GPIOC Register Map Summary

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 91
 Add.
Register Acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset

R 0 0 0 0 0 0 0 0 0 0 0 0
PU
$0 GPIOD_PUPEN W
RS 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

R 0 0 0 0 0 0 0 0 0 0 0 0 D
$1 GPIOD_DATA W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0 0 0 0 0
DD
$2 GPIOD_DDIR W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0 0 0 0 0
PE
$3 GPIOD_PEREN W
RS 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

R 0 0 0 0 0 0 0 0 0 0 0 0
IA
$4 GPIOD_IASSRT W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0 0 0 0 0 IEN
$5 GPIOD_IEN W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0 0 0 0 0 IEPOL
$6 GPIOD_IEPOL W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0 0 0 0 0
IPR
$7 GPIOD_IPEND W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0 0 0 0 0
IES
$8 GPIOD_IEDGE W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0 0 0 0 0
OEN
$9 GPIOD_PPOUTM W
RS 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

R 0 0 0 0 0 0 0 0 0 0 0 0 RAW DATA
$A GPIOD_RDATA W
RS X X X X X X X X X X X X X X X X

R 0 0 0 0 0 0 0 0 0 0 0 0
DRIVE
$B GPIOD_DRIVE W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R 0 Read as 0
W Reserved
RS Reset

56F8013/56F8011 Data Sheet, Rev. 12

92 Freescale Semiconductor
 56F8013/56F8011 Information

Figure 8-4 GPIOD Register Map Summary

Part 9 Joint Test Action Group (JTAG)

9.1 56F8013/56F8011 Information
Please contact your Freescale sales representative or authorized distributor for device/package-specific
BSDL information.
The TRST pin is not available in this package. The pin is tied to VDD in the package.
The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high
for five rising edges of TCK, as described in the 56F801X Peripheral User Manual.

Part 10 Specifications
10.1 General Characteristics
The 56F8013/56F8011 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital
inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and
5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the
power savings of 3.3V I/O levels, combined with the ability to receive 5V levels without damage.
Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum
is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to
the device.
Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to
125ºC ambient temperature over the following supply ranges:
VSS = VSSA = 0V, VDD = VDDA = 3.0–3.6V, CL < 50pF, fOP = 32MHz
Note: The 56F8011 device is specified to meet Industrial requirements only.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 93
 CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.

Table 10-1 Absolute Maximum Ratings

(VSS = 0V, VSSA = 0V)

Characteristic Symbol Notes Min Max Unit

Supply Voltage Range VDD -0.3 4.0 V

Analog Supply Voltage Range VDDA - 0.3 4.0 V

ADC High Voltage Reference VREFH - 0.3 4.0 V

Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V

Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V

Input Voltage Range (Digital inputs) VIN Pin Groups 1, 2 - 0.3 6.0 V

Input Voltage Range (ADC inputs)1 VINA Pin Group 3 - 0.3 4.0 V

Input clamp current, per pin (VIN < 0)2 VIC - -20 mA

Output clamp current, per pin (VO < 0)2 VOC - -20 mA

Output Voltage Range VOUT Pin Group 1 -0.3 4.0 V

(Normal Push-Pull mode)

Output Voltage Range VOUTOD Pin Groups 1, 2 -0.3 6.0 V

(Open Drain mode)

Ambient Temperature (Automotive) TA -40 125 °C

Ambient Temperature (Industrial) TA -40 105 °C

Junction Temperature (Automotive) TJ -40 150 °C

Junction Temperature (Industrial) TJ -40 125 °C

Storage Temperature (Automotive) TSTG -55 150 °C

Storage Temperature (Industrial) TSTG -55 150 °C

1. Pin Group 3 can tolerate 6V for less than 5 seconds when they are configured as ADC inputs or during reset. Pin Group 3 can
tolerate 6V if they are configured as GPIO.
2. Continuous input current per pin is -2 mA

56F8013/56F8011 Data Sheet, Rev. 12

94 Freescale Semiconductor
 General Characteristics
Default Mode
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
Pin Group 2: RESET, GPIOA7
Pin Group 3: ADC Analog Inputs

10.1.1 ElectroStatic Discharge (ESD) Model

Table 10-2 56F8013/56F8011 ESD Protection

Characteristic Min Typ Max Unit

ESD for Human Body Model (HBM) 2000 — — V

ESD for Machine Model (MM) 200 — — V

ESD for Charge Device Model (CDM) 750 — — V

Table 10-3 LQFP Package Thermal Characteristics6

Value
Characteristic Comments Symbol Unit Notes
(LQFP)

Junction to ambient Single layer board

RθJA 74 °C/W 1,2
Natural convection (1s)

Junction to ambient Four layer board RθJMA 50 °C/W 1,3

Natural convection (2s2p)

Junction to ambient Single layer board RθJMA 67 °C/W 1,3

(@200 ft/min) (1s)

Junction to ambient Four layer board RθJMA 46 °C/W 1,3

(@200 ft/min) (2s2p)

Junction to board RθJB 23 °C/W 4

Junction to case RθJC 20 °C/W 5

Junction to package top Natural Convection ΨJT 4 °C/W 6

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESC51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the
top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
7. See Section 12.1 for more details on thermal design considerations.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 95
 Table 10-4 Recommended Operating Conditions
(VREFL = 0V, VSSA = 0V, VSS = 0V )

Characteristic Symbol Notes Min Typ Max Unit

Supply voltage VDD 3 3.3 3.6 V
ADC Supply voltage VDDA 3 3.3 3.6 V
ADC High Voltage Reference VREFH 3 — VDDA V
Voltage difference VDD to VDDA ΔVDD -0.1 0 0.1 V
Voltage difference VSS to VSSA ΔVSS -0.1 0 0.1 V
Device Clock Frequency FSYSCLK — MHz
Using relaxation oscillator 8 32
Using external clock source 0 32
Input Voltage High (digital inputs) VIH Pin Groups 1, 2 2 — 5.5 V
Input Voltage Low (digital inputs) VIL Pin Groups 1, 2 -0.3 — 0.8 V
Output Source Current High (at VOH min.) IOH mA
When programmed for low drive strength Pin Group 1 — — -4
When programmed for high drive strength Pin Group 1 — — -8
Output Source Current Low (at VOL max.) IOL mA
When programmed for low drive strength Pin Groups 1, 2 — — 4
When programmed for high drive strength Pin Groups 1, 2 — — 8
Ambient Operating Temperature TA -40 — 125 °C
(Automotive)
Ambient Operating Temperature (Industrial) TA -40 — 105 °C

Flash Endurance NF TA = -40°C to 10,000 — — Cycles

(Program Erase Cycles) 105°C
Flash Data Retention TR TJ <= 85°C avg 15 — — Years
Flash Data Retention with <100 tFLRET TJ <= 85°C avg 20 — — Years
Program/Erase Cycles

Note: Total chip source or sink current cannot exceed 50mA

Default Mode
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
Pin Group 2: RESET, GPIOA7
Pin Group 3: ADC analog inputs

56F8013/56F8011 Data Sheet, Rev. 12

96 Freescale Semiconductor
 DC Electrical Characteristics

10.2 DC Electrical Characteristics

Table 10-5 DC Electrical Characteristics

At Recommended Operating Conditions

Test
Characteristic Symbol Notes Min Typ Max Unit
Conditions

Output Voltage High VOH Pin Group 1 2.4 — — V IOH = IOHmax

Output Voltage Low VOL Pin Groups 1, 2 — — 0.4 V IOL = IOLmax

Digital Input Current High IIH Pin Groups 1, 2 — 0 +/- 2.5 μA VIN = 2.4V to
pull-up enabled or disabled1 5.5V

Digital Input Current Low IIL Pin Groups 1, 2 μA VIN = 0V

pull-up enabled -15 -30 -60
pull-up disabled1 — 0 +/- 2.5

Output Current IOZ Pin Groups 1, 2 — 0 +/- 2.5 μA VOUT = 2.4V to

High Impedance State1 5.5V or 0V

Schmitt Trigger Input Hysteresis VHYS Pin Groups 1, 2 — 0.35 — V —

Input Capacitance CIN — 10 — pF —

Output Capacitance COUT — 10 — pF —

1. See Figure 10-1
Default Mode
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
Pin Group 2: RESET, GPIOA7
Pin Group 3: ADC Analog Inputs

2.0
0.0
- 2.0
µA

- 4.0
- 6.0
- 8.0
- 10.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Volt

Figure 10-1 IIN/IOZ vs. VIN (Typical; Pull-Up Disabled)

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 97
 Table 10-6 Current Consumption per Power Supply Pin (Typical)
Typical @ 3.3V, 25°C Maximum@ 3.6V, 25°C
Mode Conditions
IDD1 IDDA IDD1 IDDA

RUN 32MHz Device Clock 42mA 13.5mA — —

Relaxation Oscillator on
PLL powered on
Continuous MAC instructions with fetches from
Program Flash
All peripheral modules enabled. Quad Timer and
PWM using 1x Clock
ADC powered on and clocked

WAIT 32MHz Device Clock 17mA 0μA — —

Relaxation Oscillator on
PLL powered on
Processor Core in WAIT state
All Peripheral modules enabled. Quad Timer and
PWM using 1x Clock
ADC powered off

STOP 4MHz Device Clock 5mA 0μA — —

Relaxation Oscillator on
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC powered off

STANDBY > 100KHz Device Clock 430μA 0μA 550μA 1μA

STOP Relaxation Oscillator in Standby mode
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC powered off
Voltage regulator in Standby mode

POWER- Device Clock is off 300μA 0μA 400μA 1μA

DOWN Relaxation Oscillator powered off
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC powered off
Voltage Regulator in Standby mode
1. No Output Switching
All ports configured as inputs
All inputs Low
No DC Loads

56F8013/56F8011 Data Sheet, Rev. 12

98 Freescale Semiconductor
 AC Electrical Characteristics

Table 10-7 Power-On Reset Low-Voltage Parameters

Characteristic Symbol Min Typ Max Unit

Low-Voltage Interrupt for 3.3V supply1 VEI3.3 2.58 2.7 — V

Low-Voltage Interrupt for 2.5V supply2 VE12.5 — 2.15 — V

Low-Voltage Interrupt Recovery Hysteresis VEIH — 50 — mV

Power-On Reset3 POR — 1.8 1.9 V

1. When VDD drops below VEI3.3, an interrupt is generated.

2. When VDD drops below VEI32.5, an interrupt is generated.
3. Power-On Reset occurs whenever the internally regulated 2.5V digital supply drops below 1.8V. While
power is ramping up, this signal remains active for as long as the internal 2.5V is below 2.15V or the 3.3V
1/O voltage is below 2.7V, no matter how long the ramp-up rate is. The internally regulated voltage is
typically 100mV less than VDD during ramp-up until 2.5V is reached, at which time it self-regulates.

10.2.1 Voltage Regulator Specifications

The 56F8013/56F8011 have two on-chip regulators. One supplies the PLL and relaxation oscillator. It has
no external pins and therefore has no external characteristics which must be guaranteed (other than proper
operation of the device). The second regulator supplies approximately 2.5V to the 56F8013/56F8011’s
core logic. This regulator requires an external 2.2μF, or greater, capacitor for proper operation. Ceramic
and tantalum capacitors tend to provide better performance tolerances. The output voltage can be
measured directly on the VCAP pin. The specifications for this regulator are shown in Table 10-8.

Table 10-8. Regulator Parameters

Characteristic Symbol Min Typical Max Unit

Short Circuit Current ISS — 450 650 mA

Short Circuit Tolerance TRSC — — 30 Minutes

(output shorted to ground)

10.3 AC Electrical Characteristics

Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified,
propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured
between the 10% and 90% points, as shown in Figure 10-2.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 99
 VIH Low High
90%
Input Signal Midpoint1 50%
10%
Fall Time VIL Rise Time

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 10-2 Input Signal Measurement References

Figure 10-3 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH

Data1 Valid Data2 Valid Data3 Valid

Data1 Data2 Data3

Data
Data Invalid State
Tri-stated
Data Active Data Active

Figure 10-3 Signal States

10.4 Flash Memory Characteristics

Table 10-9 Flash Timing Parameters

Characteristic Symbol Min Typ Max Unit

Program time1 Tprog 20 — 40 μs

Erase time 2 Terase 20 — — ms

Mass erase time Tme 100 — — ms

1. There is additional overhead which is part of the programming sequence. See the 56F801X Peripheral User Manual
for details.
2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory.

56F8013/56F8011 Data Sheet, Rev. 12

100 Freescale Semiconductor
 External Clock Operation Timing

10.5 External Clock Operation Timing

Table 10-10 External Clock Operation Timing Requirements1

Characteristic Symbol Min Typ Max Unit

Frequency of operation (external clock driver)2 fosc 4 8 8 MHz

Clock Pulse Width3 tPW 6.25 — — ns

External Clock Input Rise Time4 trise — — 3 ns

External Clock Input Fall Time5 tfall — — 3 ns

1. Parameters listed are guaranteed by design.
2. See Figure 10-4 for details on using the recommended connection of an external clock driver.
3. The high or low pulse width must be no smaller than 6.25ns or the chip may not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.

VIH
External 90% 90%
50% 50%
Clock 10% 10%
tfall trise VIL
tPW tPW

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 10-4 External Clock Timing

10.6 Phase Locked Loop Timing

Table 10-11 PLL Timing

Characteristic Symbol Min Typ Max Unit

Internal reference relaxation oscillator frequency for frosc — 8 — MHz

the PLL

PLL output frequency1 (24 x reference frequency) fop — 192 — MHz

PLL lock time2 tlock — 40 100 µs

Cycle-to-cycle jitter tjitterpll 350 ps

1. The core system clock will operate at 1/6 of the PLL output frequency.
2. This is the time required after the PLL is enabled to ensure reliable operation.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 101
10.7 Relaxation Oscillator Timing

Table 10-12 Relaxation Oscillator Timing

Characteristic Symbol Minimum Typical Maximum Unit

Relaxation Oscillator output frequency fop — —

Normal Mode1 8.05 MHz
Standby Mode 200 kHz

Relaxation Oscillator stabilization time2 troscs — 1 3 µs

Cycle-to-cycle jitter. This is measured on the tjitterrosc — 400 ps

CLKO signal (programmed prescaler_clock)
over 264 clocks3
Minimum tuning step size .08 %
Maximum tuning step size 40 %

Variation over temperature –40°C to 150°C4 +1.0 to –1.5 +3.0 to –3.0 %

Variation over temperature 0°C to 105°C4 0 to +1 +2.0 to –2.0 %

Variation over temperature –40°C to 150°C4 +1.0 to -1.5 +3.0 to –4.5 %

(MC56F8013MFAE)
1. Output frequency after factory trim.
2. This is the time required from standby to normal mode transition.
3. JA is required to meet SCI requirements.
4. See Figure 10-5.

56F8013/56F8011 Data Sheet, Rev. 12

102 Freescale Semiconductor
 Reset, Stop, Wait, Mode Select, and Interrupt Timing

8.16

8.08

8
MHz

7.92

7.84
-50 -25 0 25 50 75 100 125 150 175

Degrees C (Junction)

Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Factory Trim

10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Note: All the address and data buses described here are internal.

Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
Characteristic Symbol Typical Min Typical Max Unit See Figure

Minimum RESET Assertion Duration tRA 4T — ns

Minimum GPIO pin Assertion for Interrupt tIW 2T — ns 10-6

RESET deassertion to First Address Fetch3 tRDA 96TOSC + 64T 97TOSC + 65T ns

Delay from Interrupt Assertion to Fetch of first tIF — 6T ns

instruction (exiting Stop)
1. In the formulas, T = clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At 8MHz
(used during Reset and Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the 56F8013/56F8011 internal reset stretching circuitry to extend this period to
2^21T.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 103
 GPIO pin
(Input)
TIW

Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)

56F8013/56F8011 Data Sheet, Rev. 12

104 Freescale Semiconductor
 Serial Peripheral Interface (SPI) Timing

10.9 Serial Peripheral Interface (SPI) Timing

Table 10-14 SPI Timing1

Characteristic Symbol Min Max Unit See Figure

Cycle time tC 10-7, 10-8,

Master 125 — ns 10-9, 10-10
Slave 62.5 — ns

Enable lead time tELD 10-10

Master — — ns
Slave 31 — ns

Enable lag time tELG 10-10

Master — — ns
Slave 125 — ns

Clock (SCK) high time tCH 10-7, 10-8,

Master 50 — ns 10-9, 10-10
Slave 31 — ns

Clock (SCK) low time tCL 10-10

Master 50 — ns
Slave 31 — ns

Data set-up time required for inputs tDS 10-7, 10-8,

Master 20 — ns 10-9, 10-10
Slave 0 — ns

Data hold time required for inputs tDH 10-7, 10-8,

Master 0 — ns 10-9, 10-10
Slave 2 — ns

Access time (time to data active from tA 10-10

high-impedance state) 4.8 15 ns
Slave

Disable time (hold time to high-impedance state) tD 10-10

Slave 3.7 15.2 ns

Data Valid for outputs tDV 10-7, 10-8,

Master — 4.5 ns 10-9, 10-10
Slave (after enable edge) — 20.4 ns

Data invalid tDI 10-7, 10-8,

Master 0 — ns 10-9, 10-10
Slave 0 — ns

Rise time tR 10-7, 10-8,

Master — 11.5 ns 10-9, 10-10
Slave — 10.0 ns

Fall time tF 10-7, 10-8,

Master — 9.7 ns 10-9, 10-10
Slave — 9.0 ns

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 105
 1. Parameters listed are guaranteed by design.
1

SS SS is held High on master

(Input)
tC
tR
tF
SCLK (CPOL = 0) tCL
(Output) tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH tCH
tDS
MISO
(Input) MSB in Bits 14–1 LSB in

tDI tDI(ref)
tDV

MOSI Master MSB out Bits 14–1 Master LSB out

(Output)
tF tR

Figure 10-7 SPI Master Timing (CPHA = 0)

56F8013/56F8011 Data Sheet, Rev. 12

106 Freescale Semiconductor
 Serial Peripheral Interface (SPI) Timing

SS SS is held High on master

(Input) tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output) tCH
tF

tCL
SCLK (CPOL = 1)
(Output) tCH
tDS
tR tDH
MISO
(Input) MSB in Bits 14–1 LSB in

tDV(ref) tDI tDV tDI(ref)

MOSI Master MSB out Bits 14– 1 Master LSB out

(Output)
tF tR

Figure 10-8 SPI Master Timing (CPHA = 1)

SS
(Input)
tC
tF tELG
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH

tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH tF
tA tR tD

MISO
(Output) Slave MSB out Bits 14–1 Slave LSB out

tDS tDV
tDI tDI
tDH
MOSI MSB in Bits 14–1 LSB in
(Input)

Figure 10-9 SPI Slave Timing (CPHA = 0)

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 107
 SS
(Input)
tF
tC
tR
SCLK (CPOL = 0) tCL
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV tCH tR
tA tF tD

MISO
(Output) Slave MSB out Bits 14–1 Slave LSB out

tDS tDV
tDI
tDH
MOSI MSB in Bits 14–1 LSB in
(Input)

Figure 10-10 SPI Slave Timing (CPHA = 1)

10.10 Quad Timer Timing

Table 10-15 Timer Timing1, 2

Characteristic Symbol Min Max Unit See Figure

Timer input period PIN 2T + 6 — ns 10-11

Timer input high / low period PINHL 1T + 3 — ns 10-11

Timer output period POUT 125 — ns 10-11

Timer output high / low period POUTHL 50 — ns 10-11

1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns.
2. Parameters listed are guaranteed by design.

56F8013/56F8011 Data Sheet, Rev. 12

108 Freescale Semiconductor
 Quad Timer Timing

Timer Inputs

PIN PINHL PINHL

Timer Outputs

POUT POUTHL POUTHL

Figure 10-11 Timer Timing

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 109
10.11 Serial Communication Interface (SCI) Timing

Table 10-16 SCI Timing1

Characteristic Symbol Min Max Unit See Figure

Baud Rate2 BR — (fMAX/16) Mbps —

RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-12

TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-13

LIN Slave Mode

Deviation of slave node clock from FTOL_UNSYNCH -14 14 %

nominal clock rate before
synchronization

Deviation of slave node clock relative FTOL_SYNCH -2 2 %

to the master node clock after
synchronization

Minimum break character length TBREAK 13 Master

node bit
periods

11 Slave node
bit periods
1. Parameters listed are guaranteed by design.
2. fMAX is the frequency of operation of the system clock in MHz, which is 32MHz for the 56F8013/56F8011 devices.
3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

RXD
Receive
data pin
(Input) RXDPW

Figure 10-12 RXD Pulse Width

TXD
Receive
data pin
(Input) TXDPW

Figure 10-13 TXD Pulse Width

56F8013/56F8011 Data Sheet, Rev. 12

110 Freescale Semiconductor
 Inter-Integrated Circuit Interface (I2C) Timing

10.12 Inter-Integrated Circuit Interface (I2C) Timing

Table 10-17 I2C Timing

Standard Mode Fast Mode
Characteristic Symbol Unit
Minimum Maximum Minimum Maximum

SCL Clock Frequency fSCL 0 100 0 400 kHz

Hold time (repeated ) tHD; STA 4.0 0.6 μs

START condition. After
this period, the first clock
pulse is generated.
LOW period of the SCL tLOW 4.7 1.25 μs
clock
HIGH period of the SCL tHIGH 4.0 0.6 μs
clock
Set-up time for a repeated tSU; STA 4.7 0.6 μs
START condition

Data hold time for I2C bus tHD; DAT 01 3.452 01 0.92 μs
devices
Data set-up time tSU; DAT 250 1003 ns

Rise time of both SDA and tr 1000 2 +0.1Cb4 300 ns

SCL signals
Fall time of both SDA and tf 300 2 +0.1Cb4 300 ns
SCL signals
Set-up time for STOP tSU; STO 4.0 0.6 μs
condition
Bus free time between tBUF 4.7 1.3 μs
STOP and START
condition
Pulse width of spikes that tSP N/A N/A 0.0 50 ns
must be suppressed by
the input filter
1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH min of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
2. The maximum tHD; DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT > = 250ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU; DAT = 1000 + 250 = 1250ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
4. Cb = total capacitance of the one bus line in pF.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 111
SDA

tSU; DAT
tLOW tHD; STA tSP tBUF

SCL

tHD; STA tSU; STA tSU; STO

S tHD; DAT tHIGH BR P S

Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I2C Bus

10.13 JTAG Timing

Table 10-18 JTAG Timing

Characteristic Symbol Min Max Unit See Figure

TCK frequency of operation1 fOP DC SYS_CLK/8 MHz 10-15

TCK clock pulse width tPW 50 — ns 10-15

TMS, TDI data set-up time tDS 5 — ns 10-16

TMS, TDI data hold time tDH 5 — ns 10-16

TCK low to TDO data valid tDV — 30 ns 10-16

TCK low to TDO tri-state tTS — 30 ns 10-16

1. TCK frequency of operation must be less than 1/8 the processor rate.

1/fOP
tPW tPW
VIH
VM VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2

Figure 10-15 Test Clock Input Timing Diagram

56F8013/56F8011 Data Sheet, Rev. 12

112 Freescale Semiconductor
 JTAG Timing

TCK
(Input)
tDS tDH

TDI
TMS Input Data Valid
(Input) tDV

TDO
(Output) Output Data Valid
tTS

TDO
(Output)

Figure 10-16 Test Access Port Timing Diagram

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 113
10.14 Analog-to-Digital Converter (ADC) Parameters
Table 10-19 ADC Parameters1
Parameter Symbol Min Typ Max Unit
DC Specifications
Resolution RES 12 — 12 Bits
ADC internal clock fADIC 0.1 — 5.33 MHz
Conversion range RAD VREFL — VREFH V

ADC power-up time2 tADPU — 6 13 tAIC cycles3

Recovery from auto standby tREC — 0 1 tAIC cycles3
Conversion time tADC — 6 — tAIC cycles3
Sample time tADS — 1 — tAIC cycles3
Accuracy
Integral non-linearity4 INL — +/- 3 +/- 5 LSB5
(Full input signal range)
Differential non-linearity DNL — +/- .6 +/- 1 LSB5
Monotonicity GUARANTEED
Offset Voltage Internal Ref VOFFSET — +/- 4 +/- 9 mV
Offset Voltage External Ref VOFFSET — +/- 6 +/- 12 mV
Gain Error (transfer gain) EGAIN — .998 to 1.002 1.01 to .99 —

ADC Inputs6 (Pin Group 3)

Input voltage (external reference) VADIN VREFL — VREFH V
Input voltage (internal reference) VADIN VSSA — VDDA V

Input leakage 7 IIA — 0 +/- 2 μA

VREFH current IVREFH — 0 — μA

Input injection current8, per pin IADI — — 3 mA

Input capacitance CADI — See Figure 10-17 — pF
Input impedance XIN — See Figure 10-17 — Ohms
AC Specifications
Signal-to-noise ratio SNR 60 65 dB
Total Harmonic Distortion THD 60 64 dB
Spurious Free Dynamic Range SFDR 61 66 dB
Signal-to-noise plus distortion SINAD 58 62 dB
Effective Number Of Bits ENOB — 10.0 Bits
1. All measurements were made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground
2. Includes power-up of ADC and VREF
3. ADC clock cycles
4. INL measured from VIN = VREFL to VIN = VREFH

56F8013/56F8011 Data Sheet, Rev. 12

114 Freescale Semiconductor
 Equivalent Circuit for ADC Inputs

5. LSB = Least Significant Bit = 0.806mV

6. Pin groups are detailed following Table 10-1.
7. For device S56F8013MFA00E, input leakage current is ± 1μA.
8. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
ADC.

10.15 Equivalent Circuit for ADC Inputs

Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (VREFH-VREFL)/2, while the other charges to the analog input voltage. When the
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches switch
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, VREF and the ADC clock frequency.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 115
 C1 : Singled Ended Mode
2 X C1 : Differential Mode

Equivalent Circuit for A/D Loading

S1
channel mux
ADC Input 125 Ohm equiv resistance
ESD Resistor 100 Ohms
S1 C1

S/H
S1
1 2 3 (VREFHx - VREFLx) / 2 C1

S1

1. Parasitic capacitance due to package, pin-to-pin and pin-to-package

S2 S2
base coupling; 1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices C1 : Singled Ended Mode
and signal routing; 2.04pF 2 X C1 : Differential Mode
3. 8 pF noise damping capacitor
4. C1 = 1.4 pF
5. S1 and S2 switch phases are non-overlapping and operate at the ADC
clock frequency

S1

S2

6. Equivalent input impedance, when the input is selected =

1
( ADC Clock Rate ) ×1.4×10 −12
+ 100ohm + 125ohm

Figure 10-17 Equivalent Circuit for A/D Loading

10.16 Power Consumption

See Section 10.1 for a list of IDD requirements for the 56F8013/56F8011. This section provides additional
detail which can be used to optimize power consumption for a given application.
Power consumption is given by the following equation:

Total power = A: internal [static component]

+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static]

A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents,
Please
PLL, seevoltage
and http://www.freescale.com for the
references. These most current
sources mechanical
operate drawing. of processor state or operating
independently

56F8013/56F8011 Data Sheet, Rev. 12

116 Freescale Semiconductor
 Power Consumption

frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the
56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading
on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two
of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero
Y-intercept.

Table 10-20 I/O Loading Coefficients at 10MHz

Intercept Slope

8mA drive 1.3 0.11mW / pF

4mA drive 1.15mW 0.11mW / pF

Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change. Table 10-20 provides coefficients for calculating power dissipated
in the I/O cells as a function of capacitive load. In these cases:
TotalPower = Σ((Intercept + Slope*Cload)*frequency/10MHz)
where:
• Summation is performed over all output pins with capacitive loads
• TotalPower is expressed in mW
• Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found
to be fairly low when averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the
device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5
for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving
10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,
as it is assumed to be negligible.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 117
Part 11 Packaging
11.1 56F8013/56F8011 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8013/56F8011. These devices come in
a 32-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the 32-pin
LQFP, Figure 11-2 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out
for the 32-pin LQFP.

GPIOA0/PWM0

GPIOA1/PWM1
TDO/GPIOD1

TMS/GPIOD3

TDI/GPIOD0

VCAP
VDD
VSS
ORIENTATION
GPIOB6/RXD/SDA/CLKIN MARK GPIOA3/PWM3
PIN 25
GPIOB1/SS/SDA GPIOA2/PWM2
PIN 1
GPIOB7/TXD/SCL
GPIOA4/PWM4/FAULT1/T2
GPIOB5/T1/FAULT3
GPIOB0/SCLK/SCL
ANB0/GPIOC4
GPIOA5/PWM5/FAULT2/T3
ANB1/GPIOC5
GPIOB4/T0/CLKO
ANB2/VREFL/GPIOC6 GPIOA6/FAULT0
PIN 17
PIN 9
VDDA GPIOB2/MISO/T2
VSS
VSSA

ANA2/VREFH/GPIOC2

ANA1/GPIOC1

ANA0/GPIOC0

TCK/GPIOD2

RESET/GPIOA7
GPIOB3/MOSI/T3

Note: Alternate signals are in italic

Figure 11-1 Top View, 56F8013/56F8011 32-Pin LQFP Package

56F8013/56F8011 Data Sheet, Rev. 12

118 Freescale Semiconductor
 56F8013/56F8011 Package and Pin-Out Information

Table 11-1 56F8013/56F8011 32-Pin LQFP Package Identification by Pin Number1

Pin Pin Pin Pin
Signal Name Signal Name Signal Name Signal Name
No. No. No. No.

1 GPIOB6 9 VSSA 17 GPIOB2 25 VCAP

RXD,SDA,CLKIN MISO,T2

2 GPIOB1 10 ANA2 18 GPIOA6 26 VDD

SS,SDA VREFH,GPIOC2 FAULT0

3 GPIOB7 11 ANA1 19 GPIOB4 27 VSS

TXD,SCL GPIOC1 T0,CLKO

4 GPIOB5 12 ANA0 20 GPIOA5 28 GPIOA1

T1,FAULT3 GPIOC0 PWM5,FAULT2,T3 PWM1

5 ANB0 13 VSS 21 GPIOB0 28 GPIOA0

GPIOC4 SCLK,SCL PWM0

6 ANB1 14 TCK 22 GPIOA4 30 TDI

GPIOC5 GPIOD2 PWM4,FAULT1,T2 GPIOD0

7 ANB2 15 RESET 23 GPIOA2 31 TMS

VREFL,GPIOC6 GPIOA7 PWM2 GPIOD3

8 VDDA 16 GPIOB3 24 GPIOA3 32 TDO

MOSI,T3 PWM3 GPIOD1
1.Alternate signals are in iltalic

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 119
 –T–, –U–, –Z–
A 4X
A1 0.20 (0.008) AB T–U Z
32 25

–T– –U–

B V AE
P
B1 DETAIL Y
8 17
V1
AE

9 DETAIL Y
4X
–Z–
9 S1 0.20 (0.008) AC T–U Z NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
S Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
DETAIL AD 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
G AT DATUM PLANE –AB–.
–AB– 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
SEATING 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PLANE
–AC– PROTRUSION. ALLOWABLE PROTRUSION IS
0.10 (0.004) AC 0.250 (0.010) PER SIDE. DIMENSIONS A AND B

AC T–U Z
BASE DO INCLUDE MOLD MISMATCH AND ARE
METAL

ÉÉ
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
N

ÉÉ
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).

ÉÉ
M

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.20 (0.008)

F D 0.0076 (0.0003).

ÉÉ
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
8X M
R J MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 7.000 BSC 0.276 BSC
A1 3.500 BSC 0.138 BSC
SECTION AE–AE B 7.000 BSC 0.276 BSC
C E B1 3.500 BSC 0.138 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
W Q G 0.800 BSC 0.031 BSC
H K H 0.050 0.150 0.002 0.006
0.250 (0.010)
GAUGE PLANE

X J 0.090 0.200 0.004 0.008

K 0.500 0.700 0.020 0.028
M 12 REF 12 REF
DETAIL AD N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1 5 1 5
R 0.150 0.250 0.006 0.010
S 9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
V 9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF

Figure 11-2 56F8013/56F8011 32-Pin LQFP Mechanical Information

56F8013/56F8011 Data Sheet, Rev. 12

120 Freescale Semiconductor
 Thermal Design Considerations

Part 12 Design Considerations

12.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJΑ x PD)
where:
TA = Ambient temperature for the package (oC)
RθJΑ = Junction-to-ambient thermal resistance (oC/W)
PD = Power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, there are two values in common usage: the value
determined on a single-layer board and the value obtained on a board with two planes. For packages such
as the PBGA, these values can be different by a factor of two. Which value is closer to the application
depends on the power dissipated by other components on the board. The value obtained on a single layer
board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the
internal planes is usually appropriate if the board has low-power dissipation and the components are well
separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = Package junction-to-ambient thermal resistance (°C/W)
RθJC = Package junction-to-case thermal resistance (°C/W)
RθCA = Package case-to-ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to
change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the
Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT x PD)
where:
TT = Thermocouple temperature on top of package (oC)
ΨJT = Thermal characterization parameter (oC/W)
PD = Power dissipation in package (W)

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 121
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.

12.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation of the 56F8013/56F8011:
• Provide a low-impedance path from the board power supply to each VDD pin on the 56F8013/56F8011 and
from the board ground to each VSS (GND) pin
• The minimum bypass requirement is to place 0.01–0.1μF capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better
tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are as short as possible

56F8013/56F8011 Data Sheet, Rev. 12

122 Freescale Semiconductor
 Electrical Design Considerations

• Bypass the VDD and VSS with approximately 100μF, plus the number of 0.1μF ceramic capacitors
• PCB trace lengths should be minimal for high-frequency signals
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA and VSSA pins
• Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA is
recommended. Connect the separate analog and digital power and ground planes as close as possible to
power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is
advisable to connect a small inductor or ferrite bead in serial with both VDDA and VSSA traces.
• It is highly desirable to physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog
ground trace around an analog signal trace to isolate it from digital traces.
• Because the Flash memory is programmed through the JTAG/EOnCE port, SPI, SCI or I2C, the designer
should provide an interface to this port if in-circuit Flash programming is desired.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor 123
 Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.

Table 13-1 56F8013/56F8011 Ordering Information

Ambient
Supply Pin Frequency
Part Package Type Temperature Order Number
Voltage Count (MHz)
Range

MC56F8013 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 32 32 –40° to + 125°C MC56F8013MFAE*

MC56F8013 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 32 32 –40° to + 125°C S568013MFA00E*

MC56F8013 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 32 32 –40° to + 105°C MC56F8013VFAE*

MC56F8011 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 32 32 –40° to + 105°C MC56F8011VFAE*

*This package is RoHS compliant.

Part 14 Appendix
Register acronyms are revised from previous device data sheets to provide a cleaner register description.
A cross reference to legacy and revised acronyms are provided in the following table.

Peripheral Reference Manual Data Sheet Processor Memory Address

New Legacy Expert
Module Register Name New Acronym Legacy Acronym Start End
Acronym Acronym Acronym

ADC Control Register 1 CTRL1 ADCR1 ADC_CTRL1 ADC_ADCR1 ADC_ADCR1 0xF080

Control Register 2 CTRL2 ADCR2 ADC_CTRL2 ADC_ADCR2 ADC_ADCR2 0xF081
Zero Crossing Control Register ZXCTRL ADZCC ADC_ZXCTRL ADC_ADZCC ADC_ADZCC 0xF082
Channel List Register 1 CLIST1 ADLST1 ADC_CLIST1 ADC_ADLST1 ADC_ADLST1 0xF083
Channel List Register 2 CLIST2 ADLST2 ADC_CLIST2 ADC_ADLST2 ADC_ADLST2 0xF084
Sample Disable Register SDIS ADSDIS ADC_SDIS ADC_ADSDIS ADC_ADSDIS 0xF085
Status Register STAT ADSTAT ADC_STAT ADC_ADSTAT ADC_ADSTAT 0xF086
Limit Status Register LIMSTAT ADLSTAT ADC_LIMSTAT ADC_ADLSTAT ADC_ADLSTAT 0xF087
Zero Crossing Status Register ZXSTAT ADZCSTAT ADC_ZXSTAT ADC_ADZCSTAT ADC_ADZCSTAT 0xF088
Result Registers 0-7 RSLT0-7 ADRSLT0-7 ADC_RSLT0-7 ADC_ADRSLT0-7 ADC_ADRSLT0-7 0xF089 0XF090
Low Limit Registers 0-7 LOLIM0-7 ADLLMT0-7 ADC_LOLIM0-7 ADC_ADLLMT0-7 ADC_ADLLMT0-7 0XF091 0XF098
High Limit Registers 0-7 HILIM0-7 ADHLMT0-7 ADC_HILIM0-7 ADC_ADHLMT0-7 ADC_ADHLMT0-7 0XF099 0XF0A0
Offset Registers 0-7 OFFST0-7 ADOFS0-7 ADC_OFFST0-7 ADC_ADOFS0-7 ADC_ADOFS0-7 0XF0A1 0XF0A8
Power Control Register PWR ADPOWER ADC_PWR ADC_ADPOWER ADC_ADPOWER 0XF0A9
Voltage Reference Register CAL ADCAL ADC_VREF ADC_ADCAL ADC_CAL 0XF0AA

COP Control Register CTRL COPCTL COP_CTRL COPCTL COPCTL 0XF0E0

Time-Out Register TOUT COPTO COP_TOUT COPTO COPTO 0XF0E1
Counter Register CNTR COPCTR COP_CNTR COPCTR COPCTR 0XF0E2

I2C Address Register ADDR IBAD I2C_ADDR I2C_IBAD IBAD 0xF0D0

Frequency Divider Register FDIV IBFD I2C_FDIV I2C_IBFD IBFD 0xF0D1
Control Register CTRL IBCR I2C_CTRL I2C_IBCR IBCR 0xF0D2

56F8013/56F8011 Data Sheet, Rev. 12

124 Freescale Semiconductor
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005, 2006, 2007, 2008. All rights reserved.

MC56F8013
Rev. 12
05/2008