DEPARTMENT OF ELECTRONICS AND COMMUNICATION

B M S COLLEGE OF ENGINEERING
(AUTONOMOUS COLLEGE UNDER VTU, BELGAUM)
BANGALORE – 560019

2021-22

6TH SEMESTER ALTERNATE ASSESSMENT - 2

IN

SYSTEM VERILOG AND VERIFICATION

(19EC6PE3SV)

BY

NAME USN
SANJANA VK 1BM19EC141

Course Instructor

Dr. Kiran Bailey

Assistant Professor
Dept. of ECE, BMSCE
 Contents
1. Design a 4-bit ALU and randomize the inputs to the design. Write assertions to test
the following:

(I) When opcode is 000, output = a + b

(II) When reset is 1, output = 0

2. Design a Moore FSM to detect the sequence 1001 without overlap. Write a test
bench environment with covergroup and coverpoints to verify the design. Randomize
the inputs appropriately using transactor class, generator class and driver class with
virtual interfaces. (Optional: Use mailboxes to communicate between generator and
driver class).

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1. Design a 4-bit ALU and randomize the inputs to the design. Write
assertions to test the following:

(I) When opcode is 000, output = a + b

(II) When reset is 1, output = 0

Design – ALU.v:

module ALU (
input clk, rst,
input [2:0] op,
input [3:0] a, b,
output reg [3:0] q
);
always @(posedge clk, posedge rst)
begin
if(rst)
begin
q <= 4'd0;
end
else
begin
case(op)
3'd0: q <= a + b;
3'd1: q <= a - b;
3'd2: q <= a * b;
3'd3: q <= a / b;
3'd4: q <= a & b;
3'd5: q <= a | b;
3'd6: q <= ~a;
3'd7: q <= (a >> 1);
default: q <= 4'bx;
endcase
end
end

endmodule

Interface – alu_inter.sv

interface alu_inter(input bit clk);

logic rst;
logic [2:0] op;
logic [3:0] a, b, q;

clocking cb @(posedge clk);

default input #1ns output #3ns;
input q;
output op, a, b;

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 endclocking
property p_rst;
@(cb) (rst == 1)|->(q == 0);
endproperty:p_rst
a1:assert property(p_rst) $display("rst held");
else $display("rst fail");

property op0;
@(cb) (op == 0)|->(q == a+b);
endproperty:op0

a2:assert property(op0) $display("add held");

else $display("add fail");
modport TB (clocking cb, output rst);
endinterface

Testbench – test.sv:

Contains transactor, driver and test blocks.

class transactor;
rand bit [3:0] op;
rand bit [4:0] a, b;
//constraint c1 {a inside {[0:10], 12, 15};}
//constraint c2 {b >= 0; b< 14;}
endclass
class driver;
transactor tx;
virtual alu_inter.TB i1;

function new(virtual alu_inter.TB i2);

this.i1 = i2;
this.tx = new();
endfunction

task drive_data();
begin
repeat (2000) @(i1.cb)
if(tx.randomize())
begin
i1.cb.op <= tx.op;
i1.cb.a <= tx.a;
i1.cb.b <= tx.b;
end
else
$display("[%d] Randomization Failed!", $time);
end
endtask
endclass
//`include "alu_inter.sv"
//`include "driver.sv"
program test(alu_inter.TB i1);
driver drv = new(i1);

initial

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 begin
i1.rst <= 1;
#10 i1.rst <= 0;
#100 i1.rst <= 1;
#20 i1.rst <= 0;
#3000 $finish;
end

initial
begin
drv.drive_data();
end
endprogram

Top Module – top.sv:

//`include "alu_inter.sv"
//`include "test.sv"
//`include "ALU.v"
module top();
bit clk;
always #5 clk = ~clk;

alu_inter io (clk);
test t1 (io);
ALU DUT (.clk(clk), .rst(io.rst), .op(io.op), .a(io.a), .b(io.b), .q(io.q));

initial
begin
$dumpfile("ALU.vcd");
$dumpvars;
end
endmodule

Simulation in Simvison:

5|Page
Assertions:
a. Add assertion held for opcode = 000:

b. Reset assertion held when rst = 0 and q = 0:

IMC Coverage Report: 98.25% Coverage

6|Page
2. Design a Moore FSM to detect the sequence 1001 without overlap. Write
a test bench environment with covergroup and coverpoints to verify the
design. Randomize the inputs appropriately using transactor class,
generator class and driver class with virtual interfaces. (Optional: Use
mailboxes to communicate between generator and driver class).

//Design
module moore101(
input clk, rst, I,

output reg [1:0] ps, ns,

output reg Y
);
// States
parameter [1:0] S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;

// Present state block

always @(posedge clk, posedge rst)
begin
if(rst)
ps <= S0;
else
ps <= ns;

end
// Next state block
always @(posedge clk , I, ps)
begin
case(ps)
S0: begin
if(I)

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 ns <= S1;
else
ns <= S0;

end
S1: begin
if(I)
ns <= S1;

else
ns <= S2;
end
S2: begin

if(I)
ns <= S3;
else
ns <= S0;

end
S3: begin
if(I)
ns <= S1;

else
ns <= S0;

end

default: ns <= S0;

endcase
end
// Output block

always @(posedge clk, ps)

begin
case(ps)
S0: Y <= 0;

S1: Y <= 0;
S2: Y <= 0;

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 S3: Y <= 1;
default: Y <= 0;
endcase

end
endmodule
//interface
interface moore101_io(input bit clk);

logic rst, I, Y;
logic [1:0] ps, ns;
clocking cb @(posedge clk);
default input #1ns output #3ns;

input Y, ps, ns;

output I;
endclocking
modport TB (clocking cb, output rst);

endinterface

test
class transactor;

rand bit I;
// constraint inp {I inside {0,1};}
endclass
//generator

class generator;
transactor tx;
virtual moore101_io.TB i1;
mailbox gen2drv;

function new(virtual moore101_io.TB i1, mailbox gen2drv);

this.i1 = i1;
this.gen2drv = gen2drv;
this.tx = new();

endfunction
task gen_data();

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 repeat (1000) @(i1.cb)
begin
if(tx.randomize())

begin
$display("[GEN] I = %d", tx.I);
end
else

begin
$display("[%d] Ramdomization Failed!", $time);
end
gen2drv.put(tx);

end
endtask
endclass
class driver;

transactor tx;
mailbox gen2drv;
virtual moore101_io.TB i1;
covergroup cg;

I: coverpoint i1.cb.I {
bins t0 = {0};
bins t1 = {1};
}

rst: coverpoint i1.rst {

bins r1 = {0};
}
ns: coverpoint i1.cb.ns {

bins t2[] = {0, 1};

bins t3[] = {2, 3};
}
ps: coverpoint i1.cb.ps {

bins t4[] = {0, 1};

bins t5[] = {2, 3};

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 }
Y: coverpoint i1.cb.Y;
endgroup

function new(virtual moore101_io.TB i1, mailbox gen2drv);

tx = new();
this.i1 = i1;
this.gen2drv = gen2drv;

this.cg = new();
endfunction
task drive_data();
begin

repeat (1000) @(i1.cb)

begin
gen2drv.get(tx);
//$display("[DRV] I = %d",i1.cb.I);

i1.cb.I <= tx.I;

cg.sample();
end
end

endtask
endclass

//testbench
program test(moore101_io.TB i1);
mailbox gen2drv = new();

driver drv = new(i1, gen2drv);

generator genr = new(i1, gen2drv);
initial
begin

i1.rst <= 0;
#10 i1.rst <= 1;

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 #50 i1.rst <= 0;
end
initial

begin
genr.gen_data();
end
initial

begin
drv.drive_data();
end
endprogram

//Top

module top;
bit clk;
always #5 clk = ~clk;
moore101_io io (clk);

moore101 DUT (.clk(clk), .rst(io.rst), .I(io.I), .ps(io.ps), .ns(io.ns), .Y(io.Y));

test t1 (io);
initial
begin

$dumpfile("moore101.vcd");
$dumpvars;
end
endmodule

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Simulation in Simvison:

IMC Coverage Report: 100% Coverage

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